lect09-cn303 [compatibility mode]

7/31/2019 Lect09-CN303 [Compatibility Mode]

1/116

CN 303

MICROPROCESSOR AND MICROCONTROLLER

Lecture#9:Interrupts


2/116

Introduction

A computer must execute one of thecollection of special routines whenever

certain conditions exits within a ro ram or

the microcomputer system.

For instance the microcomputer system

should give response to devices such as akeyboard, mouse and other components

when they request for a service.


3/116

Introduction

The most common method is polling, where theCPU tests each device in sequence and in effect

ask each one if it needs communication with a

. But polling requires that large portion of the I/O

program to continuous monitor the peripheral

devices in a loop. Polling affects system throughput ,thus affecting

number of tasks and cost effectives of a

microcomputer system.


4/116

Introduction

A more desirable method is the one that allows theCPU to execute I/O programs and stop peripheral

devices when its told by the peripheral devices.

In effect this method provides externalasynchronous input that inform the CPU to

complete the current instruction and fetch a new

routine that serves a requesting device. Once this routine completes the CPU resumes

where it left off.


5/116

Introduction

This method that causes the CPU to finishthe current instruction and fetch the new

routine that serves the re uestin device is

called INTERRUPT METHOD.

It is easy to see how throughput increases to

enhance cost effectiveness ofmicrocomputer systems through this

method.


6/116

Introduction

Microcomputer systems allow execution ofspecial routines called INTERRUPT

SERVICE ROUTINES when the receives

an interrupt.

Remember an interrupt cause a processor to

stop executing a normal program and call aspecial routine that services an interrupt.


7/116


8/116

Hardware interrupts

These are caused by externalsignals applied to the Non-

Maskable Interrupt (NMI) inputpin or the interrupt(INTR) input

pin.


9/116

Software interrupts

These are caused by a special instructionINT n(integer) or by a condition produced

in the 8086 b execution of an

instruction(Divide by zero etc).

Note that : An interrupt service

routine(ISR) is executed whenever aprocessor receives an interrupt but control is

returned to the interrupted program when

the ISR completes.


10/116

Interrupt cycle of 8086

At the end of each instruction cycle 8086checks to see if there is any interrupt

re uest if so 8086 res onds b doin the

followings;1. It decrements SP by 2 and pushes the flags on

the stack

2. It disables the INTR interrupt pin by clearing

the IF flag

3. It resets the trap flag(TF)


11/116

Interrupt cycle of 8086

4. It decrements SP by 2 again and pushes CS onthe stack

5. It decrements SP by 2 again and pushes IP on

the stack6. It executes an indirect far jump to transfer

control to the ISR by loading the CS and IP

values as start a address of the ISR7. Now the ISR is running

8. Finally an IRET instruction returns control to

the main program


12/116

ISR starting address

QuestionHow does a processor get the starting address

of the ISR?

Answer

From the INTERRUPT VECTOR TABLE

In an 8086 system the 1st

1Kbyte ofmemory from 00000H to 003FFH is

reserved for storing the starting addresses of

ISRs.


13/116


This memory block is called theINTERRUPT VECTOR (POINTER)

TABLE.

Since 4 bytes are required to store CS and

IP values for each ISR,the table can hold the

starting addresses for 256 ISRs. The starting address for each ISR is

extracted from the IVT using an integer

number a part of theINTR n instruction.


14/116


Note that : An integer is an index to the IVT andpoints to the 1st byte of the starting address.

Figure 11.1 shows typical usage of interrupts in a

typical system. Figure 11.2 (a)shows how the 256 interrupt

pointers or vectors are arranged in the memory to

create the IVT. Figure 11.2(b) gives the contents of an interrupt

vector.


15/116

Figure 11.1 Interrupt usage in atypical system


16/116

Index ADDRESS IVT

32-255 080H-3FFH Type 32-255

User interrupt vectors

5-31 014H-07FH Type 5-31

Figure 11.2(a) and (b)

eserve

4 010H-013H Type 4

overflow

3 00CH-00FH Type 3

1-Byte breakpoint

2 008H-00BH Type 2

Non-maskable

1 004H-007H Type 1

Single step

0 000H-003H Type 0Divide error


17/116

8086 IVT

Only five have explicit definitions such asdivide by zero and non-maskable interrupt.

-

in future microprocessors.

The upper 32-255 are available for

hardware and software interrupts.


18/116

Interrupt vector and IVT

When an 8086 responds to an interrupt, itautomatically goes to the specified location

in the IVT usin the su lied interru t

vector from software or hardware as anindex to the IVT to retrieve the starting

address of the ISR.

So the user has to load these starting

addresses for different ISRs at the start of

the program.


19/116

8086 Interrupt Types

Divide by zero(Type 0)When a quotient from either a DIV and IDIV

instruction is too lar e to fit in the result

register or zero;8086 automatically executetype 0 interrupt.

Single Step Interrupt(Type 1)

When a processor receives this interrupt it

executes next instruction and wait for further

instruction from a user


20/116


Then user can examine contents of memory locationsand registers, if they are correct user can tell the

processor to execute the next instruction.

.

An 8086 is used in this mode by setting the Trap

flag, once the TF is set an 8086 automatically

execute Type 1 interrupt after executing each

instruction.

But TF can be set or clear by manipulating the flag

register contents in memory using PUSHF

instruction.


21/116


Non Maskable Interrupt(Type 2)Its activated by low to high transition on 8086

NMI in ut in.

Can not be disabled by any instruction

Breakpoint Interrupt(Type 3)

Is produced by execution of INT 3 instruction,

inserting a breakpoint causes a system to

execute instructions up to breakpoint, and then

goes to the breakpoint procedure.


22/116


In the breakpoint procedure you can write aprogram to display register contents, memory

contents and other information that is required

to e ug your program.Can insert as many breakpoints as you can

Overflow Interrupt(Type 4)

Checks overflow condition after any signedarithmetic operation in the system and then

executes the INTO or INT 4 instruction.


23/116


To detect overflow in your programs put anINTO instruction after the arithmetic

instruction in the program, if OF is set

n cat ng an over ow error, t e wexecute a type 4 interrupt after executing the

INTO instruction otherwise INTO will simply

function as NOP if OF is not set.


24/116


Software Interrupts Type 0-255The INT n instruction can be used to cause the 8086 to

execute one of the 256 possible interrupt types.

For instance INT 2 executes an NMI interrupt serviceroutine, allowing to test the NMI routine without the

need to apply an external signal to the NMI input pin.

From these interrupts desired routines from different

programs in a system e.g. BIOS in IBM PC can becalled.


25/116


Software Interrupts Type 0-255IBM PCs ROM has a collection of routines,

each erformin some s ecific function such as

reading a character from the keyboard, writingcharacter to CRT.

This routines a referred to as Basic Input

Output System or BIOS.An 8086 interrupt cycle is similar for all

interrupts.


26/116


Maskable Interrupt(INTR)Is level-sensitive interrupt activated by

a l in lo ic 1 at the INTR in ut in.

Its set by an external event and cleared insidethe interrupt service procedure.

Once accepted by the 8086 the INTR input is

automatically disabled and re-enabled by theIRET instruction at the end of the interrupt

service procedure.


27/116


The microprocessor responds to the INTRinput by pulsing the INTA output in

antici ation of receivin an interru t vector

type number on data bus connection D7-D0.

Figure 11-8 shows the timing diagram for

the INTR and INTA pins of the

microprocessor.


28/116

Figure 11-8 shows the timing diagram

for the INTR and INTA pins of themicroprocessor.


29/116


There are two INTA pulses generated by thesystem that are used to insert the vector type

number on the data bus.


30/116


31/116

Interrupt Priorities

To enforce priorities;An 8086 clears the interrupt flag automatically

as art of res ondin to an interru t.

This prevents a signal on INTR input frominterrupting a higher priority ISR.

But an 8086 allows a signal on NMI input to

interrupt higher priority interrupt.

Note that : An 8086 checks internal

interrupts before it checks external

interru ts.(Divide error and NMI exam le)


32/116

Expanding Interrupt Structure

Interrupts are needed for variety ofapplications.

interrupt input pin.

But an 8086 gives only two interrupt input

pins : NMI and INTR. For applications with multiple sources of

interrupts an external device called a

priority interrupt controller(PIC) is used.


33/116

Connection between 8086 and8259


34/116

Features of 8259

1. It can manage 8 priority interrupts, equivalent toproviding 8 interrupt pins on the processor INTR

input pin.

2. It is possible to locate vector table for theseadditional interrupts anywhere in the memory

map . However, all 8 interrupts must be spaced at

the interval of 4 or 8 locations.

3. By cascading 8259s it is possible to get 64

priority interrupts.


35/116

Features of 8259

4. An interrupt mask register makes it possible tomask individual interrupt request.

5. Can be programmed to accept either the level

triggered or the edge triggered interrupt request.6. User can get the information of pending

interrupts, in-service interrupts and masked

interrupts from 8259A.7. The 8259A is designed to minimize software and

real time overhead in handling multi-level

priority interrupts.


36/116

Pin out of the 8259A PIC


37/116

8259A Pin out and functions WR

The write input connects to either the lower orupper write strobe signal in a 16-bit system or

any other bus write strobe in any size system.

RDThe read input connects to the read strobe

signal.

INT The interrupt output connects to the INTR pin

on the microprocessor from the master, and is

connected to a master IR pin on a slave.


38/116


39/116

8259A Pin out and functions

CSChip select enables the 8259A for

ro rammin and control.

CAS0-CAS2The cascade lines are used as outputs from the

master to the slaves for cascading multiple

8259As in a system.


40/116

8259A Pin out and functions SP/EN

Slave program/enable buffer is a dual-functionpin.

When the 8259A is in buffered mode, this pin

is an output that controls the data bustransceivers in a large microprocessor-based

system.

When the 8259A is not in buffered mode, thispin programs the device as a master (1) or a

slave (0).


41/116

Block diagram of 8259A


42/116


It includes eight blocks;1. Data bus buffer

.

3. Control logic

4. Interrupt request register(IIR)

5. Interrupt service register(ISR)

6. Interrupt mask register(IMR)

7. Priority resolver and

8. Cascade buffer


43/116


Data bufferAllows the 8086 to send control words to the

8259A and read a status word from the 8259A.

The 8 data bus also allows the 8259A to sendinterrupt types to the 8086.

Read/Write logic

The RD and WR control the data flow on the

bus when the device is selected by asserting its

chip select(CS) input low.


44/116


Control logicThis block as an input and output line.

request will cause it to assert its INT output pinhigh, if this pin is connected to the INTR pin of

the 8086 and if the IF flag is set then this high

signal causes the 8086 to respond to theinterrupt request.


45/116


Interrupt Request RegisterStore 8 bits to indicate interrupt inputs(IR0-

IR7) re uestin a service.

If respective bit is 1-requesting serviceotherwise if respective bit is 0-not requesting

any service.

Interrupt Service registerStores input lines(as bits) that are currently

being serviced.


46/116


Interrupt Mask RegisterStores interrupt lines(as bits) that are currently

masked.

This register can be programmed by anOCW(details later).

An interrupt that is masked by software will not

be recognized and serviced even if it set in theIRR.


47/116


Priority resolverDetermines the priority of bits set in the IRR.

ISR during the INTA input.


48/116


Cascade buffer comparatorGenerates control signals necessary for cascade

o erations and Buffer-Enable si nals.

Allows cascading of the 8259 with other 8259sto expand interrupt handling capacity to 64

levels.

If 8259s are cascaded first is a master andothers are slaves.

The 8259 can be set as a master or slave by the

SP/EN pin.


49/116


CAS0-CAS1Selects 1 out of 8 possible slaves.

inputs for slaves.When a master receives interrupt request from

other slaves(8259s) in response to the first

INTA it generates three bits on the CAS0-CAS2 lines to select 1 out of 8 possible slaves.


50/116


The slaves(8259s) accept these signals andcompare them with the code assigned to them

during initialisation.

The slave selected(which had originally placedan interrupt request to the master) then puts out

the address of the interrupt service routine

during the second and third INTA pulses from

the CPU.


51/116


SP/EN(Slave Program/Enable Buffer)This signal specifies if the 8259 acts as a master when it

is HIGH otherwise its grounded if it acts as the slave in

non- u ere mo e.

In buffered mode when the 8259 is sending the data in

response to INTA data can not be accessed by the

CPU(bse data bus buffer are disabled during interrupt

processing in large systems using buffers to drive thedata bus)

Therefore this signal is used as an output to enable data

bus buffers of the system.


52/116

Interrupt Sequence The events occurs as follows;

1. One or more INTERRUT REQUESTlines(IR0-IR7) are raised high, setting the

corres ondin IRR bit s .

2. The priority resolver checks the three registers: IRR for interrupt request,IMR for masking

bits and ISR for interrupt request being

served. It resolves the priority and sets theINT high when appropriate.

3. The CPU acknowledges the INT and responds

with an INTA pulse.


53/116

Interrupt Sequence

4. Upon receiving an INTA from the CPU,the

highest priority ISR bit is set and the

corresponding IRR bit is reset. The 8259 does

not r ve ata us ur ng t s cyc e.

5. The 8086 initiates a second INTA pulse,

during this pulse the 8259 releases a 8-bit

pointer(interrupt type) onto the data bus

where it is read by the CPU.


54/116

Interrupt Sequence

4. This completes the interrupt cycle. In the

AEOI mode the ISR bit is reset at the end of

the second INTA pulse.Otherwise,the ISR bit

rema ns set unt an appropr ate

command is issued at the end of the interrupt

subroutine.

5. Note that : The priority modes can configured

by the programmer dynamically at any time

during the main program to define the

complete interrupt service structure based on

system requirements.


55/116

Priority Modes and OtherFeatures

The various modes of operation of the 8259are;

a Full nested mode

b) Rotating priority modec) Special masked mode and

d) Polled mode


56/116


57/116

Fully nested mode

On the acknowledgement of an interrupt the8259 in this mode it will set the

corres ondin bit in ISR to revent all

interrupts of the same or low level and itwill accept higher priority interrupt requests

, then the vector address corresponding to

this interrupt is sent.


58/116

Fully nested mode

The bit in ISR will remain set until EOI isissued by the microprocessor at the of the

interru t service routines.

But if AEOI(Automatic End of Interrupt) bitis set , the bit in the ISR resets at the trailing

edge of the last INTA.


59/116

Special Fully NestedMode(SFNM)

In FNM,on the acknowledgement of aninterrupt, further interrupts from the same

level are disabled.

But in large systems with cascaded 8259sand where interrupt levels within each slave

have to be considered.

FNM disables further interrupts on the same

input level in the master.


60/116


Such that if the slave places an interruptinput to the master further interrupts to the

slave will cause the slave to lace interru ts

to the master on the same input and thesewill be neglected if the master is operating

in FNM.

SFNM avoids this problem, and its set usingICW4.


61/116


It is similar to FNM except for thefollowing differences;

1. The slave is allowed to lace further re uests

even if the interrupt request is beingserviced.(further requests are of higher

priority than request currently being serviced

and are recognized by the master whichinitiates interrupt requests to the CPU)


62/116


2. Before the master serves another ISR anon-specific EOI must be sent to the slave

to determine if it was the onl interru t to

the slave.If it is not the same interrupt request level

input to the master must be serviced again

because the slave as presented more than one

interrupt requests and an EOI must not be sent

to the master.


63/116


Otherwise if no more interrupt requests from the

slave an EOI interrupt is sent to the master

which now it is free to serve the next slave.


64/116

Rotating Priority Mode

Two types;1. Automatic rotation

,

receives a lowest priority.

Assuming IR3 has just been serviced , it

will receive the seventh priority.


65/116

Rotating Priority Mode

2. Specific rotation In this mode a device after being serviced,

device.


66/116

Special Mask Mode

In this mode , if any interrupt is in servicethen the corresponding bit remains set in

ISR and lower riorit interru ts are

inhibited But the interrupt service routines;

Can dynamically alter the priority structure

Only by inhibiting further interrupts in the

same level and allowing interrupts form all

other levels(lower and higher) during its

execution under software control that are not


67/116

Special Mask Mode

That is any interrupt can be selectivelyenabled by loading the mask register

priority requests for a portion of itsexecution but enables some of them for

another portion.


68/116

Poll Mode

In this mode the INT output is not used. Instead the microprocessor checks the status

command. After issuing a poll command the

microprocessor reads contents of 8259A

and the 8259A provides polled word and

sets ISR bit of highest priority active

interrupt request.


69/116

Polled word

I X X X X W2 W1 W0

=

I=0No interrupt request activated

W2 W1 W0Binary code of highest priority

active interrupt request


70/116


71/116

Programming the 8259A

The 8259A can be initialized with 4

ICWs,the first two are compulsory and the

other two are o tional based on modes

being used. The ICWs must be issued in a given

sequence.

After iniatilization,the 8259A can be set up

to operate in various modes by using three

different OCWs.


72/116

Programming the 8259A

However OCWs need no specific issuing

sequence.


73/116


74/116


75/116

Initialized Command Word 1ICW1


76/116


77/116

Initialized Command Word 1(ICW1)

A write command issued to the 8259 with

A0=0 and D4=1 is interpreted as ICW1,

which starts the initialization se uence.

It specifies;1. Single or multiple 8259A in the system

2. 4 or 8 bit interval between the interrupt vector

locations

3. Edge triggered or level triggered interrupts

4. ICW4 is needed or not


78/116



79/116

Initialized Command Word 2


80/116

(ICW2)

A write command following ICW1,with

A0=1 is interpreted as ICW2.

interrupt vector address of all the interrupts.


81/116



82/116



83/116

(ICW3)

ICW3 is required only if there is more than

one 8259 in the system, and if they are

cascaded ICW3 is used to load a b te to the

8259 master or slave. The byte to be loaded as an ICW3 for 8259

master or a slave is as shown in the previous

slide.



84/116

(ICW3)

When loaded to the8259 master each bit in

ICW3 indicates whether the respective IR

in ut of the master as a slave attached to it.

When loaded to the 8259 slave, bits D0-D2of ICW3 are used to assign a slave

identification code(slave ID) to the 8259.


85/116



86/116



87/116

(ICW4)

It is loaded if the D0 bit (IC 4) is set.

It specifies;

. -

nested mode2. Whether to use buffered mode or non-buffered

mode

3. Whether to use Automatic EOI or Normal EOI4. CPU used,8086/8088 or 80810


88/116

Operation Command Word 1


89/116

(OCW1)



90/116

(OCW1)

A write command to 8259 with A0=1(after

ICW2) is interpreted as OCW1.

recognition of specific interrupt requests byprogramming the IMR.

M=1 indicates that the interrupt is to be

masked and M=0 indicates that it is to beunmasked as shown in the previous slide.


91/116

Operation Command Word 2OCW2


92/116



93/116

(OCW2)

A write command with A0=1 and

D4,D3=00 is interpreted as OCW2.

-, ,

the Rotate and End of Interrupt Modes andcombinations of the two.

L2-L0 are used to specify the interrupt level

to be acted upon when the SL bit is active.


94/116

Operation Command Word 3OCW3


95/116


(OCW3)


96/116

(OCW3)

OCW3 is used to read the status of the

registers, and to set or reset the Special

Mask and Polled Modes.

The status of the Interrupt Request Register; In-Service Register and Interrupt Mask

Register of the 8259 may be read by issuing

appropriate Read Commands as describedbellow.

IRR status Read


97/116

IRR status Read

An OCW3 with RR(Read Register)=1 and

RIS(Read ISR)=0 set up the 8259 for a

status read of the interru t re uest

register(IIR). The next Read commands(all) with A0=1

cause the 8259 to send IRR status word

when the 8259 is not in the Polled Modeafter its set for IRR status read operation.

ISR status Read


98/116

ISR status Read

An OCW3 with RR(Read Register)=1 and

RIS(Read ISR)=1 set up the 8259 for a

status read of the In-Service Re ister ISR .

A subsequent Read command issued to the8259 will cause the 8259 to send ISR status

word onto the data bus.

IMR status Read


99/116

IMR status Read

A Read command issued to the 8259 with

A0=1(with RD,CS=0) causes the 8259 to

ut out the contents of the Interru t Mask

Register(IMR). OCW3 is not required for a status read of

the IMR.

IMPORTANT NOTE


100/116

IMPORTANT NOTE

The sequence shown on the flow chart must

be followed to initialize 8259A.

an ICW2 must be sent to any 8259A in thesystem.

If a system has any slave 8259s(cascade

mode) then an ICW3 must be sent to themaster, and difference ICW3 must be sent

to the slave.

IMPORTANT NOTE


101/116

IMPORTANT NOTE

If the system is an 8086,or if you want to

specify certain special conditions , then

send ICW4 to the master and to each slave.

8259A Interfacing


102/116

Fig 11.4 shows how an 8259A can be

interfaced with the 8086 microprocessor

system in minimum mode.

The 74LS138 address decoder will assert

the CS input to the 8259A when an I/O base

address is FFF0H or FFF2H on the address

bus.

The A0 input of the 8259A is used to selectone of the two internal addresses in the

device.

8259A Interfacing(Fig 11.6)


103/116

8259A Interfacing


104/116

8259A Interfacing

Since A0 is connected to system line A1,so

the system internal addresses are FFF0H

and FFF2H.

Data lines of an 8259A are connected to thelower half of the system data bus, because

the 8086 expects to receive interrupt types

on these lower eight data lines. RD and WR signals are connected to the

system RD and WR lines.

8259A Interfacing


105/116

8259A Interfacing

The interrupt request signal INT from the

8259A is connected to the INTR input of

the 8086 and INTA from 8086 is connected

to INTA on the 8259A.

Since we are using a single 8259A in the

system SP/EN pin is tied high and CAS0-

CAS2 lines are left open. The 8 IR inputs are available for interrupt

signals.

8259A Interfacing


106/116

8259A Interfacing

Note that;

1. Unused IR inputs should be tied to ground

cause an interrupt.2. In maximum mode RD and INTA signals

of 8259A are connected to the

IORC,IOWC and INTA lines of 8288 buscontroller.

Cascading the 8259s


107/116

Cascading the 8259s

8259As can easily be interconnected to get

multiple interrupts.

.

connected in the cascade mode. In cascade mode one 8259A is configured

as Master and other 8259As as Slaves.

In this figure 8259A-1 is the Master and

others are slaves.


108/116

Cascading the 8259s(Fig 11.7)


109/116

Cascading the 8259s

Each slave is identified by the number


110/116

Each slave is identified by the number

which is assigned as part of its initialization.

Since the 8086 as an INTR input, only oneof the 8259A INT ins is connected to the

8086 INTR pin.

The 8259A connected directly in to the

8086 INTR pin is referred as the master.

The INT pins from other 8259A(Slaves) areconnected to the IR inputs of the 8259A

master.

Cascading the 8259s


111/116

g

The INTA signal is connected to both

master and slave 8259A.

-

from the master to the corresponding pins ofthe slave.

For master these pins function as outputs

and as inputs for slaves.

The signal is tied high for the master and it

is grounded for slaves.

Cascading the 8259s


112/116

g

Note that;

Each 8259A has its own addresses so that

command words can be written to it and status

bytes read from it.

Addresses for 8259As

8259A-1:FFF0H and FFF2H

8259A-2:FFF4H and FFF6H8259A-3:FFF8H and FFFAH

Master and slave operation


113/116

p

1. Slave receives an interrupt signal on one of

its IR inputs

.

of the interrupt request3. If the interrupt is unmasked and its priority

is higher than any other interrupt being

serviced in the slave, the slave will send anINT signal to the IR input of a master


114/116


115/116


116/116

lect09-cn303 [compatibility mode]

Documents