CS152: Computer Architecture and EngineeringGeneric Instruction Processing
Note: These slides have been solely prepared by Shantanu Dutt. The “Patterson Fall 97 copyright UCB” logo appearing on the bottom right corner is incorrect (as is the logo on the bottom-left corner) . They appear because the same template as Dave Patterson’s intro slides used in Lect. 1-2 were used for these slides by mistake. The incorrect logos will be removed later (haven’t yet figured out how to).
Shantanu Dutt, UIC
Co-athor of textbook used in class
Best known for being one of pioneers of RISC
currently author of article on future of microprocessors in SciAm Sept 1995
RY
undergrad and grad work at Berkeley
joined NextGen to design fact 80x86 microprocessors
one of architects of UltraSPARC fastest SPARC mper shipping this Fall
Shantanu Dutt, UIC
Basic Functions of a Control Unit -- Read and Write Selects
Generic Instruction Processing in the Control and Datapaths
Shantanu Dutt, UIC
:
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
Shantanu Dutt, UIC
Computer = Processor + Memory + I/O
Processor = Datapath + Control
Note: The Datapath includes the top levels of the memory hierarchy (e.g., 1st level caches). Some include the entire memory hierarchy as part of the datapath.
Datapath
Datapath = (Data Mem?) + Register File + ALU
Data Memory
Control = (Instr. Mem?) + PC + Instr. Reg. + C.U. (FSM)
Instruction Memory
Basic Functions of the C.U.
The CU functions by sending signals in each state that do the following:
Read Selection = Connection to a bus from various sources (e.g., buses, registers, FU o/ps) using Muxes or Tri-State Buffers (+ Decoders). Only one source can be read onto a bus.
Write Selection = Loading one or more registers w/ the data at the input of the registers.
Read occurs at the beginning of a clock cycle (cc) and the corresponding write into the target register occurs at the rising edge of the next cc (assuming Read finishes by that time; in general the Write occurs at the rising edge of the next cc after the Read finishes). Control signals for both need to be valid in the current cc
r1
Basic Functions of the C.U.
The C.U. orchestrates the processing of instructions along a datapath by a simple sequence of Read and Write selects in each cc
A Register-Transfer-Like Notation:
Read Operation: r2 => Bus (r2 o/p connected to the bus)
Write Operation: rb <= Bus; rd <= Bus (Bus value written/loaded to registers rb, rd
Note final effect of the above Read and Write in the same cc (I.e. Read and Write select control signals valid in the same cc) is :
rb <= r2; rd <= r2
Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]
Memory Interface (Addr. + Data Bus)
IR
PC
C.U.
FSM
PC
Upd.
1
1
Load IR when
Data Memory
Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]
Memory Interface (Addr. Bus)
Memory Interface (Addr. Bus)
Buses A and B
[r3 => BusA; r7=> BusB]
ALU w/ Bus A, B data
[rega <= Bus A; regb<= BusB
Shantanu Dutt, UIC
Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]
Memory Interface (Addr. Bus)
[ADD o/p => ALU o/p]
ADD
Memory Interface (Addr. Bus)
dest filed of IR [r2 <= o/p reg]
r2