Lec. 6:

Folding & Interpolating ADCs

Lecturer: Hooman Farkhani

Department of Electrical Engineering

Islamic Azad University of Najafabad

Feb. 2016.

Email: H_farkhani@yahoo.com

In The Name of Almighty

2

Folding ADC

، Flashبه منظور برطرف نمودن مشکل افزایش نمایی تعداد مقایسه گرها با افزایش تعداد بیتها در مبدل •

. استفاده می شود( Folding)از تکنیک تا کردن ورودی

اصلی این ساختار استفاده از یک مقایسه گر برای مقایسه ورودی با چندین ولتاژ مرجع به جای یک وایده •

Folding preaبرای دستیابی به این هدف، سیگنال ورودی توسط . می باشد( ساختار فلش)لتاژ مرجع

mplifiers به تعداد مشخص تا(Fold )می شود .

به طوریکه در حالیکه مبدل فلش برای این عمل موجب کاهش قابل توجه تعداد مقایسه گرها می شود، •

مقایسه عدد 6فقط به ( 4=بیت 2با تعداد تا خوردن ) foldedمقایسه گر نیاز دارد، مبدل 15بیت به 4دقت

. گر نیازمند است

3

Folding ADC

گر برای ­و سه مقایسه( خطوط عمودی)، (MSB)سه مقایسه گر برای تعیین دو بیت پرارزش (LSB)تعیین دو بیت کم ارزش

4

Signal Folding

• Analog pre-processing

→ folding amplifier

• Folding factor (F) is

equal to the number of

folded segments.

Segment indicator (log2(F) bits)

Fine quantization N-log2(F) bits

VFS

0

2N-1

…

Vi

Do

1 2 3 4 5 6 7 8

5

Folding ADC Architecture

• The fine ADC performs amplitude quantization on the folded signal.

• The coarse ADC differentiates which segment Vin resides in.

…

2n1 Sub-Ranges

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Folding ADC Example: 6-Bit

• Coarse ADC determines segment, fine ADC determines level within segment

• Folding factor (FF) quantifies number of folder output segments

[B. Murmann]

7

Folding Amplifier

Example: 2-Bit Folding Circuit

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Zero-Crossing Detection

• Only detect zero-crossings instead of fine amplitude quantization

→ insensitive to folder nonlinearities.

• P parallel folding amplifiers are required.

F = 3, P = 4

Vi

Vo

0

9

Offset Parallel Folding

• Total # of zero-crossings = Total # of preamps = P*F

• Parallel folding saves the # of comparators, but not the # of preamps

→ still large Cin.

F = 3, P = 4

Re

fere

nce

La

dd

er

Folder 2 V2

Folder 1 V1

ViVR

Folder 3 V3

Folder 4 V4

Vi0

Vi0

Vi0

Vi0

c

c

c

c

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Folding ADC

از نقطه نظر سرعت عملکرد، از آنجاییکه مقایسه گرهایLSB وMSB کنند، لذا ­همزمان عمل می

با کاهش مصرف توان و سطح اشغالی . باشد Flashمی تواند مشابه Foldingسرعت عملکرد مبدل

. بیت قابل پیاده سازی است 10، رزولوشن تا فلش مبدلنسبت به Foldingمبدلهای

Pros

Folding reduces the comparator number by the folding factor F,

while the number of preamps remains the same.

Cons

Multiple differential pairs in the folder increases the output loading.

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Interpolating ADC

Idea:

– Interpolation between preamp outputs

• Reduces number of preamps

– Reduced input capacitance

– Reduced area, power dissipation

• Same number of latches

• Important “side-benefit”

– Decreased sensitivity to preamp offset

• Improved DNL

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Interpolation

– 12 –

Uniformly spaced zero-crossings in flash ADCs

……

Vi

VR1

VR2

VR3

Vo1

Vo2

Vo3

Vo1

Vo2

Vo3

VR1

VR2

VR3

Ref: R. van de Grift, I. W. J. M. Rutten, and M. van der Veen, "An 8-bit video ADC

incorporating folding and interpolation techniques," IEEE Journal of Solid-State

Circuits, vol. 22, pp. 944-953, issue 6, 1987.

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Resistive Interpolation

• Intermediate zero-crossings are recovered by interpolation.

• DNL is improved by voltage interpolation.

• Requires overlapped linear regions b/t adjacent preamps.

Vo1

Vo2

Vo3

VR1

VR2

VR3

……

Vi

VR1

VR3

Vo1

Vo2

Vo3

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Interpolation Nonlinearity

• Nonlinear TF of preamps cause errors in the interpolated zero-crossings.

• Interpolation nonlinearity directly translates into DNL and INL.

• Impedance mismatch due to interpolation also causes dynamic errors.

VA

VB/4+VA*3/4

VA/2+VB/2

VB*3/4+VA/4

VB

A

B

A

B

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Capacitive Interpolation

K. Kusumoto,

JSSC, Dec. 1993

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Current Interpolation

Less accurate then voltage interpolation due to mismatch of current mirrors

Ref: M. Steyaert, R. Roovers, and J. Craninckx, "100 MHz 8 bit CMOS interpolating

A/D converter," in Proceedings of IEEE Custom Integrated Circuits Conference,

1993, pp. 28.1.1-28.1.4.

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Features of Interpolation

• Reduces the total number of preamps by the interpolation

factor.

• Total number of latches stay the same.

• Reduces the total input capacitance (larger input BW).

• More area- and power-efficient than straight flash ADC.

• Voltage interpolation improves DNL.

• Subject to preamp nonlinearities.

• For interpolation factors >2, amplifier nonlinearity can limit the

precision of zero crossings

– See e.g. Van de Plassche, p.121

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Folding & Interpolating ADC: Example

[Murmann]

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Folding & Interpolating ADCs (Recent Years):

Reference

/Date

Technology

(nm)

Resoluti

on (Bit)

Speed

(Gs/s)

Supply

(V)

Power

(mW)

ERBW

(GHz) ENOB (Bit)

FOM

(pJ/step)

[JSCC 2009]

Bob

Verbrugen

90n 5 1.75 1 2.2mW 0.787 @DC:

4.7 0.16

[JSCC 2010]

Nakajima 90n 6 2.7 1 50mW N.A. 5.28 0.47

[JSCC 2009]

C.Taft 180n 10 1 1.8 1200mW N.A. 9.06 2.24

[ISSCC

2004]

C.Taft

180n 8 1.6 1.8 1200mW N.A. 7.26 4.89

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References

Professor Boris Murmann Course slides 2012,

Stanford University- EE315B course

Professor Y. Chiu course slides, Fall 2014.