layout & stick diagram design rules
TRANSCRIPT
![Page 1: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/1.jpg)
LAYOUT DESIGN RULES & GATE LAYOUT
ByS.VARUN
M.Tech [EST]
![Page 2: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/2.jpg)
What is a LAYOUT DESIGN?
![Page 3: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/3.jpg)
Layout Design is a schematic of the Integrated Circuit(IC) which describes the exact placement of the components for fabrication.
Layout Design rules describe how small features can be & how closely they can be packed in a manufacturing process
![Page 4: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/4.jpg)
Why do we need Layout Design Rules?
![Page 5: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/5.jpg)
Industrial Design rules are generally specified in microns.
This makes migrating from one process to more advanced process difficult because not all rules scale in the same way.
![Page 6: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/6.jpg)
In order to bring uniformity,Mead & Conway popularized lambda-based design rules based on single parameter.
Lambda,characterizes the resolution of the process & is generally the half of the minimum drawn transistor channel length.
![Page 7: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/7.jpg)
The channel length is the distance between drain & the source which is set by a minimum width of a polysilicon wire.
Ex:-A 180 nm process has a minimum polysilicon width of 0.18microns and uses design rules with lambda=0.09.
![Page 8: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/8.jpg)
However the designers make the scaling layout trivial.
The same layout can be moved to a new process simply by specifying the Lambda value.
The potential density advantage of micron rules is sacrificed for simplicity and easy scalability of lambda rules.
![Page 9: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/9.jpg)
Designers often describe a process by its feature size.
Feature Size refers to the minimum transistor length,So lambda is half the feature size.
Transistor dimensions are always specified by Width/Length ratio.
![Page 10: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/10.jpg)
Ex-In 0.6 um technology, width corresponds to 1.2um & length to 0.6um.
In digital systems, the transistors are chosen to have minimum possible length because short channel transistors are faster, smaller & consume less power.
![Page 11: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/11.jpg)
![Page 12: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/12.jpg)
STICK DIAGRAMS
Stick diagrams may be used to convey layer information through the use of a color code
Ex-In the case of nMOS design, green for n-diffusion, red for polysilicon, blue for metal,and black for contact areas.
![Page 13: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/13.jpg)
A stick diagram is stick figure view of a layout.
It is useful for a)Planning Layoutb)Relative Placement of transistorsc)Assignment of signals to layersd)Connections between cellse)Cell hierarchy
![Page 14: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/14.jpg)
LAYOUT ENCODINGS
![Page 15: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/15.jpg)
![Page 16: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/16.jpg)
n-Type ENHANCEMENT
![Page 17: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/17.jpg)
n-Type DEPLETION
![Page 18: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/18.jpg)
p-Type ENHANCEMENT
![Page 19: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/19.jpg)
STICK DIAGRAM DESIGN RULES
1)When two or more ‘sticks’ of the same type cross or touch each other which represents electrical contact.
2)When two or more ‘sticks’ of different type cross or touch each other which represents no electrical contact.
![Page 20: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/20.jpg)
3)When poly crosses diffusion, it represents a transistor.
4)In CMOS, a demarcation line is drawn to avoid touching of p-diffusion & n-diffusion. All p-MOS should lie on one side of the line & all n-MOS should be on the other side of the line.
![Page 21: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/21.jpg)
DIAGRAMATIC REPRESENTATIONS
![Page 22: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/22.jpg)
n-Type ENHANCEMENT & DEPLETION TRANSISTOR
![Page 23: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/23.jpg)
p-Type ENHANCEMENT TRANSISTOR
![Page 24: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/24.jpg)
CMOS INVERTER STICK & LAYOUT DIAGRAM
![Page 25: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/25.jpg)
CMOS NAND GATE STICK DIAGRAM
![Page 26: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/26.jpg)
CMOS NOR GATE STICK DIAGRAM
![Page 27: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/27.jpg)
EXAMPLE EXPRESSION
![Page 28: Layout & Stick Diagram Design Rules](https://reader035.vdocuments.site/reader035/viewer/2022062223/58741dfa1a28abcb5b8b75c5/html5/thumbnails/28.jpg)
THANK
YOUALL
S.VARUN