latch and flisp flop.ppt
TRANSCRIPT
-
8/9/2019 Latch and Flisp Flop.ppt
1/18
1
Latches and Flip-Flops
Dr. Le Dung
Faculty of Electronics and Telecommunications
Hanoi University of Science and Technology
Content
•
Memory element
•
Latches
•
Flip-Flops
Dr. Le Dung 2 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
2/18
2
A device with exactly two stable states
Bistable multivibrator circuit
Q1 on Q2 off
Q1 off Q2 on
2 stable states
as
a memory element
can store one bit
Dr. Le Dung 3 Hanoi University of Science and Technology
Memory element
Latch Flip-Flop (with clock)
1-state
or
0-state
Q
Q
Excitation
inputs
1-state (set):
Q=1, Q=0
0-state (reset):
Q=0, Q=1
Inhibited-state:
Q = Q
Set
Reset
Q
Set
Reset
Q
Clock
Excitation
inputs
Dr. Le Dung 4 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
3/18
3
Latches
• SR latch (Set-Reset latch)
+ with NOR structure
+ with NAND structure
• Gated SR latch
• D latch (Delay or Data latch = transparent latch)
• Some applications of the latches (1) (2) (3)
Dr. Le Dung 5 Hanoi University of Science and Technology
Set-Reset Latch with NOR structure
S R Q’ (next)
0 0 Q (latch)*
0 1 0 (reset)
1 0 1 (set)
1 1 Q’=Q’=0(Inhibited)
* Latch = No change
SR latch
S, R active “High”
NOR structure
Set
Q=1,Q=0
Reset
Q=0,Q=1
XQ=Q
SR=10
SR=01
SR=00
SR=10
SR=00
SR=01SR=11 SR=11
Inhibited
State diagram (Moore)
LatchLatch
Dr. Le Dung 6 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
4/18
4
Set-Reset Latch with NAND structure
S R Q’ (next)
0 0 Q’=Q’=1(Inhibited)
0 1 1 (set)
1 0 0 (reset)
1 1 Q (latch)*
* Latch = No change
SR latch
S, R active “Low”
NAND structure
Set
Q=1,Q=0
Reset
Q=0,Q=1
XQ=Q
SR=01
SR=10
SR=11
SR=01
SR=11
SR=10SR=00 SR=00
Inhibited
State diagram (Moore)
LatchLatch
Dr. Le Dung 7 Hanoi University of Science and Technology
SR latch timing diagram NOR SR Latch
S, R active “High”
Q’=Q’=0
(Inhibited)
11
1 (set)01
0 (reset)10
Q (latch)*00
Q’ (next)RS
(Illegal)
Q’ = S + RQ
Dr. Le Dung 8 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
5/18
5
Gated SR Latch
* Hold = No action
Gated SR latchE S R Q’ (next)
0 x x Q (hold)*
1 0 0 Q (latch)
1 0 1 0 (reset)
1 1 0 1 (set)
1 1 1 InhibitedE,S,R active “High”
Set
Q=1,Q=0
Reset
Q=0,Q=1
XQ=Q
ESR=110
ESR=1010xx,
110
111 111
Inhibited
State diagram (Moore)
0xx,
101
Dr. Le Dung 9 Hanoi University of Science and Technology
D Latch
E D Q’ (next)
0 x Q (hold)*
1 0 0 (reset=store 0)1 1 1 (set=store 1)
Set
Q=1,Q=0
Reset
Q=0,Q=1
ED=11
ED=10
0x,
11
0x,
10
Store 1 Store 0
Dr. Le Dung 10 Hanoi University of Science and Technology
Data or Delay latch
= transparent latch
-
8/9/2019 Latch and Flisp Flop.ppt
6/18
6
Some applications of the latches (1)
Dr. Le Dung 11 Hanoi University of Science and Technology
(App 1) Debounce a mechanical switch
Some applications of the latches (2)
Dr. Le Dung 12 Hanoi University of Science and Technology
(App 2) LED detect alarm system
-
8/9/2019 Latch and Flisp Flop.ppt
7/18
7
Some applications of the latches (3)
Dr. Le Dung 13 Hanoi University of Science and Technology
(App 3) 74LS75 Quad D latch module with enable
Flip-Flops• Clock signals
• Clocked flip-flops
+ Master-Slave Flip-Flop (Pulse-triggered FF)
+ Edge-triggered Flip-Flop
•
SR Flip-Flop• JK Flip-Flop
• D Flip-Flop
• T Flip-Flop
• Asynchronous set and reset (Preset and Clear)
• Some applications of the flip-flops(1) (2) (3)
Dr. Le Dung 14 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
8/18
8
Clock signals
Dr. Le Dung 15 Hanoi University of Science and Technology
Clocked Flip-Flops
Dr. Le Dung 16 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
9/18
9
Master-Slave Flip-Flops
Dr. Le Dung 17 Hanoi University of Science and Technology
Edge-triggered Flip-Flops
Dr. Le Dung 18 Hanoi University of Science and Technology
PGT detector NGT detector
-
8/9/2019 Latch and Flisp Flop.ppt
10/18
10
SR Flip-Flop (active with PGT)
Dr. Le Dung 19 Hanoi University of Science and Technology
SR Flip-Flop (active with NGT)
Dr. Le Dung 20 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
11/18
11
JK Flip-Flop
Dr. Le Dung 21 Hanoi University of Science and Technology
JK Flip-Flop (active with PGT)
Dr. Le Dung 22 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
12/18
12
JK Flip-Flop (active with NGT)
Dr. Le Dung 23 Hanoi University of Science and Technology
Internal Circuitry of JK Flip-Flop
Dr. Le Dung 24 Hanoi University of Science and Technology
Feedback
Feedback
-
8/9/2019 Latch and Flisp Flop.ppt
13/18
13
Pulse-triggered JK Flip-Flop
Dr. Le Dung 25 Hanoi University of Science and Technology
D Flip-Flop
Dr. Le Dung 26 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
14/18
14
Make D Flip-Flop from JK Flip-Flop
Dr. Le Dung 27 Hanoi University of Science and Technology
T Flip-Flop (active with NGT)
Dr. Le Dung 28 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
15/18
15
Clocked T Flip-Flop
Dr. Le Dung 29 Hanoi University of Science and Technology
Asynchronous set and reset (1)
Dr. Le Dung 30 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
16/18
16
Asynchronous set and reset (2)
Dr. Le Dung 31 Hanoi University of Science and Technology
JK-FF with Preset and Clear inputs
Asynchronous set and reset (3)
Dr. Le Dung 32 Hanoi University of Science and Technology
-
8/9/2019 Latch and Flisp Flop.ppt
17/18
17
Asynchronous set and reset (4)
Dr. Le Dung 33 Hanoi University of Science and Technology
T-FF with Preset and Clear inputs
Applications of the Flip-Flop
Dr. Le Dung 34 Hanoi University of Science and Technology
+ Thi!t k! các b" #!m (Counter)
+ Thi!t k! thanh ghi d$ch (Shift register)
+ Thi!t k! m%ch dãy
+ Các &ng d'ng khác
-
8/9/2019 Latch and Flisp Flop.ppt
18/18
18
Some applications of the Flip-Flop (1)
Dr. Le Dung 35 Hanoi University of Science and Technology
3 bits Up-Counter
Some applications of the Flip-Flop (2)
Dr. Le Dung 36 Hanoi University of Science and Technology
Serial shift register