labs m1 rabat june2011

Rabat_test_lab 1/42 June 11 - BP

PRODUCTION

TESTING

LABS


EXERCICE – 74ACT299

GENERAL DESCRIPTION

• 8-bit universal shift/storage register with tristate outputs.

• Four modes of operation:

o hold (store)

o shift left

o shift right

o load data

Pin description

True table


DC Electical Characteristics for ACT family devices

AC Operating Requirements for ACT family devices


FOCUS on DATA SHEET (answer to questions on a separate paper)

We want to test and characterize our device according to its electrical and timing

specifications

1. 74ACT299 device functionality check

We want to verify that the device works like described in the true table. Fill the

following table according to the requested instructions and referring to the true table

We consider that an I/O pin is used as input or output but can’t be both during one

clock pulse.

M

R

C

P

S

0

S

1

D

S0

D

S

7

I

O

0

I

O

1

I

O

2

I

O

3

I

O

4

I

O

5

I

O

6

I

O

7

Q

0

Q

7

INSTRUCTIONS

0 1 0 0 0 0 0 0 0 0 0 0 0 0 X X Reset

1 1 0 0 0 0 X X X X X X X X X X Hold

1 1 1 1 0 0 1 0 0 0 0 0 0 0 H L // Load 10000000

1 1 1 0 0 0 L H L L L L L L L L Shift right 8 times

1 1 0 1 0 1 L L L L L L L H L H Shift left

1 1 0 0 0 0 H H L L L L L L L L Hold

// Load 10101010

Hold

Shift left

Hold

Reset

// Load 11111111

Hold

Hold

// Load 00000000

Hold


2. VIL/VIH test conditions

We want to verify the “fan in” of the 74ACT299 device. According to the DC electrical

characteristics, define the voltages to apply to the device input pins to test at min

and max conditions:

VDD = 4.5V VDD = 5.5V

VIL = VIL =

VIH = VIH =

With VOL = VDD/2 – 10% and VOH = VDD/2 + 10% what are VOL and VOH values for both

VDD conditions

VDD = 4.5V VDD = 5.5V

VOL = VOL =

VOH = VOH =

3. VOL/VOH tests conditions

We want to verify the “fan out” of the 74ACT299 device. According to the DC

electrical characteristics, define the voltages to apply to the device I/Os to test at min

and max conditions:

VDD = 4.5V VDD = 5.5V

VIL = VIL =

VIH = VIH =

VOL = VOL =

VOH = VOH =

IOL = IOL =

IOH = IOH =

Vref = 2.5V Vref = 2.5V

4. Timing test limits

We want to verify the set up & hold times and the propagation delay of all outputs to the

clock CP of the 74ACT299 device. According to the AC electrical characteristics, define

the min and max limits for the following timing parameters. Select the limits in order to

be in the worst case condition:

Parameters Min Max

Set up time I/On to CP

Hold time I/On to CP

Propagation delay CP to Q0 or Q7

Propagation delay CP to I/On


FOCUS on TEST DEVELOPMENT

Refer to the data sheet to define:

5. Levels to apply to the following pins for a functional test:

Input pins Vil Vih

CP

DS0, DS7

MR_

S0, S1

Output pins Vol Voh

IO[0 :7]

Q0, Q7

6. Timings:

Considering a 20MHz tester period and the following drive and receive definitions, use the graph

below to represent the timing (shape + edge) of each pin in one period:

Input pins Shape d1(ns) d2(ns)

CP RZ 10 40

DS0, DS7 NRZ 0 -

MR_ RO 10 20

S0, S1 NRZ 5 -

Output pins Shape r1(ns)

IO[0 :7] Edge H 45 -

Q0, Q7 Edge L 45 -

10 20 30 40 50 0

CP MR_ S0 S1 DS0 DS7 IO/0 IO/1 IO/2 IO/3 IO/4 IO/5 IO/6 IO/7 Q0 Q7

ns

Tester period


FOCUS on TEST FLOW

We want to apply the test conditions and limits defined for the Vil/Vih, Vol/Voh, set up time

and propagation delay tests to a predefined test flow.

We first need to start the tester software: “SmarTest”

Step 1: Start SmarTest (Tester sw)

From Unix environment, open a terminal and type:

ssh –X [email protected] (Y = 1 up to 12)

Enter password: #trainYv93#

vncviewer VerigyOFF2.cnfm.fr :user_display_number (refer to table below)

Enter again the password: #trainYv93#

Login Password VNC display number

train1v93 #train1v93# 71


train3v93 #train3v93# 73 train4v93 #train4v93# 74







From Windows environment, open the Real VNC icon and enter the local address, the user’s

display number (example with user train1v93) and password.

Select “Options”, then “Misc” and enable the “Shared connection” like shown in next figure.


If the connection establishes, you should get the following window.


From the start menu « », the shortcuts to launch SmarTest® are located in the

menu « Verigy ».

Mode « Online »

disponible sur

VerigyON seulement

Mode « Offline »

A utiliser par défaut

When starting Smartest®, you will have the following Workspace Laucher window. Select Ok

if you have the following path:

/home/trainYv93/workspace_Rabat

When launching SmarTest®, 3 windows appear on the screen:

• « Operation Control » window allows controlling tasks execution on tester. Used to format

datalog stream results.

/home/trainYv93/workspace_Rabat


• « ui_report » window allows following the communication between the tester and

SmarTest®. It is very important to regularly look at this window to verify if any error or

warning messages appear.

• « SmarTest Eclipse Workcenter», window where the users will find all tools to develop a test

program.


Eléments du

programme de

test

Explorateur de fichiers Editeur de fichiers

Menu

« setup »Menu « results »

Step 2: Create a SmarTest Device directory

Verify or start Smartest in the offline mode.

If you have not previously created and used a device file, you will see a window with the heading "- change device -”. Otherwise, the software will point to the device (directory) you last used. This step of creating a SmarTest device directory will be bypassed and the software will continue to initialize.


• In the “Path” field, verify that you are in your own directory: /home/trainYv93/RABAT

• In the “Device” edit field, type 74ACT299_user_name in the Change Device window.

• Click the Create button. You will see a "create new device" window.

• Click the create device or enter device button. SmarTest creates a device directory 74ACT299_ user_name in your specified path.

• The ui_report window shows that you are the user and that the device directory is

74ACT299_ user_name. The Operation Control and Main Toolbar GUIs will appear on your monitor and signals the completion of the SmarTest startup.

Step 3: Defining the pin configuration

Learning objective: We will begin creating our test program for the 74ACT299 shift register by defining the pin configuration. Define a pin configuration is always the first step to take. In this lab exercise, defining the pins will involve the following tasks:

Channel allocation to the device pins.

Specification of the DPS operating ranges.

Definition of pin groups. Getting started: Before using the SmarTest Pin Configuration GUI, you will need to know how to map your DUT pins to the V93000 channels; this routing is dependant upon the load board circuit layout. A listing of the routing for the loadboard use in this lab is provided in Table 1.

1. Channel allocation

• If not already running, start the SmarTest software in the offline mode. Be sure that the active device directory is /home/trainYv93/RABAT/74ACT299_user_name. (Y=[1:12])


• In the Test Program Explorer window, click on “Pin Configuration ” and select “new ” from the scroll-down menu. Give the name “pins ” to the new file and open it.


From the Test Program Explorer Window, double click on “Pin Setting” to be able to fill the pin setting table.

Figure: Pin Configuration window, initial view

• Enter information for the pins listed in Table 1 below.

For each pin, enter Pin No, Pin Name, Type, Tester Channel from this table.

For each i, o or io pins, always use the default settings of Pin Mode (std) and Series Resistor (0.0).

For the DPS pin, enter a Load C (capacitive load) of 10.0 (µF). This entry determines the operating range of the DPS. No mode must be entered for the DPS pin.

Table 1: Load board channel mapping

Pin Number

Pin Name

Type Tester Channel

Pin Number Pin Name Type Tester Channel

12 CP I 10102 16 I/O7 Io 10106

18 DS7 I 10108 4 I/O6 Io 10111 11 DS0 I 10101 15 I/O5 Io 10105

19 S1 I 10109 5 I/O4 Io 10112

1 S0 I 10110 14 I/O3 Io 10104 9 _MR I 10116 6 I/O2 Io 10113

17 Q7 O 10107 13 I/O1 Io 10103

8 Q0 O 10115 7 I/O0 Io 10114 Vcc DPS+ DPS11


• You should get a similar window:

• The test Program Explorer shows different state of setup graphically. Here is a

summary. a. Green box - GUI and hardware are in sync. What you see on Setup

Editors are already in Tester hardware memory. No further action is needed by you.

b. Yellow box - contents of Setup Editors are not identical to that of hardware memory.

You have to decide if you want to apply those new configuration to hardware or not. In the Test Program Explorer view, right-click the Pin Setting icon and select Apply . This downloads the channel allocation to the tester.


• In the Test Program Explorer, select the “pins” name and click “Save As“ in the scroll down menu. This saves the pin configuration setup on disk.

2. Defining pin groups

You have now to create the following pin groups:

Group Include Pins io_in I/O7(i), I/O6(i), .... I/O0(i)

io_out I/O7(o), I/O6(o), .... I/O0(o)

io_pins Io_in, io_out Mode S1, S0

Ser_in DS7, DS0 Ser_out Q7, Q0

ctrl CP, _MR, mode

all_in ctrl, ser_in, io_in all_out io_out, ser_out

Table 2: Pin groups to define

• In the Pin Group Definition Editor, you can choose from one of two group types:

o Atomar groups consist of a number of individual digital pins, such as the pins in the table1.

o Expression based groups support elementary set operations. The expressions can contain any of the following:

� individual digital pins (as above).

� atomar groups.


� existing expression based groups.

• In the Test Program Explorer View, click the arrow on the left side of the “Pin

configuration” name to highlight Group. Right click “Groups” and select “New…” • The New Group window pops up. Select the group type and enter the group name

(use the Group column of the following table) in the “New Group” text box. Click OK. • Repeat the following steps for all groups listed in table 2, below:

o Select either "new atomar definition" or "new expression based definition" buttons, depending on the method of creating groups that you prefer.

o For groups that define membership of only individual pins, e.g. io_in and ser_in in Table 2 below, you may use either "new atomar definition", or "new expression based definition".or groups that define membership to include other declared groups, e.g. io_pins in Table 2 below, that have already been defined, select "new expression based definition".

• In the group name edit field, enter a group name. Use the names from Table 2. Be sure to type in the names exactly as it appears in the table.


• If you are using the “expression based method”

o Choose the default operator. This is the operator that will be used if you add a pin or a pin group to the expression by clicking “Add” pin group in the “pinlist/grouplist” columns. For the lab, you only need the “Union ” operator.

o Choose the component Type (IO).

o Double-click each of the required pins and/or groups listed in the “pinlist/grouplist” columns. Alternatively, you select the desired pins and click the “Add” button.

o Click the “evaluate expression” button.

• In the Test Program Explorer, select the “pins” name and click Save in the scroll

down menu.


Step 4: Loading Level, Timing, Pattern files

• Open a terminal window from the RedHat menu « ».

Mode « Online »

disponible sur

VerigyON seulement

Mode « Offline »

A utiliser par défaut

• Copy the level, timing and pattern files which are stored under the path

/home/trainYv93/DIG_INIT/aca_init/ to your corresponding directories:

- Copy the levels to your device level directory with the command:

cp /home/trainYv93/DIG_INIT/aca_init/level

/home/trainYv93/RABAT/74ACT299_username/levels/.

- Repeat the operation for the timings:

cp /home/trainYv93/DIG_INIT/aca_init/timing /home/trainYv93/

RABAT/74ACT299_username /timing/.

- Repeat the operation for the vector:

cp /home/trainYv93/DIG_INIT/aca_init/all_binl /home/trainYv93/

RABAT/74ACT299_username vectors/.

cp /home/trainYv93/DIG_INIT/aca_init/vector /home/trainYv93/

RABAT/74ACT299_username vectors/.

• Return to the Test Program Explorer and load the levels, timing and vector:

1. From the Test Program Explorer, select “levels”

2. From the right click menu, select “Load”

3. From the “Select File to Load” window, select “levels”

• Repeats these 3 previous steps to load the timing and pattern files:

- Timing file : timing

- Pattern file : all.binl


Step 5: Creating a first test flow

1. Creating an empty test flow

From the Test Program Explorer window, select and create a new test flow. Give the

name “functional_testflow”.

Right-click on the new test flow and select Open with Graphical Editor.


The following empty test flow pop-up.

First, click on the button from the Testflow Editor Bar and enter select + load your

context = pin configuration + levels + timing + vector like shown on the following

window.

1. Creating a Continuity test

From the Testflow Editor Bar, select Insert/run and branch and fill the Test suite as

follow:

Testsuite fields value

Testsuite name Continuity

Timing Equation 1

Timing Spec Set 1

Timing Set 1

Level Equation 1

Level Spec 1

Level Set 1

Vector Label “gross_func”

Once, the primary settings are entered, click on the Testfunction field then click on

New Testfunction button to create a new test continuity from the standard tests

library.

Enter the name “continuity_tf” in the TestFunction field.


In the Test Control window (yellow window), enter the following values in the fields

indicated and options.

Window field value comment

pin list @ all pins

test current (PMU Force current) –50 uA

pass volt min 200 mV

pass volt max 700 mV

settling time 4 mS

Select options: PPMU parallel and both polarities (the associated

selected button will be black).

Click Done in the Test Suite window.

In the Test Suite window, select the Flags tab. In the page that appears, check the

flags:

Output on pass Output on fail

Pass value Fail value

Per pin on pass Per pin on fail

These settings affect the amount of data that is displayed in the ui_report window

when the testflow is executed. Enable all the 6 boxes mentioned above.


Click Done in the Testsuite Dialog.

2. Creating a Functional Test

After the passing branch of the continuity Test Suite, you are going to insert a

functional Test Suite. From the Testflow Editor Bar, select Insert/run and branch and fill

the Test suite as follow:

Testsuite fields value

Testsuite name Functional

Timing Equation 1

Timing Spec Set 1

Timing Set 1

Level Equation 1

Level Spec 1

Level Set 1

Vector Label “gross_func”

Once, the primary settings are entered, click on the Testfunction field then click on

New Testfunction button to create a new test functional from the standard tests

library.

Enter the name “functional_tf” in the TestFunction field.


Select the Flags tab of the Testsuite Dialog window. In the page that appears, check

the flags:

Output on pass Output on fail

Pass value Fail value

Per pin on pass Per pin on fail

These settings affect the amount of data that is displayed in the ui_report window

when the testflow is executed. Enable all the 6 boxes mentioned above.

3. Inserting a good and bad bins

In the Fail branch of the continuity test, click the insert point and select Insert >

badbin. The Bin Dialog window will appear. See Figure 4.

Figure 4 Bin Dialog window


In the Bin Dialog, enter numerical values for Software Bin, 2; Hardware Bin, 2. Enter

“Failed Continuity” in the Software Description.

Click the Done button in the Bin Dialog.

In the Fail branch of the Functional test, click the insert point and select Insert > badbin.

The Bin Dialog window will appear. In the Bin Dialog, enter numerical values for Software

Bin, 3; Hardware Bin, 3. Enter “Failed Functional” in the Software Description.

Click the Done button in the Bin Dialog.

Select Insert > good bin at the rightmost insertion point of the testflow. The testflow will

end there when the gross_func test passes. Enter “1” as Software and Hardware bin

numbers. Enter “Good Part!” in the Software Description.

Click Done.

You should get the following test flow:

Return to the Test Program Explorer and save your test flow.

4. Executing a Test flow

From the Testflow Editor, in simulator mode, verify that your test flow has no error

(check the UI_report window) before running it on the tester. Click on the “Running

Man” icon:

Quit the simulator mode and connect to the tester:

- Exit SmarTest: File/Exit

- Close the VNC viewer window clicking on the cross (DON’T “logout”)

From a Unix environment:

- Return to the terminal window

- Connect to the tester machine:

vncviewer VerigyON.cnfm.fr :user_display_number


Login Password VNC display number










From Windows environment:

- Open the Real VNC icon and enter the local address, the user’s display number

(example with user train1v93) and password.

Once the Verigy/Linux window is opened:

- Start the online license

- From the Test Program Explorer, load your test flow

- Open it with the Graphical Editor

- Do a “File/load setup”

- Execute the test flow

- Look at the result in the IU_report

- Execute only the continuity test (right click and select “execute site in

focus”)

- Look at the measurements in the IU_report

What are the values measured for the pins during the continuity test?


FOCUS ON CHARACTERIZATION: DC and AC Tests

• Open a terminal window from the RedHat menu « ».

• Copy the testflow file called “tf_ac_dc_char” stored under the path

/home/trainYv93/DIG_INIT/aca_init/ to your testflow directory with the command:

cp /home/trainYv93/DIG_INIT/aca_init/tf_ac_dc_char

/home/trainYv93/RABAT/74ACT299_username/testflow/.

From the Test Program Explorer, load the test flow called “tf_ac_dc_char”

Open the test flow with the graphical editor.

From the “Test Flow Editor” window, load the setups (File/load setups).

The objective of the exercise is to apply the test conditions you have extracted from the

data sheet to the parametric tests implemented in the test flow.

The modification of the test program is done offline.

1. Vil/Vih test

a. In the test flow, double-click on the “Vil/Vih” test to open it.

b. Put the mouse in the “test function” section and click on “Edit” to open the

“test control” window (yellow window).

c. Replace the predefined vil and vih values by your values extracted from the

data sheet in section “Focus on data sheet”.

d. Execute the test to check if there is no error.

e. Click on “Done” in the “Vil/Vih” test window (grey window).

Select


2. Vol/Voh test

a. Repeat a. and b. actions from section 1 with “Vol/Voh” test.

b. Insert the Vol/Voh values that you have extracted from the data sheet in

section “Focus on data sheet”.

c. Execute the test suite to check if no error.

d. Click on “Done”

Iol/h

Vol max/Voh min

Vol min/Voh max

3. Set up time test

a. Repeat a. and b. actions from section1 with “Set up time” test.

b. Replaced the predefined pass limit by the limit you have extracted from the





4. Propagation delay test

a. Repeat a. and b. actions from section1 with “Propagation delay” test.

b. Replaced the predefined pass limit by the limit you have extracted from the




5. Save your changes done in the test flow:

Click on the test flow “tf_ac_dc_charac” in the Test Program Explorer window and select

“SAVE AS”. Save the new test flow to “TestflowComplete”.

When the tester is free, exit Smartest offline mode and connect to the online license

following the same procedure than when checking the functional test flow.

To see in the IU_report the details of your test results when you execute the full test flow, you need enable the datalog formatter from the “test flow editor” window:


1. Open the “system flag” window: datalog_formatter: on (parameter n° 6 in the list) Log_events_enable: on (last parameter in the list)

2. Open the “test flag” window: Limits_enable: on (parameter n° 12 in the list)

3. From the “operation control” window, click on “production setting” 4. From the “testflow setting mode”, click on “report formatter” 5. From the “report formatter”, select “EventFormatter”

6. From the “ui_report” window, select “open Report Dialog” in Datalog menu. 7. In the “report dialog” window:

a. Select the “PASS” and “FAIL” buttons for all test types except for “Analog Test”. b. In each “Output as Result”, select all buttons except “shmoo data” and

“waveforms”. c. Click on “Set Testsuite Flags” and “close”

3 : enter a test

S

el

4 3


Execute the whole test flow and read in the top part of the IU_report window the measured

values of each parametric test. Compare your measured values with the ones in the data

sheet. What can you say about the device?

6. Shmoo plots analysis

This exercise is to be done in offline mode while waiting for the tester.

You have the 2 following shmoo plots displayed to analyse.

The first one corresponds to the variation of the acquisition time on the output Q7 versus

Vdd.

The second one corresponds to the variation of the clock driving edge “d1” versus the

driving edge “d1” of serial input pins DS0 and DS7.


• Focus on the variations of Q7 versus Vdd shmoo plot and knowing that the capture

edge “r1” is setup to 12,5ns, calculate the margin for “r1” in ns when Vdd = 4V, 4.5V,

5V and 5.5V

Vdd = 4.0 V r1 margin = (ns)




• Indicate the passing area. Can you explain what this graph means?

• Focus on the variations of the serial inputs DS0, DS7 versus the clock CP shmoo plot.

Knowing that “d1” represents the active edge of the serial inputs and is setup to 5 ns, use

the shmoo plot to calculate the margin in “ns” when the active edge “d1” of CP = 10ns,

20ns and 30ns.

d1(CP) = 10ns d1 margin = (ns)




• Indicate the passing area. Can you explain what this graph means?

“d1” of DS0 and DS7 versus “d1” of CP


FOCUS ON DEBUGGING

Step1: Error Map

Analyse the pictures below and answer to the following questions:

o What does represent the alignment of cells?

o What does the red and grey cells represents

o What are the failing pins and failing cycles for each error map?


Step2: Timing Diagram

Analyse the pictures presented below.

- What represent the pink and black waveforms?

- What represent the black arrows?

Identify the failing pins and failing cycles in the timing diagram. Which values are

captured?


FOCUS ON DIAGNOSIS

From the following test pattern debugger report, try to identify the type of fault (stuck at

0/1) and location in the device (input/output pins or internal node).

labs m1 rabat june2011

Documents

hold rabat

hold load

functional test

test development

bp rabat

timing test limits

vilvih test conditions

left hold