Samuel Silverstein Stockholm University

L1Calo upgrade discussion

Overview Issues

Latency Rates Schedule

Proposed upgrade strategy R&D

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Upgrade phases (for this talk)

Phase I (before calorimeter upgrades): Two projects

FPGA-based MCM replacement for PPr CMM++ in CP and JEP, options for

• Limited topo algorithms in CMM++ modules

• Topological processing in separate TP

Phase II (digital calorimeter readout to USA15) "Level 0": topological algorithms on finer-granularity

"mini towers" built in RODs, plus muon objects Fixed, low latency (< 3.2 s)

"Level 1": full calorimeter resolution, plus objects from muon and ID triggers

Longer latency, possibly asynchronous

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CP 0

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CP 2

Phase I with CMM++ (one example)

160 Mbit/s

160 Mbit/sTo CTP

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To CTP

160 Mbit/s

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CP 1

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CP 3

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Jet 0

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Jet 1

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Can use half ofCP ROIs

1 of 2

Runfaster?

Quadrant border data

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TopoProcessor

Jet / ET

(JEP)

0.2 x 0.2

E/ /hadclusters

(CP)0.1 x 0.1

High-speedoptical links

Jets

ClustersTo CTP

Energies

Muons

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Phase II concept Latency and rates

Fast L0 (40 MHz in, up to 500 kHz out, <3.2s) Slower L1 (500 kHz in, <75-100 kHz out, >9.6s)

Level 0: Finer-granularity "mini towers" with e.g. Et, fine-location of

shower maxima, longitudinal profiles, quality flags, etc. Multi-crate L0Calo processor: sliding-window algorithms to

identify features L0Topo: trigger algorithms using calo and muon objects L0 ROIs sent to L1Track to gather track candidates

Level 1: Refined L0 algorithms with full calorimeter data L1Topo: trigger algorithms using calo, muon, track objects

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Phase II concept (Murrough)

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Latency issues

Phase I: Latency envelope 2.5 s May currently be as few as 10 BCs from limits

Phase II: L0 trigger limited to 3.2 s (by muons) Tile and (esp) LAr digital processing add additional latency At least three sequential multi-Gbit links in L0 RTDP Need to evaluate and limit all potential sources of latency

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Latency issues

Sources of additional latency: Link choice (SerDes latency)

GBT: 8-10 BC if optimised (S. Muschter), 16 BC (GBT group) 8b/10b: 5 BC (3.2 Gbit), 3 BC (6.4 Gbit)

Upgraded firmware CPM and JEM merger encoding (and decoding): ~0.5 - 1 BC CTP upgrade to 80 MHz: 2-3 BC

Topological algorithms themselves Possible latency savings

Faster FPGAs in upgraded hardware CMM++ (Virtex E Virtex 6) PPr MCM upgrade from ASIC to Spartan 6

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Rate issues

Conflicting demands at sLHC L1 tracker concept relies on high L0 trigger rate

Richard Brenner: >500 kHz Muon detector cannot handle high L0 trigger rate

< 200 kHz No obvious options

Upgrade muon electronics Many inaccessible boards. Years to disassemble and replace

Muon system ignores L0A, reads out after L1A L1A latency too long. Data lost

"Private trigger" for muons? Won't work....how do we decide which L0A will be accepted by L1?

Data lost. How do we proceed?

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Schedule issues

Phase I: CMM++ should be ready for deployment by 2015

Need to start Phase I soon May be needed before calorimeter upgrade (2017-19)

but discarded when calorimeters are upgraded

Phase II: Large, completely new system! Concurrent with calorimeter upgrade (2017-19)

Need to start Phase II soon

Problem: Phase I and II development in parallel conflicting demands on manpower, organisation, etc

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Proposed strategy

Focus on Phase II "Staged" deployment:

L0Calo/L0Topo in time for calo upgrades• 2017-2019 timescale• Fixed latency, maximum 3.2 s• Run at <75 kHz until L1 is ready• L0Topo compatible with CMM++ outputs

– Usable as TP in Phase-1 system (see next slide) L1 trigger ready for ID upgrade

• Increase L0 rate to 500 kHz• Asynchronous processing?

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Phase-II "staging"Install with calorimeter upgrades (2017-2019)

Install with ID upgrade (2020-)

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Proposed strategy

Phase-I development in parallel Lower initial ambition level Build and deploy CMM++ as soon as possible

Limited topo algorithms in CMM++ Muon ROIs not included?

L0Topo compatible with CMM++ outputs? Use as TP if Phase I delayed, or too much pileup Early, parasitic testing/integration of L0Topo before

rest of L0Calo is ready? Possible to include muon ROIs?

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R&D results

MCM replacement design is progressing well Spartan 6 FPGA could be used to improve pileup performance,

maybe lower latency. Encouraging work on CPM merger

Readout scheme makes better use of bandwidth, small cost in latency and design size

Use same format for Jets? Maybe add jet ROI energies to threshold bits

New ideas for CMM++ Virtex 6 HXT adds more logic, plus up to 72 multi-Gbit

transceivers (from half that on LXT device) More optical links open new possibilities for merger topology

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R&D results

New results from GOLD Encouraging link latency results Experience with new HXT FPGAs Understanding of phase II HW issues, including power, board

density, etc Stockholm link test board

High-speed links can be run with TTC Latency results compatible with GOLD 8b/10b measurements IPG during empty LHC BCs

Similar scheme needed for any 8b/10b link. New algorithm studies

Many algorithms possible with CMM++ only Interesting idea to combine jet and energy transverse mass Need to focus on questions of bandwidth (vs. processing power):

how much information is needed, and where?

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Discussion?