L1Calo Status Report• eFEX• jFEX• gFEX• L1Topo• ROD• Hub• TREX• FOX• Mapping• FTM• Link-Speed

Tests

15 October 2015 Ian Brawn, on behalf of L1Calo

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Ian Brawn, on behalf of L1Calo

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eFEX• Sent to manufacture 24/7/15

– Bare board (for impedance testing) expected ~today

– Assembled module expected 30th October

• Firmware – All IBERT cores generated– Control

• FPGA–FPGA interface in development

• All L1Calo modules – IPBus Common Register

definition proposed at L1Calo Weekly meeting• Incorporating feedback

15 October 2015

Simulation results from HyperLynx for typical track, attenuation vs. frequency

eFEX layout

Ian Brawn, on behalf of L1Calo

3

jFEX• Simplified board design

– Eliminated Merger FPGA– Control mezzanine– Modular design for Mpod

+ Processor FPGA “blocks”• Time reduction in board

design• Schematics almost finished;

layout ongoing• On schedule for Q1 2016

manufacture• 3D model of fibre routing

developed– Working on problems

exposed at Join meeting• Firmware in development

15 October 2015

Ian Brawn, on behalf of L1Calo

4

gFEX• Prototype 1a, no. 1 & 2:

– Without/with Proc FPGA (XC7VX550T)– Power, clock & Zynq commissioned– MGTs: 12.8 Gb/s, BER <1.2 1015

• 80 GTH (pFPGA)+ 16 GTX (Zynz) simultaneously

• Prototype 1b– Re-work (CDC->SiLab clock, DDR3, PHY)– Manufacture 24 Sept

• Prototype 2b: Full prototype– Design changes

• 4V7 → 3Ultrascale (XCVU160)• Redundant readout via Hub-ROD removed

(readout via FELIX)– Manufacture end of year– Routing well advanced

• Firmware– Control– Test engines– Algorithmic– GBT & TTC interfaces

15 October 2015

gFEX Prototype 1a, no. 2Done

IBERT eye for pFPGA→Fibre→pFPGA@ 12.8 Gb/s

Ian Brawn, on behalf of L1Calo

5

L1Topo• Expect only minor changes to Topo

required at Phase-I– Mezzanine upgrade for readout via

2 L1Calo Hub-RODs

• But… also plan to implement Phase-II requirements at Phase-I– Real-time RoI outputs

• Associated with L1As

• Need to evaluate (for Phase II)– Scale of required changes– Optimum system architecture– L1Topo upgrade plan

• Currently, L1Topo effort bound up in Run 2.

15 October 2015

Run-2 L1Topo

Ian Brawn, on behalf of L1Calo

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ROD• Initial layout completed in July• Power-supply issue :

– Switching noise from GE modules few x 10 mV

– Solution: ferrite inductors & isolated ground planes

• PCB manufacture underway• Quotes for assembly collected

• Fully assembled module expected end of November

• Firmware– First draft of firmware

specification circulated within L1Calo

15 October 2015

ROD prototype, 3D model

Power-Supply Test Board

Ian Brawn, on behalf of L1Calo

7

Hub• Delicate design process required at

the ROD/Hub interface– Tight space limitations after making

space for ROD– FEX data fidelity to ROD remains the

driving design philosophy

• Layout and routing underway• Assembled modules anticipated mid

December – early January.

• TTC SFP+ connector removed from design. – All optical I/O will be performed via

minipod

• Firmware design progressing in parallel to board design.

15 October 2015

Hub Layout

Ian Brawn, on behalf of L1Calo

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FOX• Design and production of demonstrator

complete: – Lar/TileFOX Demonstrator – e/j/gFOX Demonstrator

• 2U boxes with– MTP connectors– fanout cables, – Internal LC connectors, – Splitters

• Fibre fuser purchased, will start tests

• Mapping – Georges Aad & Michael Begel have

been working on mappings since Spring– Work well progressed– Schedule for documentation to be

written in September, but not happened yet

15 October 2015

FOX, block diagram

FOX Demonstrator Module

Ian Brawn, on behalf of L1Calo

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TREX• PDR held on 31st July

– PDR Agenda: https://indico.cern.ch/event/396166

– Specification:https://edms.cern.ch/document/1533071/0.2

– Report now public:– https://edms.cern.ch/ui/file/1533071/0.2/TRE

X_PDR_Report_v1.pdf

• Design approved– TREX not part of TDR design– Approval: panel recommends TREX be

adopted by ATLAS

• Actions identified include– Investigations into

• MGT clocking scheme• Power & cooling• Fibre mechanics

• Manufacture Q1 2016

• Recruitment required

15 October 2015

TREX Block Diagram

Ian Brawn, on behalf of L1Calo

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FTM• Simpler design than eFEX but

same PCB material & build

• 2 assembled FTMs delivered– Initial tests underway– Some problems connecting

with JTAG chain

• Firmware development– Control

• IPBus readout of FPGA temperatures and voltages added

• Work on MGTs underway

15 October 2015

FTM Prototype

Ian Brawn, on behalf of L1Calo

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Link-Speed Tests• Hardware Schedule

– Slip in eFEX schedule link-speed tests late January• LAr informed

– jFEX will arrive too late for LAr deadline• L1Calo must define how extrapolate from eFEX test results to jFEX

conclusions

• LAr–L1Calo Meeting 15th Oct, 4pm– https://indico.cern.ch/event/453211/– Discussion of

• Schedule: to fix dates of tests • Test Lab: location, identification of joint infrastructure

– Long-term facility for LAr-L1Calo-etc. tests• Firmware: requirements, link protocol, test patterns • Test Plan: Review of latest document

• Manufacture additional gFEX to provide focus for test rig commissioning?– Evaluate schedule to assess benefit

15 October 2015