l14-intstruct-busint

8/6/2019 L14-IntStruct-BusInt

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Interconnection structures

Computer consists of set of components (or modules) of 3

basic types.

CPU

Memory

I/O

These components communicate with each other.

The collection of paths connecting various modules is calledasInterconnection structure .

There may be different designs of interconnection structure

depending upon exchanges that must be made b/w the

modules.


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Memory:

Consists of N words of equal length

Receives and sends data

Nature of operation is indicated by Read and Write control signal

Location for operation is specified by an address

I/O Module:

Functionally similar to memory module

It has 2 operations Read and Write

Can control more than one external device. Each interface to anexternal device is called as aPort

Has external data paths for input and output data Able to send interrupt signals to the CPU


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CPU:

Reads instruction and data

Writes out data (after processing)

Sends control signals to other units

Receives (& acts on) interrupts


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Interconnection structure must support following types oftransfers:

Memory to CPU: CPU reads instruction/data from memory

CPU to Memory : CPU writes unit of data to memory

I/O to CPU: CPU reads data from I/O device or via I/Omodule

CPU to I/O : CPU sends data to I/O device.

I/O to or from Memory : An I/O module is allowed toexchange data directly with memory, without help of CPU,using Direct Memory Access (DMA).


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Bus InterconnectionWhat is a Bus?

A communication pathway connecting two or more devices

Bus is a shared transmission medium

Usually broadcast: multiple devices connect to the bus and a

signal transmitted by any one of device is available for receptionby all other devices attached to the bus

Only one device at a time can successfully transmit, because iftwo devices transmit during same time, their signals will overlapand become garbled.

Often grouped

A number of channels (lines) are grouped in one bus

e.g. 32 bit data bus has 32 separate single bit lines

Bits can transmit simultaneously on these lines.


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Computer system contain a number of different buses that

provide pathways between components.

A bus that connects major computer components (CPU,memory, I/O) is called a System Bus.

There can be many different bus designs. On any bus the lines

can be classified into 3 functional groups:

Data lines Address lines

Control lines


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Data Bus

Provides path for moving data

Remember that there is no difference between data and

instruction at this level

Typically consists of 8,16,32,64 separate data lines. Number of

data lines being referred to as Width of data bus.

Each line can carry only 1 bit at a time, so width of data bus

determines how many bits can be transferred at a time.

Width is the key factor for determining overall system

performance.

If a data bus is 8 bits wide and each instruction is 16 bits longthen CPU must access the memory module 2 times during each

instruction cycle.


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Address Bus

Identify the source or destination of data.

e.g. if CPU wishes to read data from memory, it will put address

of desired word on the address bus.

Width of address bus determines maximum possible memory

capacity of the system.

e.g. 8080 has 16 bit address bus giving 64k address space

Can also be used to address I/O ports.


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Control Bus

Used to control access to data and address lines.

Used to control use of data and address lines.

Such control is needed because data and address lines are shared

by all components.

Both command and timing information is transmitted on the bus.

Command signal specify operations to be performed

Timing signal indicate validity of data and address info.


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Architecture

Multiple Bus hierarchy


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Elements ofBus Design

Following are the elements of Bus Design:

1. Bus Type : Dedicated, Multiplexed

2. Method of Arbitration : Centralized, Distributed

3. Timing : Synchronous, Asynchronous

4. Bus Width

5. Data transfer Type


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1.Bus Type

Dedicated Permanently assigned to one function or to a physical

subset of computer components

Dedicated to a function means e.g. Separate data & addresslines

Physical dedication means refers to use of multiple buses,

each of which connects to a subset of modules. e.g. use of

an I/O bus to interconnect all I/O modules, this bus is then

connected to the main bus. Advantage of having physical dedication is high throughput

Disadvantage is increased size and cost of the system


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Multiplexed Shared lines

E.g. address and data information may be transmitted over

the same set of lines using an address valid control line. At

the beginning of data transfer, address is placed on the bus

and address valid line is activated. Each module has

specified time to copy address from the bus. The address isthen removed from the bus and same bus is then used for

subsequent read and write data transfer.

Advantage is use of fewer line, which saves space and cost.

Disadvantage is more complex circuitry is needed.

Performance is reduced as events that share the same line

cannot take place in parallel.


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2. Method ofArbitration

If more than one module need control of bus then some method

of arbitration is needed. Because only one module at a time can

transmit successfully over the bus.

Methods are classified as:

Centralized Distributed

In centralized scheme, a single hardware device, bus controller

orarbiteris used for allocation time on the bus.

In distributed scheme, there is no central controller. Here each

module contains access control logic and module act together to

share the bus.


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3. Timing

The way in which events are coordinated on the bus.

Synchronous

Events determined by clock signals

Control Bus includes clock line

A single 1-0 transmission is called as clock/bus cycle

All devices on the line can read clock line

Asynchronous

Events follows and depend on occurrence of previous event Synchronous timing is simpler to implement and test but less

flexible than asynchronous timing


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4.Bus Width Bus width refers to no. of line in a bus.

Width of data bus has an impact on system performance--wider the data bus, greater the no. of bits transferred at a time

Width of address bus has an impact on system capacity

--wider the address bus, greater the range of locations that can be

referenced

5.Date Transfer Type Read

Write

Read-modify-write : read followed immediately by a write to thesame address. The whole operation is typically indivisible.

Read-after-write : An indivisible operation consist of a write

followed immediately by a read from the same address

Block data transfer: one address cycle is followed by n data cycles.

l14-intstruct-busint

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