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L12: 6.111 Spring 2008 1Introductory Digital Systems Laboratory
L12: Reconfigurable Logic ArchitecturesL12: Reconfigurable Logic Architectures
Acknowledgements:
Lecture material adapted from R. Katz, G. Borriello, “Contemporary Logic Design”(second edition), Copyright 2005 Prentice-Hall/Pearson Education.
Frank Honore
Lecture Notes prepared by Professor Anantha Chandrakasan
L12: 6.111 Spring 2008 2Introductory Digital Systems Laboratory
History of Computational FabricsHistory of Computational Fabrics
Discrete devices: relays, transistors (1940s-50s)Discrete logic gates (1950s-60s)Integrated circuits (1960s-70s)
e.g. TTL packages: Data Book for 100’s of different parts
Gate Arrays (IBM 1970s)Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming)
Software Based Schemes (1970’s- present)Run instructions on a general purpose core
Programmable Logic (1980’s to present)A chip that be reprogrammed after it has been fabricatedExamples: PALs, EPROM, EEPROM, PLDs, FPGAsExcellent support for mapping from Verilog
ASIC Design (1980’s to present)Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon area
L12: 6.111 Spring 2008 3Introductory Digital Systems Laboratory
Reconfigurable LogicReconfigurable Logic
Logic blocksTo implement combinationaland sequential logic
InterconnectWires to connect inputs andoutputs to logic blocks
I/O blocksSpecial logic blocks at periphery of device forexternal connections
Key questions:How to make logic blocks programmable?(after chip has been fabbed!)What should the logic granularity be?How to make the wires programmable?(after chip has been fabbed!)Specialized wiring structures for localvs. long distance routes?How many wires per logic block?
LogicLogic
Configuration
Inputs Outputsn m
Q
QSET
CLR
D
L12: 6.111 Spring 2008 4Introductory Digital Systems Laboratory
Programmable Array Logic (PAL)Programmable Array Logic (PAL)
Based on the fact that any combinational logic can be realized as a sum-of-productsPALs feature an array of AND-OR gates with programmable interconnect
input signals
output signals
programming of product terms
programming of sum terms
AND array OR array
L12: 6.111 Spring 2008 5Introductory Digital Systems Laboratory
Inside the 22v10 PALInside the 22v10 PAL
Each input pin (and its complement) sent to the AND arrayOR gates for each output can take 8-16 product terms, depending on output pin“Macrocell” block provides additional output flexibility...
L12: 6.111 Spring 2008 6Introductory Digital Systems Laboratory
Cypress PAL CE22V10Cypress PAL CE22V10
Combinational/active low
Combinational/active high
Outputs may be registered or combinational, positive or inverted
From Lattice SemiconductorFrom Cypress
L12: 6.111 Spring 2008 7Introductory Digital Systems Laboratory
RAM Based Field Programmable RAM Based Field Programmable Logic Logic -- XilinxXilinx
CLB
CLB
CLB
CLB
SwitchMatrix
ProgrammableInterconnect I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
Pad
D QSD
RDEC
S/RControl
D QSD
RDEC
S/RControl
1
1
F'G'
H'
DIN
F'G'
H'
DIN
F'
G'H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
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The Xilinx 4000 CLBThe Xilinx 4000 CLB
L12: 6.111 Spring 2008 9Introductory Digital Systems Laboratory
Two 4Two 4--input Functions, Registered Outputinput Functions, Registered Output and a Two Input Functionand a Two Input Function
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55--input Function, Combinational Outputinput Function, Combinational Output
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LUT MappingLUT Mapping
N-LUT direct implementation of a truth table: any function of n-inputs.N-LUT requires 2N storage elements (latches)N-inputs select one latch location (like a memory)
4LUT example
Latches set by configuration bitstream
Inputs
Output
Why Latches and Not Registers?
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Configuring the CLB as a RAMConfiguring the CLB as a RAM
Memory is built using Latches not FFs
Read is same a LUT Function!
16x2
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Xilinx 4000 InterconnectXilinx 4000 Interconnect
L12: 6.111 Spring 2008 14Introductory Digital Systems Laboratory
Xilinx 4000 Interconnect DetailsXilinx 4000 Interconnect Details
Wires are not ideal!
L12: 6.111 Spring 2008 15Introductory Digital Systems Laboratory
Xilinx 4000 Flexible IOBXilinx 4000 Flexible IOB
Adjust Transition Time
Adjust the Sampling Edge
Outputs through FF or bypassed
L12: 6.111 Spring 2008 16Introductory Digital Systems Laboratory
Add Bells & WhistlesAdd Bells & Whistles
Hard Processor
I/O
BRAM
Gigabit Serial
Multiplier
Programmable Termination
Z
VCCIO
Z
Z
ImpedanceControl Clock
Mgmt
18 Bit
18 Bit36 Bit
Courtesy of David B. Parlour, ISSCC 2004 Tutorial, “The Reality and Promise of Reconfigurable Computing in Digital Signal Processing”
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The The VirtexVirtex II CLB (Half Slice Shown)II CLB (Half Slice Shown)
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Adder ImplementationAdder Implementation
Y = A ⊕ B ⊕ CinAB
Cin
CoutLUT: A⊕B
1 half-Slice = 1-bit adder
Dedicated carry logic
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Carry ChainCarry Chain
1 CLB = 4 Slices = 2, 4-bit adders
64-bit Adder: 16 CLBs
+
CLB15
CLB0A[3:0]B[3:0]
A[63:60]B[63:60]
A[63:0]
B[63:0]Y[63:0]
Y[3:0]
Y[63:60]
Y[64]
CLBs must be in same column
CLB1A[7:4]B[7:4] Y[7:4]
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VirtexVirtex II FeaturesII Features
Double Data Rate registers Digital Clock Manager
Embedded MultiplierBlock SelectRAM
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The Latest Generation: The Latest Generation: VirtexVirtex--II ProII Pro
Courtesy XilinxHigh-speed I/O
Embedded PowerPc
Embedded memories
Hardwired multipliers
FPGA Fabric
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AlteraAltera’’ss New New StratixStratix ArchitectureArchitecture
Embedded DSP feature: 9x9, 18x18, 36x36 with 52-bit accumulatorUp to 11,310 LE’s, 10Mbits RAM10 LE’s per LAB
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Design Flow Design Flow -- MappingMapping
Technology Mapping: Schematic/HDL to Physical Logic unitsCompile functions into basic LUT-based groups (function of target architecture)
always @(posedge Clock or negedge Reset)beginif (! Reset)
q <= 0;else
q <= (a & b & c) | (b & d);end
Q
QSET
CLR
D
LUTQ
QSET
CLR
D
abc
db
L12: 6.111 Spring 2008 24Introductory Digital Systems Laboratory
Design Flow Design Flow –– Placement & RoutePlacement & Route
Placement – assign logic location on a particular device
LUT
LUT
LUT
Routing – iterative process to connect CLB inputs/outputs and IOBs. Optimizes critical path delay – can take hours or days for large, dense designs
Iterate placement if timing not met
Satisfy timing? Generate Bitstream to config device
Challenge! Cannot use full chip for reasonable speeds (wires are not ideal). Typically no more than 50% utilization.
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Example: Example: VerilogVerilog to FPGAto FPGA
module adder64 (a, b, sum); input [63:0] a, b; output [63:0] sum;
assign sum = a + b;endmodule
Virtex II – XC2V2000
• Synthesis• Tech Map• Place&Route
64-bit Adder Example
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How are How are FPGAsFPGAs Used?Used?
(courtesy of IKOS)FPGA-based Emulator
Logic EmulationPrototyping
Ensemble of gate arrays used to emulate a circuit to be manufacturedGet more/better/faster debugging done than with simulation
Reconfigurable hardwareOne hardware block used to implement more than one function
Special-purpose computation engines
Hardware dedicated to solving one problem (or class of problems)Accelerators attached to general-purpose computers (e.g., in a cell phone!)
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SummarySummary
FPGA provide a flexible platform for implementing digital computingA rich set of macros and I/Os supported (multipliers, block RAMS, ROMS, high-speed I/O)A wide range of applications from prototyping (to validate a design before ASIC mapping) to high-performance spatial computingInterconnects are a major bottleneck (physical design and locality are important considerations)
“College students will study concurrent programming instead of “C” as their first
computing experience.”
-- David B. Parlour, ISSCC 2004 Tutorial