l1 mos model
TRANSCRIPT
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MOS MODEL
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In this lecture, you will learn about
Basic components that form MOS model.
Basic equations that describe these functions andcomponents.
Small signal model useful for analog design.
Contact Information: A/P Ganesh Samudra, Tel: 6516-2293, email:
[email protected] Room : E5 03-13.
mailto:[email protected]:[email protected] -
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S G
N+
D
N+
Schematic representation of MOSFET is shown below.The main purpose of MOS model to represent thecomplex MOS device with simple circuit elements likedependent sources, capacitors and resistors.
Although we would like to see MOSFET as a gatevoltage controlled current source like below, unwantedparasitic devices/elements are always present as aconsequence of actual physical structure of MOSFET.
MOS Model-Dependent Source
Id Source
We will now develop each of these elements.
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S G
N+
D
N+
The primary device functions through the gate
capacitance. As gate overlaps with the bulk (also calledbody or substrate), the source and drain, this capacitancecan be distributed between all these 3 terminals givingfollowing representation for the gate capacitance.
MOS Model-Gate Capacitance
CGB
CGDCGS
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S G
N+
D
N+
Along the width direction, S/D doped regions normally
diffuse laterally under the gate which gives this overlapcapacitance. When positive voltage is applied to the gate,these N+ regions pileup (accumulate) negative chargedelectrons below the gate oxide giving overlap parasiticcapacitances as shown below.
MOS Model-Overlap Capacitance
C GSO C GSO CGDO
Gate-S and D Overlap Regions
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S G
N+
D
N+
There is parasitic resistance from terminals of S/D
(Source/Drain) to the inversion layer as current has toflow through doped regions. This is modeled as a normalresistor.
MOS Model-S/D Resistance
RD
RS
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S G
N+
D
N+
N+ S/D regions form N+P junction with substrate due to
vertical implant and diffusion of dopants. They form a junction diode and also have junction capacitancesassociated with them as shown below. The junctioncapacitance and diode current values are proportional toarea of the junction.
MOS Model- Bottom Junction
S-Bulkbottom
JunctionCapacitance
S-Bulkbottom
JunctionDiode
D-Bulkbottom
JunctionCapacitance
D-Bulkbottom
JunctionDiode
Vertical Implant/Diffusion
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S G
N+
D
N+
N+ S/D regions form N+P sidewall junction with substrate
due to lateral encroachment of implant and diffusion ofdopants under the gate. They form a junction diode andalso have junction capacitances associated with them asshown below. The junction capacitance and diode currentvalues are proportional to perimeter of the junction.
MOS Model-Sidewall Junction
D SidewallJunction
Diode and
capacitance
S SidewallJunction
Diode and
capacitance
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SPICE MODEL for MOSFET
C GBO is in missing dimension shown on layout
width edges due to birds beak encroachment.
S G
D
C GSO C GDO
N + N +
SBdiode(genreversebiased)
SBSide wallCap &diode
DBSidewall
diode andcapacitance
C GB
R S R D
C GD C G S
Noise Source
I d Source
Source toBulk (SB)bottomcapacitance
DBdiode&bottomcap
B
Overall MOS Model
Combining all aboveelements and adding anoise source in
parallel, we have theintegrated model.
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S G
N+
D
N+
Now we will look at sample of detailed models for each of
the elements described in the previous slides. The first element is the dependent current source
between S and D. This models how I d depends on V DS ,VGS , VBS and the dependence is modified with short
channel effects. All these parameters are grouped in thispart.
MOS Model-Dependent Source
Id Source
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* The following basic set of 6 parameters determines theproperties of the current source, I
d.
VTO : Zero bias, long channel threshold voltage.
KP: called as transconductance parameter so that KP = COX(see below) and hence has units of A/V 2.
GAMMA (): Bulk threshold parameter which specifiesdependence of V T on V BS . Called body effect.
PHI : Surface potential. Mainly determined by substrate
doping. LAMBADA (): Channel length modulation parameter.
Models increase in drain current with increase in V DS in thesaturation region.
MOS Model-Dependent Source
f )(
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In this simple level 1 model that we will use,
Subthreshold Region.
Linear region
saturation region.
MOS Model-Dependent Source
TGS D VVfor0I
DS2DSDSTGSox D V1V21 -VV-VC
LW
I
'DSDSTGS VV,VVfor
DS 2TGSox D V1V-VC2LW
I
'DSDSTGS VV,VVfor
.VV-VVwhere DSATTGS'DS
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Normally, a compact notation is used to express the currentwith .
The actual threshold voltage is found with the followingexpressions.
where D is drain induced barrier lowering parameter thatreduces V T at higher V DS for short channel devices and
Vfb is the flat band voltage. V TO is the Zero bias, longchannel threshold voltage and PHI is the surfacepotential, mainly determined by substrate doping as onthe next slide.
MOS Model-Dependent Source
ox CL
W
V - V +2+2+V =V DS DSB f f fbT
2+2+V =V f f fbT 0
f )(
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The other quantities in the equation are VT = threshold voltage = Surface mobility of the carriers W = Width of the MOS device L = Length of the MOS device ND NA = Net doping concentration in the channel and ni = the intrinsic carrier concentration.
MOS Model-Dependent Source
and N-N
lnq
kT
i
AD
n f
,C
N-Nq2 )(
OX
ADsi parameter effect body
.thicknessoxidebeingd ,d
C oxox
oxOX
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Clearly, change in the threshold voltage due to bodyeffect or substrate bias effect is given by
Note that the p-substrate of n-channel devices is alwaysgrounded. The n-substrate of p-channel devices isgenerally tied to the power supply voltage V DD or couldalso be shorted to the source to eliminate body effectcompletely.
If any of these parameters are not specified, they arecalculated with device physics equations and some otherparameters related to process such as d OX, oxidethickness for gate, N Sub , substrate doping, NSS surfacestate density, NFS fast surface state density, etc.
MOS Model-Dependent Source
][ 2 V +2 =V f SB f T
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The characteristics for N channel device using equationsabove are as shown. They help determine by extendingthe saturation region I
Dto negative V
DSaxis.
MOS Model-Dependent Source
In addition, the velocity saturation effect can be includedby adding a critical field parameter or reducing saturationcurrent exponent below 2 and reducing the saturationvoltage V DS . Higher level models in circuit simulators likeSPICE have much larger set of parameters for accuracy.
VGS = V T + 1
VGS = V T + 2
VGS = V T + 3
VDS
ID
1/ Figure : I D vs V DS characteristics
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S G
N+
D
N+
These are modeled through 3 non-linear bias dependent
capacitances C GS , C GD, C GB defined by piecewise linearMeyers model. There are other advanced modelsavailable for more accuracy and at higher frequency.
MOS Model-Gate Capacitance
CGB
CGDCGS
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Meyer model for gate capacitance.
Linear Region - strong inversion
MOS Model-Gate Capacitance
0=C GB
])2V T 2-V GS+V GD(
)2V T -V GS( -[1WLC ox32 =C GD
])2V T 2-V GS+V GD(
)2V T -V GD( -[1WLC ox32
GS =C
Saturation Region -strong inversion
C GB=0=C GD
WLC ox32
GS =C
Weak inversion Ignored in the simple model.
Why these both are zero?
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S G
N+
D
N+
there are three overlap capacitances.
CGSO: Gate to source overlap capacitance per meter ofchannel width. This and drain overlap capacitance(CGDO) are independent of length L as they areassociated with edge effects along the width.
MOS Model-Overlap Capacitance
C GSO C GSO CGDO
Gate-S and D Overlap Regions
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CGBO: Gate to bulk overlap capacitance per meter ofchannel length and is associated with edge effects at thewidth ends of the gate area. This capacitance is not seenin the slides as it is in the third dimension missing in ourfigures.
MOS Model-Overlap Capacitance
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S G
N+
D
N+
RS and R D are the source and drain resistances due towhich inside source and drain voltages applied to actual
inversion layer will change as there will be voltage drops.They are specified normally as an effective sheetresistance of S/D regions and found using number ofsquares in S/D regions.
MOS Model-S/D Resistance
RDRS
How to find number of squares in S/D regions?
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S G
N+
D
N+
The source to substrate and drain to substrate bottom junction parasitic diodes are modeled with ( Expectation?)
MOS Model- Bottom Junction
S-Bulkbottom
JunctionCapacitance
S-Bulkbottom
JunctionDiode
D-Bulkbottom
JunctionCapacitance
D-Bulkbottom
JunctionDiode
1eAII kTdiodeqV
sdiode
where I S is reverse saturationcurrent per unit area modelparameter and A is the junctionarea. Since junctions are reversedbiased in MOS, I diode -AI s.
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Although these S-D region doping profiles are quite
complex, the junction capacitance is calculated usingsimple abrupt junction capacitance formula fromEE2004/EE2021 for simplicity. Since source draindoping profiles are normally the same, the bottom
capacitances are modeled with CJ: Zero bias bulk junction bottom capacitance per unit
area
MJ: Bulk junction bottom grading coefficient
PB: Bulk junction built in potential
MOS Model- Bottom Junction
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The model is based on the same equation with step junction and depletion approximation in EE2004/EE2021so that
MOS Model- Bottom Junction
MJ
BSBD
SD
PB)V(V
-1
CJ)(AA(Source)drainateCapacitanc
layout.fromce)drain(Sourtheof areatheis)(AAwhere SD
Here, the expressions in parenthesis () apply to sourceand the expression replaces the drain term just precedingthe parenthesis.
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S G
N+
D
N+
The source to substrate and drain to substrate sidewall junction parasitic diodes are modeled with
MOS Model-Sidewall Junction
D SidewallJunction
Diode and
capacitance
S SidewallJunction
Diode and
capacitance
1ePII kTdiodeqV
sdiode
where I S is reverse saturation currentper unit length model parameter and Pis the junction perimeter. Since
junctions are reversed biased in MOS,Idiode -PI s.
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Although these S-D region sidewall (lateral) doping
profiles are quite complex, the junction capacitance iscalculated using simple abrupt junction capacitanceformula from EE2004/EE2021 for simplicity. Since source
drain sidewall doping profiles are normally the same,
the sidewall capacitances are modeled with CJSW: Zero bias bulk junction bottom capacitance per
unit length
MJSW: Bulk junction bottom grading coefficient
PB: Bulk junction built in potential taken same as that ofthe bottom junction.
MOS Model- Sidewall Junction
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The model is based on the same equation with step junction and depletion approximation in EE2004/EE2021so that
MOS Model- Sidewall Junction
MJSWBSBD
SD
PB
)V(V -1
CJSW)(PP(Source)drainateCapacitancSidewall
layout.fromce)drain(Sourtheof perimetertheis)(PPwhere SD
Here, the expressions in parenthesis () apply to sourceand the expression replaces the drain term just precedingthe parenthesis.
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In addition, there are noise coefficients which may addsome noise to I D. As one can see, this model ignoresmany parasitic resistances, bipolar devices and PNPNdevices.
This completes the discussion on accurate modeling ofMOSFET.
MOS Model
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The model shown earlier is good for circuit simulation, buttoo complex for simple hand calculations of gain, cornerfrequency, output resistance, etc. For this purpose,simpler small signal model is developed in this part.
In this analysis, a small AC signal v is superimposed onnormal DC biases. In the notations, AC signals willnormally use all small letters, DC all capitals and totalvoltage with AC and DC components added will usemixed case. For example, V OUT is a DC voltage, v out ACvoltage and V out is the total voltage (this is normally usedin large signal response which is determined by the totalvoltage).
Lumped Small Signal (AC) Model for MOSFET
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The effect of gate voltage is modeled usingtransconductance
Hence this gm
models how drain current will change withchange in gate voltage (which is the AC voltage applied tothe gate). Normally, the input voltage applied to the gatechanges I D and hence changes output voltage, normallytaken at the drain.
Lumped Small Signal (AC) Model for MOSFET
.GSVDI mg
This effect is captured as adependent current sourcecircuit element between drainand source.
gmVgs
D
S
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In the linear region,
by taking partial derivative of the model equation in thelinear region. Hence there is a drop with decreasing drainto source voltage.
In the saturation region where many analog amplifiersoperate,
Lumped Small Signal (AC) Model for MOSFET
.V1VCLWg DSDSox m
.V-V
I2V1V-VCLWg
TGS
DDS TGSox m
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The effect of the drain voltage is modeled using the drainconductance
This models how I D changes when the output voltagenormally taken at the drain changes. Since we want onlyinput voltage to affect I D and not the output voltage,ideally, this should be zero.
Hence in saturation region using I D expression in the
model
This effect is captured as a resistor circuit elementbetween drain and source.
Lumped Small Signal (AC) Model for MOSFET
.DSVDI dg
D2TGSox d IV-VC2LW
g
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The effect of body bias or substrate voltage is modeledusing transconductance
by taking partial derivative of the model equation.
Hence this value is mainly determined by as thedependence is through changes in V T. This effect iscaptured as a dependent current source circuit element
between drain and source.
Lumped Small Signal (AC) Model for MOSFET
,BSVDI mbg
All these three componentsare heavily dependent onthe models used.
gmVsb
D
S
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The complete AC representation for nMOS device iscaptured in the following figure. We add all capacitors thatare in parallel to lump them together as though they areconstant mainly determined by DC voltages (Which onceare combined in each one?). For analytic calculations,this is adequate. Circuit simulators like SPICE can take
care of actual voltage dependencies.
Lumped Small Signal (AC) Model for MOSFET
G
C gb
C gs
C sb
S
g mv gs g mbv sbr 0 = . 1
g d
D
C db
C gd