l1 intro r1.ppt [호환 모드]

1

Digital Integrated Circuit DesignDigital Integrated Circuit DesignL1 Introduction

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General InformationGeneral Information

Instructor : Jinyong [email protected] 312, LG Research Building(Tue, Thu), g( , )Mailbox @copyroom on 2nd floorOffice: x5016(LG312), x0204(NCNT)

GradingHomework - 30%

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Term Project - 30%Midterm Exam- 20%Final Exam - 20%

2

(continued)(continued)

Design Project32bit x 32bit NAND Flash

1.8V operationtransistor model: TBPControl logic (ECC optional) design & simulationcircuit design and simulationReport on target & performance comparison

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Report on target & performance comparison /analysisFinal Report by 12/11

(continued)(continued)Baseline textbook디지털집적회로, 대영사, 박홍준Digital Integrated Circuits By J. Rabaey, A. Chandrakasan, B. Nikolicy y, ,Prentice Hall

ReferenceAnalysis and Design of Digital Integrated Circuits

in deep submicron technologyBy D. Hodges, H. Jackson, R. SalehMcGraw Hill

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Class Material on webClass schedule

Mid term: 10/21 (Tue)Final on 12/18 (Thu)

3

Class GoalsClass GoalsDigital Integrated Circuits

CMOS gatesPropagation delay, noise margins and power dissipation FOM’sdissipation, FOM sCombinational and sequential circuitsArithmetic, Datapath, Memory, Clock and InterconnectDesign for Testability

What will you learn?U d t di d i i d ti i i di it l

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Understanding, designing and optimizing digital circuits with respect to quality metrics: speed, power, cost and reliabilityCircuit Design (design & simulation, layout) on flash memory

Digital Integrated CircuitsDigital Integrated CircuitsIntroduction: Issues in digital designTh CMOS i tThe CMOS inverterCombinational logic structuresSequential logic gatesMemory CircuitDesign for TestabilityInterconnect: R L and C

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Interconnect: R, L and CTimingArithmetic building blocksDesign methodologies

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IntroductionIntroductionWhy is digital IC design different today than it was before?Differences from other disciplinesFuture perspectives

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The First Integrated Circuits The First Integrated Circuits

Bipolar logicp g1960’s

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ECL 3-input GateMotorola 1966

© Digital Integrated Circuits2nd

5

Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor

19711000 transistors1 MHz operation

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Dual core microprocessor Dual core microprocessor (Montecito, 90nm)(Montecito, 90nm)

1.72 * 10^9 tr

596 mm^2

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6

Transistor (90 nm technology)

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From Mark Bohr

DNA strand ~ 10nm

Intel

Wires (65nm process)8 layers of Metal (Cu)4 in X, 4 in Y directionVias connect layersWire delay determined by C and R Higher layer – bigger wire - smaller delayWidth can be controlled

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Width can be controlled

From Mark Bohr Intel

7

Process scalingProcess scalingHigh Volume High Volume ManufacturingManufacturing

20042004 20062006 20082008 20102010 20122012 20142014 20162016 20182018

Technology Node Technology Node (nm)(nm)

9090 6565 4545 3232 2222 1616 1111 88

Integration Capacity Integration Capacity (BT)(BT)

2 4 8 16 32 64 128 256

Delay = CV/I scalingDelay = CV/I scaling 0.70.7 ~0.7~0.7 >0.7>0.7 Delay scaling will slow downDelay scaling will slow down

Energy/Logic Op Energy/Logic Op scalingscaling

>0.35>0.35 >0.5>0.5 >0.5>0.5 Energy scaling will slow downEnergy scaling will slow down

Bulk Planar CMOSBulk Planar CMOS High Probability Low ProbabilityHigh Probability Low ProbabilityAlternate, 3G etcAlternate, 3G etc Low Probability High ProbabilityLow Probability High Probability

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VariabilityVariability Medium High Very HighMedium High Very HighILD (K)ILD (K) ~3~3 <3<3 Reduce slowly towards 2Reduce slowly towards 2--2.52.5RC DelayRC Delay 11 11 11 11 11 11 11 11Metal LayersMetal Layers 66--77 77--88 88--99 0.5 to 1 layer per generation0.5 to 1 layer per generation

From Pat Gelsinger Intel

Moore’s Law and its costs Moore’s Law and its costs

1.E+01

1.E+02

1.E+03

1.E+04

MIP

s

$ per MIPS$ per MIPS

$100

$1,000

$10,000

st ($

M)

FAB CostFAB Cost

1.E-02

1.E-01

1.E+00

1960 1970 1980 1990 2000 2010

$/M

1 E 03

1.E-02

1.E-01

stor

$ per Transistor$ per Transistor

1.E+01

1.E+02

1.E+03

l ($)

Per ChipTest CapitalTest Capital

$1

$10

$100

1960 1970 1980 1990 2000 2010

Fab

Cos

www.icknowledge.com

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1.E-06

1.E-05

1.E-04

1.E-03

1960 1970 1980 1990 2000 2010

$/Tr

ansi

s

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1980 1990 2000 2010

Test

Cap

ital

Based on SIA roadmap

Intel

8

Moore’s LawMoore’s LawIn 1965, Gordon Moore noted that the

number of transistors on a chip doublednumber of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months


Moore’s LawMoore’s Law1615IO

N

1413121110

9876543LO

G2 O

F TH

E N

UM

BER

OF

ON

ENTS

PER

INTE

GR

ATE

D F

UN

CTI

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210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

CO

MPO

Electronics, April 19, 1965.


9

Evolution in ComplexityEvolution in Complexity


Transistor CountsTransistor Counts

1,000,000K

1 Billion 1 Billion TransistorsTransistors1,000,000

100,000

10,000

1,000

100 80286i386

i486Pentium®

Pentium® ProPentium® II

Pentium® III

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10

11975 1980 1985 1990 1995 2000 2005 2010

8086Source: IntelSource: Intel

ProjectedProjected

Courtesy, Intel© Digital Integrated Circuits2nd

10

Die Size GrowthDie Size Growth100

)

40048008

80808085

8086286

386486 Pentium ® procP6

1

10

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

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11970 1980 1990 2000 2010

Year

Die size grows by 14% to satisfy Moore’s Law


FrequencyFrequency

1000

10000

hz)

Doubles every2 years

P6Pentium ® proc

48638628680868085

8080800840040 1

1

10

100

Freq

uenc

y (M

h y

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0.11970 1980 1990 2000 2010

Year

Lead Microprocessors frequency doubles every 2 years


11

Power DissipationPower DissipationP6

Pentium ® proc

100

s)

486386

2868086

808580808008

4004

0.1

1

10

Pow

er (W

atts

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0.11971 1974 1978 1985 1992 2000

Year

Lead Microprocessors power continues to increase


Power densityPower density

1000

10000

W/c

m2) Rocket

Nozzle

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

Pow

er D

ensi

ty (W

Hot Plate

NuclearReactor

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11970 1980 1990 2000 2010

Year

Power density too high to keep junctions at low temp


12

Challenges in Digital DesignChallenges in Digital Design

∝ DSM ∝ 1/DSM

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

∝ DSM ∝ 1/DSM

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Clock distribution.

Everything Looks a Little Different…and There’s a Lot of Them!?


Productivity TrendsProductivity Trends

1,000,000

10,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

10,000

1,000

er C

hip

(M)

10,000

100,000

Mo.

1

10

100

1,000

10,000

100,000

33 5 3 5 5

10

100

1,000

10,000

100,000

1,000,000

xxxx

xx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

pe

0.01

0.1

1

10

100

1,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-M

Com

plex

ity

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2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap© Digital Integrated Circuits2nd

13

Why Scaling?Why Scaling?Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xBut …

How to design chips with more and more functions?Design engineering population does not double every

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Design engineering population does not double every two years…

Hence, a need for more efficient design methodsExploit different levels of abstraction


Design Abstraction LevelsDesign Abstraction LevelsSYSTEM

+

CIRCUIT

GATE

MODULE

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n+n+S

GD

DEVICE


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Design MetricsDesign Metrics

How to evaluate performance of a digital circuit (gate block )?digital circuit (gate, block, …)?

CostReliabilityScalabilitySpeed (delay, operating frequency) P di i ti

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Power dissipationEnergy to perform a function


Cost of Integrated CircuitsCost of Integrated CircuitsNRE (non-recurrent engineering) costs

design time and effort, mask generationone-time cost factor

Recurrent costssilicon processing, packaging, test

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proportional to volumeproportional to chip area


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NRE Cost is IncreasingNRE Cost is Increasing


Die CostDie Cost

Single dieSingle die

Wafer

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Going up to 12” (30cm)


16

YieldYield%100

per wafer chips ofnumber Totalper wafer chips good of No.

×=Y

costWafer costDie =yield Dieper wafer Dies

cost Die×

=

( )area die2

diameterwafer area die

diameter/2wafer per wafer Dies2

××π

−×π

=


DefectsDefects

α−⎟⎞

⎜⎛ ×+=

area dieareaunit per defects1yielddie

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⎟⎠

⎜⎝ α+1yield die

α is approximately 3

4area) (die cost die f=


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Reliability―Reliability―Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits

i(t)

Inductive coupling Capacitive coupling Power and ground

v(t) VDD

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p g p p g gnoise


DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic

V(y)

VOH = f(VOL)VOH

VOL

VM

fV(y)=V(x)

Switching Threshold

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

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V(x)

OL

VOHVOL

Nominal Voltage Levels


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Mapping between analog and digital signalsMapping between analog and digital signals

Slope = -1V

VoutVOH“1” Slope 1

Slope = -1

V OH

VIL

VIH

UndefinedRegion

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V IL V IH V in

p

V OL“0” VOL

IL


Definition of Noise MarginsDefinition of Noise Margins

"1"

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

VOH

VOL

NMH

NML

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"0"

Gate Output Gate Input


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Noise BudgetNoise BudgetAllocates gross noise margin to expected sources of noiseSources: supply noise, cross talk, interference, offsetDifferentiate between fixed and

ti l i

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proportional noise sources


Key Reliability PropertiesKey Reliability PropertiesAbsolute noise margin values are deceptive

a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)

Noise immunity is the more important metric –the capability to suppress noise sourcesKey metrics: Noise transfer functions Output

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Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;


20

Regenerative PropertyRegenerative Property

vout

vout

v1

v3

finv(v)

f (v)

v3

v1

f (v)

finv(v)

v3

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v0 v2 in

Regenerative Non-Regenerativev2 v0 in


Regenerative PropertyRegenerative Property

v v v v v v v

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

(Vol

t) v03

5

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2

V

4

v1v2

t (nsec)0

2 1

1

6 8 10Simulated response


21

FanFan--in and Fanin and Fan--outout

NM

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Fan-out N Fan-in M


The Ideal GateThe Ideal Gate

V out

Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2 g = ∞

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V in


22

An OldAn Old--time Invertertime Inverter

NM L4.0

5.0

NM H

Vout(V)V M

1 0

2.0

3.0

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V in (V)0.0

1.0

1.0 2.0 3.0 4.0 5.0


Delay DefinitionsDelay DefinitionsVin

Vout

tpHL tpLH

t

90%

50%

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tf trt10%

50%


23

Ring OscillatorRing Oscillator

v0 v1 v5

v1 v2v0 v3 v4 v5

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T = 2 ´ tp ´ N


A FirstA First--Order RC NetworkOrder RC Network

Rvout

vin C

R

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tp = ln (2) τ = 0.69 RC

Important model – matches delay of inverter


24

Power DissipationPower Dissipation

Instantaneous power:Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: Ppeak = Vsupplyipeak

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Average power:

( )∫ ∫+ +

==Tt

tTt

t supplysupply

ave dttiT

Vdttp

TP )(1


Energy and EnergyEnergy and Energy--DelayDelay

Power-Delay Product (PDP) =owe De ay oduct ( D )

E = Energy per operation = Pav × tp

Energy-Delay Product (EDP) =

li i f E

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quality metric of gate = E × tp


25

A FirstA First--Order RC NetworkOrder RC Network

voutR

E0 1 P t( )dtT∫ Vdd i l t( )dt

T∫ Vdd CLdV

Vdd

∫ CL Vdd• 2= = = =

vin CL

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E0 1→ P t( )dt0∫ Vdd isupply t( )dt

0∫ Vdd CLdVout

0∫ CL Vdd•

Ecap Pcap t( )dt0

T∫ Vouticap t( )dt

0

T∫ CLVoutdVout

0

Vdd∫

12---C

LVdd• 2= = = =


SummarySummaryDigital integrated circuits have come a long way and still have quite some potential left for th i d dthe coming decadesSome interesting challenges ahead

Getting a clear perspective on the challenges and potential solutions is the purpose of this book

Understanding the design metrics that govern digital design is crucial

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digital design is crucialCost, reliability, speed, power and energy dissipation


l1 intro r1.ppt [호환 모드]

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