l08 ec360(19)-dsp processors

7/30/2019 L08 EC360(19)-DSP Processors

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Digital Signal Processor -

Instruction Set

Sonali chouhan


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DSP Algorithms Shape DSPs

How Signal Processing is DifferentFrom Other Tasks Very computationally demanding

Requires attention to numeric fidelity High memory bandwidth requirements Streaming dataand lots of it Predictable data access patterns

Execution-time locality Math-centric Real-time constraints Standards: algorithms, interfaces


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General-Purpose Features

Several DSPs now include featurestraditionally associated with general-purpose processors User modes

Memory management units Compiler-oriented features such as

specialized addressing modes

Enable more sophisticated OSs

Ease implementation of non-signal-processing tasks

Often make processors better compiler

targets


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DSP processors

SHARC, BlackFin, TMS320C55x,TMS320C67x, TMS320C64x

16-32 bit word size

Single program Lightweight, often real-time OS Super Harvard Architecture Support Improved throughput Audio, Image and Video processing,

Coding and Decoding, Cellular BaseStation, Adaptive Filtering, Real Timeoperations


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Super Harvard Architecture

Super Harvard architecture improves

upon the Harvard architecture by addingan instruction cache and a dedicated I/Ocontroller

In Harvard architecture data memory bus

is busier than the program memory bus


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Super Harvard Architecture(Contd.)

Relocate part of the "data" toprogram memory (secondary data)

Improves performance in case ofdata extensive operations (e.g., loop)

Adds program cache in CPU

Stores ~32 most recent instructions

I/O port allows Direct memory access(DMA)

No CPU cycles wasted


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Proprietary v/s Shared Most DSP architectures are not shared, not

licensable One silicon vendor per architecture

In contrast, many GPPs are shared andlicensable

ARM, MIPS, PowerPC, SH-x, x86 There are some shared or licensable DSP

architectures CEVA, StarCore, ZSP

Shared architectures can encourage stability,price competition, and wide third-party support

But proprietary architectures May achieve faster technological advances May have market momentum, integration

advantages


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SHARC instruction set

SHARC programming model.

SHARC assembly language.

SHARC memory organization. SHARC data operations.

SHARC flow of control.


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SHARC programming model

Register files:

R0-R15 (aliased as F0-F15 for floatingpoint)

Status registers.

Loop registers.

Data address generator registers. Interrupt registers.


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SHARC assembly language

Algebraic notation terminated bysemicolon:

R1=DM(M0,I0), R2=PM(M8,I8); ! comment

label: R3=R1+R2;

data memory access program memory access


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SHARC memory space

IOP registers0x0

256

forbidden

normal word

addressing

short word

addressing

0x20000

0x40000

interrupt vectors


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SHARC data types

32-bit IEEE single-precision floating-point.

40-bit IEEE extended-precisionfloating-point.

32-bit integers.

Memory organized internally as 32-bit words.


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SHARC microarchitecture

Modified Harvard architecture.

Program memory can be used to storesome data.

Register file connects to:

multiplier

shifter;

ALU.


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SHARC Computation Unit


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SHARC mode registers

Most important:

ASTAT: arithmetic status.

STKY: sticky.

MODE 1: mode 1.


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Rounding and saturation

Floating-point can be:

rounded toward zero;

rounded toward nearest.

ALU supports saturation arithmetic(controlled by ALUSAT bit in MODE1reg).

Overflow results in max value, notrollover.


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Multiplier

Fixed-point operations canaccumulate into local MR registers orbe written to register file.

Fixed-point result is 80 bits.

Floating-point results always go toregister file.

Status bits: negative, under/overflow,invalid, fixed-point underflow,floating-point underflow, floating-

point invalid.


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ALU/shifter status flags

ALU:

zero, overflow, negative, fixed-pointcarry, inputsign, floating-point invalid,

last op was floating-point, compareaccumulation registers, floating-pointunder/oveflow, fixed-point overflow,floating-point invalid

Shifter:

zero, overflow, sign


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Flag operations

All ALU operations set AZ (zero), AN(negative), AV (overflow), AC (fixed-point carry), AI (floating-point invalid)

bits in ASTAT.

STKY is sticky version of some ASTATbits.


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Reference

ADSP-21161 SHARC Processor H/WReference (Rev 4.0)

l08 ec360(19)-dsp processors

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