kl17 sub-family reference manual - nxp …cache.freescale.com/files/32bit/doc/ref_manual...section...

KL17 Sub-Family Reference ManualSupports: MKL17Z128VFM4, MKL17Z256VFM4, MKL17Z128VFT4,

MKL17Z256VFT4, MKL17Z128VMP4, MKL17Z256VMP4,MKL17Z128VLH4, MKL17Z256VLH4, MKL17Z256CAL4R

Document Number: KL17P64M48SF6RMRev. 5.1, 07/2016

KL17 Sub-Family Reference Manual, Rev. 5.1, 07/2016

2 NXP Semiconductors

Contents

Section number Title Page

Chapter 1About This Document

1.1 Overview.......................................................................................................................................................................37

1.1.1 Purpose...........................................................................................................................................................37

1.1.2 Audience........................................................................................................................................................ 37

1.2 Conventions.................................................................................................................................................................. 37

1.2.1 Numbering systems........................................................................................................................................37

1.2.2 Typographic notation..................................................................................................................................... 38

1.2.3 Special terms.................................................................................................................................................. 38

Chapter 2Introduction

2.1 Overview.......................................................................................................................................................................39

2.1.1 Sub-family introduction................................................................................................................................. 39

2.2 Module functional categories........................................................................................................................................40

2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 40

2.2.2 System modules............................................................................................................................................. 41

2.2.3 Memories and memory interfaces..................................................................................................................42

2.2.4 Clocks.............................................................................................................................................................42

2.2.5 Security and integrity modules...................................................................................................................... 43

2.2.6 Analog modules............................................................................................................................................. 43

2.2.7 Timer modules............................................................................................................................................... 43

2.2.8 Communication interfaces............................................................................................................................. 44

2.2.9 Human-machine interfaces............................................................................................................................ 44

2.3 Module to module interconnects...................................................................................................................................45

2.3.1 Interconnection overview...............................................................................................................................45

2.3.2 Analog reference options............................................................................................................................... 47

Chapter 3Core Overview


NXP Semiconductors 3


3.1 ARM Cortex-M0+ core introduction............................................................................................................................49

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 49

3.1.2 System tick timer........................................................................................................................................... 49

3.1.3 Debug facilities.............................................................................................................................................. 49

3.1.4 Core privilege levels...................................................................................................................................... 50

3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................50

3.2.1 Interrupt priority levels.................................................................................................................................. 50

3.2.2 Non-maskable interrupt..................................................................................................................................50

3.2.3 Interrupt channel assignments........................................................................................................................50

3.3 AWIC introduction....................................................................................................................................................... 53

3.3.1 Wake-up sources............................................................................................................................................ 53

Chapter 4Memory Map

4.1 Introduction...................................................................................................................................................................55

4.2 Flash memory............................................................................................................................................................... 55

4.2.1 Flash memory map.........................................................................................................................................55

4.2.2 Flash security................................................................................................................................................. 56

4.2.3 Flash modes....................................................................................................................................................56

4.2.4 Erase all flash contents...................................................................................................................................56

4.2.5 FTFA_FOPT register..................................................................................................................................... 57

4.3 SRAM........................................................................................................................................................................... 57

4.3.1 SRAM sizes....................................................................................................................................................57

4.3.2 SRAM ranges.................................................................................................................................................57

4.3.3 SRAM retention in low power modes............................................................................................................58

4.4 System Register file...................................................................................................................................................... 59

4.5 System memory map.....................................................................................................................................................59

4.6 Bit Manipulation Engine...............................................................................................................................................60

4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................60

4.7.1 Read-after-write sequence and required serialization of memory operations................................................60




4.7.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................61

Chapter 5Clock Distribution

5.1 Introduction...................................................................................................................................................................65

5.2 Programming model......................................................................................................................................................65

5.3 High-level device clocking diagram............................................................................................................................. 65

5.4 Clock definitions...........................................................................................................................................................66

5.4.1 Device clock summary...................................................................................................................................67

5.5 Internal clocking requirements..................................................................................................................................... 69

5.5.1 Clock divider values after reset......................................................................................................................70

5.5.2 VLPR mode clocking.....................................................................................................................................70

5.6 Clock gating..................................................................................................................................................................70

5.7 Module clocks...............................................................................................................................................................71

5.7.1 PMC 1-kHz LPO clock.................................................................................................................................. 72

5.7.2 COP clocking................................................................................................................................................. 72

5.7.3 RTC clocking................................................................................................................................................. 73

5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................ 73

5.7.5 LPTMR clocking............................................................................................................................................74

5.7.6 TPM clocking.................................................................................................................................................75

5.7.7 LPUART clocking......................................................................................................................................... 75

5.7.8 FlexIO clocking..............................................................................................................................................76

5.7.9 I2S/SAI clocking............................................................................................................................................77

Chapter 6Reset and Boot

6.1 Introduction...................................................................................................................................................................79

6.2 Reset..............................................................................................................................................................................79

6.2.1 Power-on reset (POR).................................................................................................................................... 80

6.2.2 System reset sources...................................................................................................................................... 80

6.2.3 MCU resets.................................................................................................................................................... 83




6.2.4 RESET pin .................................................................................................................................................... 84

6.3 Boot...............................................................................................................................................................................84

6.3.1 Boot sources...................................................................................................................................................85

6.3.2 FOPT boot options......................................................................................................................................... 85

6.3.3 Boot sequence................................................................................................................................................ 87

Chapter 7Power Management

7.1 Introduction...................................................................................................................................................................89

7.2 Clocking modes............................................................................................................................................................ 89

7.2.1 Partial Stop.....................................................................................................................................................89

7.2.2 DMA Wakeup................................................................................................................................................ 90

7.2.3 Compute Operation........................................................................................................................................ 91

7.2.4 Peripheral Doze..............................................................................................................................................92

7.2.5 Clock gating................................................................................................................................................... 93

7.3 Power modes.................................................................................................................................................................93

7.4 Entering and exiting power modes............................................................................................................................... 95

7.5 Module operation in low-power modes........................................................................................................................ 96

Chapter 8Security

8.1 Introduction...................................................................................................................................................................101

8.1.1 Flash security................................................................................................................................................. 101

8.1.2 Security interactions with other modules.......................................................................................................101

Chapter 9Debug

9.1 Introduction...................................................................................................................................................................103

9.2 Debug port pin descriptions..........................................................................................................................................103

9.3 SWD status and control registers..................................................................................................................................104

9.3.1 MDM-AP Control Register............................................................................................................................105

9.3.2 MDM-AP Status Register.............................................................................................................................. 106

9.4 Debug resets..................................................................................................................................................................108




9.5 Micro Trace Buffer (MTB)...........................................................................................................................................108

9.6 Debug in low-power modes.......................................................................................................................................... 109

9.7 Debug and security....................................................................................................................................................... 110

Chapter 10Pinouts and Packaging

10.1 Introduction...................................................................................................................................................................111

10.2 Signal multiplexing integration.................................................................................................................................... 111

10.2.1 Clock gating................................................................................................................................................... 112

10.2.2 Signal multiplexing constraints......................................................................................................................112

10.3 KL17 signal multiplexing and pin assignments............................................................................................................112

10.4 KL17 Family Pinouts....................................................................................................................................................115

10.5 Module Signal Description Tables................................................................................................................................120

10.5.1 Core modules................................................................................................................................................. 120

10.5.2 System modules............................................................................................................................................. 121

10.5.3 Clock modules................................................................................................................................................121

10.5.4 Analog............................................................................................................................................................122

10.5.5 Timer Modules...............................................................................................................................................122

10.5.6 Communication interfaces............................................................................................................................. 124

10.5.7 Human-machine interfaces (HMI)................................................................................................................. 126

Chapter 11Port Control and Interrupts (PORT)

11.1 Chip-specific PORT information..................................................................................................................................127

11.2 Port control and interrupt summary.............................................................................................................................. 128

11.3 Introduction...................................................................................................................................................................129

11.4 Overview.......................................................................................................................................................................129

11.4.1 Features.......................................................................................................................................................... 129

11.4.2 Modes of operation........................................................................................................................................ 130

11.5 External signal description............................................................................................................................................131

11.6 Detailed signal description............................................................................................................................................131




11.7 Memory map and register definition.............................................................................................................................131

11.7.1 Pin Control Register n (PORTx_PCRn).........................................................................................................137

11.7.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................... 140

11.7.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................140

11.7.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 141

11.8 Functional description...................................................................................................................................................141

11.8.1 Pin control...................................................................................................................................................... 141

11.8.2 Global pin control.......................................................................................................................................... 142

11.8.3 External interrupts..........................................................................................................................................142

Chapter 12System Integration Module (SIM)

12.1 Chip-specific SIM information.....................................................................................................................................145

12.1.1 COP clocks.....................................................................................................................................................145

12.2 Introduction...................................................................................................................................................................145

12.2.1 Features.......................................................................................................................................................... 145


12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 147





12.3.6 System Device Identification Register (SIM_SDID).....................................................................................154

12.3.7 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................156




12.3.11 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................162

12.3.12 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 164

12.3.13 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 165




12.3.14 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................166

12.3.15 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 167

12.3.16 Unique Identification Register Low (SIM_UIDL)........................................................................................ 167

12.3.17 COP Control Register (SIM_COPC)............................................................................................................. 168

12.3.18 Service COP (SIM_SRVCOP).......................................................................................................................169


12.4.1 COP watchdog operation............................................................................................................................... 170

Chapter 13Kinetis ROM Bootloader

13.1 Chip-Specific Information............................................................................................................................................ 173

13.2 Introduction...................................................................................................................................................................173

13.3 Functional Description..................................................................................................................................................175

13.3.1 Memory Maps................................................................................................................................................ 175

13.3.2 The Kinetis Bootloader Configuration Area (BCA)...................................................................................... 176

13.3.3 Start-up Process..............................................................................................................................................177

13.3.4 Clock Configuration.......................................................................................................................................179

13.3.5 Bootloader Entry Point...................................................................................................................................180

13.3.6 Bootloader Protocol....................................................................................................................................... 181

13.3.7 Bootloader Packet Types............................................................................................................................... 186

13.3.8 Bootloader Command API.............................................................................................................................193

13.3.9 Bootloader Exit state......................................................................................................................................207

13.4 Peripherals Supported................................................................................................................................................... 208

13.4.1 I2C Peripheral................................................................................................................................................ 208

13.4.2 SPI Peripheral................................................................................................................................................ 210

13.5 Get/SetProperty Command Properties..........................................................................................................................212

13.5.1 Property Definitions.......................................................................................................................................213

13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................215

13.7 Bootloader errata...........................................................................................................................................................216

Chapter 14




System Mode Controller (SMC)

14.1 Chip-specific SMC information....................................................................................................................................219

14.2 Introduction...................................................................................................................................................................219

14.3 Modes of operation....................................................................................................................................................... 219

14.4 Memory map and register descriptions.........................................................................................................................221

14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................222

14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................223

14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................224

14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 226


14.5.1 Power mode transitions..................................................................................................................................226

14.5.2 Power mode entry/exit sequencing................................................................................................................ 229

14.5.3 Run modes......................................................................................................................................................230

14.5.4 Wait modes.................................................................................................................................................... 232

14.5.5 Stop modes.....................................................................................................................................................233

14.5.6 Debug in low power modes........................................................................................................................... 236

Chapter 15Power Management Controller (PMC)

15.1 Introduction...................................................................................................................................................................237

15.2 Features.........................................................................................................................................................................237

15.3 Low-voltage detect (LVD) system................................................................................................................................237

15.3.1 LVD reset operation.......................................................................................................................................238

15.3.2 LVD interrupt operation.................................................................................................................................238

15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 238

15.4 I/O retention..................................................................................................................................................................239

15.5 Memory map and register descriptions.........................................................................................................................239

15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 240

15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 241

15.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................ 242




Chapter 16Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................245

16.1.1 Features.......................................................................................................................................................... 245

16.2 Memory map/register descriptions............................................................................................................................... 245

16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................246

16.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 246

16.2.3 Platform Control Register (MCM_PLACR)..................................................................................................247

16.2.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 250

Chapter 17Crossbar Switch Lite (AXBS-Lite)

17.1 Chip-specific AXBS-Lite information..........................................................................................................................253

17.1.1 Crossbar-light switch master assignments..................................................................................................... 253

17.1.2 Crossbar switch slave assignments................................................................................................................ 253

17.2 Introduction...................................................................................................................................................................253

17.2.1 Features.......................................................................................................................................................... 254

17.3 Memory Map / Register Definition...............................................................................................................................254


17.4.1 General operation...........................................................................................................................................254

17.4.2 Arbitration......................................................................................................................................................255

17.5 Initialization/application information........................................................................................................................... 257

Chapter 18Low-Leakage Wakeup Unit (LLWU)

18.1 LLWU interrupt............................................................................................................................................................ 259

18.1.1 Wake-up Sources........................................................................................................................................... 259

18.2 Introduction...................................................................................................................................................................260

18.2.1 Features.......................................................................................................................................................... 260


18.2.3 Block diagram................................................................................................................................................ 262

18.3 LLWU signal descriptions............................................................................................................................................ 263




18.4 Memory map/register definition................................................................................................................................... 263

18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................264




18.4.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 268

18.4.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................270



18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 275

18.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 276


18.5.1 LLS mode.......................................................................................................................................................278

18.5.2 VLLS modes.................................................................................................................................................. 278

18.5.3 Initialization................................................................................................................................................... 278

Chapter 19Peripheral Bridge (AIPS-Lite)

19.1 Chip-specific AIPS-Lite information............................................................................................................................279

19.1.1 Number of peripheral bridges........................................................................................................................ 279

19.1.2 Memory maps................................................................................................................................................ 279

19.2 Introduction...................................................................................................................................................................279

19.2.1 Features.......................................................................................................................................................... 279



19.3.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 280

19.3.2 Peripheral Access Control Register (AIPS_PACRn).....................................................................................282

19.3.3 Peripheral Access Control Register (AIPS_n)............................................................................................... 0


19.4.1 Access support............................................................................................................................................... 287




Chapter 20Direct Memory Access Multiplexer (DMAMUX)

20.1 Chip-specific DMAMUX information......................................................................................................................... 289

20.1.1 DMA MUX Request Sources........................................................................................................................ 289

20.1.2 DMA transfers via PIT trigger....................................................................................................................... 291

20.2 Introduction...................................................................................................................................................................291

20.2.1 Overview........................................................................................................................................................291

20.2.2 Features.......................................................................................................................................................... 292


20.3 External signal description............................................................................................................................................293


20.4.1 Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 293


20.5.1 DMA channels with periodic triggering capability........................................................................................295

20.5.2 DMA channels with no triggering capability.................................................................................................297

20.5.3 Always-enabled DMA sources...................................................................................................................... 297

20.6 Initialization/application information........................................................................................................................... 299

20.6.1 Reset...............................................................................................................................................................299

20.6.2 Enabling and configuring sources..................................................................................................................299

Chapter 21DMA Controller Module

21.1 Introduction...................................................................................................................................................................303

21.1.1 Overview........................................................................................................................................................303

21.1.2 Features.......................................................................................................................................................... 304

21.2 DMA Transfer Overview..............................................................................................................................................305

21.3 Memory Map/Register Definition.................................................................................................................................306

21.3.1 Source Address Register (DMA_SARn)....................................................................................................... 307

21.3.2 Destination Address Register (DMA_DARn)............................................................................................... 308

21.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................309




21.3.4 DMA Control Register (DMA_DCRn)..........................................................................................................311


21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................ 315

21.4.2 Channel initialization and startup.................................................................................................................. 316

21.4.3 Dual-Address Data Transfer Mode................................................................................................................ 317

21.4.4 Advanced Data Transfer Controls: Auto-Alignment..................................................................................... 318

21.4.5 Termination....................................................................................................................................................319

Chapter 22Reset Control Module (RCM)

22.1 Introduction...................................................................................................................................................................321

22.2 Reset memory map and register descriptions............................................................................................................... 321

22.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 322

22.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 323

22.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 324

22.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 325

22.2.5 Force Mode Register (RCM_FM)..................................................................................................................327

22.2.6 Mode Register (RCM_MR)........................................................................................................................... 327

22.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................328

22.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................329

Chapter 23Analog-to-Digital Converter (ADC)

23.1 Chip-specific ADC information....................................................................................................................................331

23.1.1 ADC instantiation information.......................................................................................................................331

23.1.2 DMA Support on ADC.................................................................................................................................. 331

23.1.3 ADC0 connections/channel assignment.........................................................................................................332

23.1.4 ADC analog supply and reference connections............................................................................................. 333

23.1.5 Alternate clock............................................................................................................................................... 333

23.2 Introduction...................................................................................................................................................................334

23.2.1 Features.......................................................................................................................................................... 334




23.2.2 Block diagram................................................................................................................................................ 335

23.3 ADC signal descriptions............................................................................................................................................... 336

23.3.1 Analog Power (VDDA)................................................................................................................................. 336

23.3.2 Analog Ground (VSSA).................................................................................................................................336

23.3.3 Voltage Reference Select............................................................................................................................... 336

23.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 337

23.3.5 Differential Analog Channel Inputs (DADx).................................................................................................337

23.4 Memory map and register definitions........................................................................................................................... 337

23.4.1 ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................339

23.4.2 ADC Configuration Register 1 (ADCx_CFG1).............................................................................................342

23.4.3 ADC Configuration Register 2 (ADCx_CFG2).............................................................................................343

23.4.4 ADC Data Result Register (ADCx_Rn).........................................................................................................344

23.4.5 Compare Value Registers (ADCx_CVn)....................................................................................................... 346

23.4.6 Status and Control Register 2 (ADCx_SC2)..................................................................................................347

23.4.7 Status and Control Register 3 (ADCx_SC3)..................................................................................................349

23.4.8 ADC Offset Correction Register (ADCx_OFS).............................................................................................350

23.4.9 ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................351

23.4.10 ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 351

23.4.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 352

23.4.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................353

23.4.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 353





23.4.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................356

23.4.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 356

23.4.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 357









23.5.1 Clock select and divide control......................................................................................................................360

23.5.2 Voltage reference selection............................................................................................................................361

23.5.3 Hardware trigger and channel selects............................................................................................................ 361

23.5.4 Conversion control.........................................................................................................................................362

23.5.5 Automatic compare function..........................................................................................................................370

23.5.6 Calibration function....................................................................................................................................... 371

23.5.7 User-defined offset function.......................................................................................................................... 373

23.5.8 Temperature sensor........................................................................................................................................ 374

23.5.9 MCU wait mode operation.............................................................................................................................375

23.5.10 MCU Normal Stop mode operation............................................................................................................... 375

23.5.11 MCU Low-Power Stop mode operation........................................................................................................ 376

23.6 Initialization information.............................................................................................................................................. 377

23.6.1 ADC module initialization example.............................................................................................................. 377

23.7 Application information................................................................................................................................................379

23.7.1 External pins and routing............................................................................................................................... 379

23.7.2 Sources of error..............................................................................................................................................381

Chapter 24Comparator (CMP)

24.1 Chip-specific CMP information....................................................................................................................................387

24.1.1 CMP instantiation information.......................................................................................................................387

24.1.2 CMP input connections..................................................................................................................................387

24.1.3 CMP external references................................................................................................................................388

24.1.4 CMP trigger mode..........................................................................................................................................388

24.2 Introduction...................................................................................................................................................................389

24.2.1 CMP features..................................................................................................................................................389




24.2.2 6-bit DAC key features.................................................................................................................................. 390

24.2.3 ANMUX key features.................................................................................................................................... 390

24.2.4 CMP, DAC and ANMUX diagram................................................................................................................390

24.2.5 CMP block diagram....................................................................................................................................... 391

24.3 Memory map/register definitions..................................................................................................................................393

24.3.1 CMP Control Register 0 (CMPx_CR0)......................................................................................................... 393

24.3.2 CMP Control Register 1 (CMPx_CR1)......................................................................................................... 394

24.3.3 CMP Filter Period Register (CMPx_FPR).....................................................................................................395

24.3.4 CMP Status and Control Register (CMPx_SCR)...........................................................................................396

24.3.5 DAC Control Register (CMPx_DACCR)...................................................................................................... 397

24.3.6 MUX Control Register (CMPx_MUXCR).................................................................................................... 397


24.4.1 CMP functional modes...................................................................................................................................399

24.4.2 Power modes.................................................................................................................................................. 402

24.4.3 Startup and operation..................................................................................................................................... 403

24.4.4 Low-pass filter............................................................................................................................................... 404

24.5 CMP interrupts..............................................................................................................................................................406

24.6 DMA support................................................................................................................................................................ 406

24.7 CMP Asynchronous DMA support...............................................................................................................................406

24.8 Digital-to-analog converter...........................................................................................................................................407

24.9 DAC functional description.......................................................................................................................................... 407

24.9.1 Voltage reference source select......................................................................................................................407

24.10 DAC resets....................................................................................................................................................................408

24.11 DAC clocks...................................................................................................................................................................408

24.12 DAC interrupts..............................................................................................................................................................408

24.13 CMP Trigger Mode.......................................................................................................................................................408

Chapter 2512-bit Digital-to-Analog Converter (DAC)

25.1 Introduction...................................................................................................................................................................409




25.2 Features.........................................................................................................................................................................409

25.3 Block diagram...............................................................................................................................................................409


25.4.1 DAC Data Low Register (DACx_DATnL)................................................................................................... 411

25.4.2 DAC Data High Register (DACx_DATnH).................................................................................................. 411

25.4.3 DAC Status Register (DACx_SR)................................................................................................................. 412

25.4.4 DAC Control Register (DACx_C0)............................................................................................................... 413

25.4.5 DAC Control Register 1 (DACx_C1)............................................................................................................ 414

25.4.6 DAC Control Register 2 (DACx_C2)............................................................................................................ 414


25.5.1 DAC data buffer operation.............................................................................................................................415

25.5.2 DMA operation.............................................................................................................................................. 417

25.5.3 Resets............................................................................................................................................................. 417

25.5.4 Low-Power mode operation...........................................................................................................................417

Chapter 26Voltage Reference (VREFV1)

26.1 Introduction...................................................................................................................................................................419

26.1.1 Overview........................................................................................................................................................420

26.1.2 Features.......................................................................................................................................................... 420

26.1.3 Modes of Operation....................................................................................................................................... 420

26.1.4 VREF Signal Descriptions............................................................................................................................. 421

26.2 Memory Map and Register Definition..........................................................................................................................421

26.2.1 VREF Trim Register (VREF_TRM)..............................................................................................................422

26.2.2 VREF Status and Control Register (VREF_SC)............................................................................................423


26.3.1 Voltage Reference Disabled, SC[VREFEN] = 0........................................................................................... 424

26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1............................................................................................ 424

26.4 Internal voltage regulator..............................................................................................................................................426

26.5 Initialization/Application Information..........................................................................................................................426




Chapter 27Multipurpose Clock Generator Lite (MCG_Lite)

27.1 Introduction ..................................................................................................................................................................429

27.1.1 Features ......................................................................................................................................................... 429

27.1.2 Block diagram ............................................................................................................................................... 429


27.2.1 MCG Control Register 1 (MCG_C1).............................................................................................................431

27.2.2 MCG Control Register 2 (MCG_C2).............................................................................................................432

27.2.3 MCG Status Register (MCG_S).................................................................................................................... 433

27.2.4 MCG Status and Control Register (MCG_SC)..............................................................................................433

27.2.5 MCG Miscellaneous Control Register (MCG_MC)......................................................................................434


27.3.1 Clock mode switching ...................................................................................................................................435

27.3.2 LIRC divider 1 .............................................................................................................................................. 436

27.3.3 LIRC divider 2 .............................................................................................................................................. 436

27.3.4 Enable LIRC in Stop mode ........................................................................................................................... 436

27.3.5 MCG-Lite in Low-power mode .................................................................................................................... 436

Chapter 28Oscillator (OSC)

28.1 Chip-specific OSC information.................................................................................................................................... 439

28.1.1 OSC modes of operation with MCG_Lite and RTC......................................................................................439

28.2 Introduction...................................................................................................................................................................439

28.3 Features and Modes...................................................................................................................................................... 439

28.4 Block Diagram..............................................................................................................................................................440

28.5 OSC Signal Descriptions.............................................................................................................................................. 441

28.6 External Crystal / Resonator Connections.................................................................................................................... 441

28.7 External Clock Connections......................................................................................................................................... 443

28.8 Memory Map/Register Definitions...............................................................................................................................443

28.8.1 OSC Memory Map/Register Definition.........................................................................................................444





28.9.1 OSC module states......................................................................................................................................... 445

28.9.2 OSC module modes....................................................................................................................................... 447

28.9.3 Counter...........................................................................................................................................................449

28.9.4 Reference clock pin requirements..................................................................................................................449

28.10 Reset..............................................................................................................................................................................449

28.11 Low power modes operation.........................................................................................................................................450

28.12 Interrupts.......................................................................................................................................................................450

Chapter 29Timer/PWM Module (TPM)

29.1 Chip-specific TPM information....................................................................................................................................451

29.1.1 TPM instantiation information.......................................................................................................................451

29.1.2 Clock options................................................................................................................................................. 452

29.1.3 Trigger options...............................................................................................................................................452

29.1.4 Global timebase..............................................................................................................................................453

29.1.5 TPM interrupts............................................................................................................................................... 453

29.2 Introduction...................................................................................................................................................................454

29.2.1 TPM Philosophy............................................................................................................................................ 454

29.2.2 Features.......................................................................................................................................................... 454


29.2.4 Block diagram................................................................................................................................................ 455

29.3 TPM Signal Descriptions..............................................................................................................................................456

29.3.1 TPM_EXTCLK TPM External Clock...................................................................................................... 456

29.3.2 TPM_CHn TPM Channel (n) I/O Pin....................................................................................................... 457

29.4 Memory Map and Register Definition..........................................................................................................................457

29.4.1 Status and Control (TPMx_SC)..................................................................................................................... 459

29.4.2 Counter (TPMx_CNT)................................................................................................................................... 460

29.4.3 Modulo (TPMx_MOD).................................................................................................................................. 461

29.4.4 Channel (n) Status and Control (TPMx_CnSC).............................................................................................462




29.4.5 Channel (n) Value (TPMx_CnV)...................................................................................................................464

29.4.6 Capture and Compare Status (TPMx_STATUS)........................................................................................... 464

29.4.7 Channel Polarity (TPMx_POL)..................................................................................................................... 466

29.4.8 Configuration (TPMx_CONF).......................................................................................................................467


29.5.1 Clock domains................................................................................................................................................470

29.5.2 Prescaler......................................................................................................................................................... 471

29.5.3 Counter...........................................................................................................................................................471

29.5.4 Input Capture Mode....................................................................................................................................... 474

29.5.5 Output Compare Mode...................................................................................................................................475

29.5.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................476

29.5.7 Center-Aligned PWM (CPWM) Mode.......................................................................................................... 478

29.5.8 Registers Updated from Write Buffers.......................................................................................................... 480

29.5.9 DMA.............................................................................................................................................................. 480

29.5.10 Output triggers............................................................................................................................................... 481

29.5.11 Reset Overview.............................................................................................................................................. 481

29.5.12 TPM Interrupts...............................................................................................................................................482

Chapter 30Periodic Interrupt Timer (PIT)

30.1 Chip-specific PIT information...................................................................................................................................... 483

30.1.1 PIT/DMA periodic trigger assignments ........................................................................................................483

30.1.2 PIT/ADC triggers...........................................................................................................................................483

30.1.3 PIT/TPM triggers........................................................................................................................................... 483

30.1.4 PIT/DAC triggers...........................................................................................................................................483

30.2 Introduction...................................................................................................................................................................484

30.2.1 Block diagram................................................................................................................................................ 484

30.2.2 Features.......................................................................................................................................................... 484

30.3 Signal description..........................................................................................................................................................485

30.4 Memory map/register description................................................................................................................................. 485




30.4.1 PIT Module Control Register (PIT_MCR).................................................................................................... 486

30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)................................................................................. 487

30.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)................................................................................. 487

30.4.4 Timer Load Value Register (PIT_LDVALn).................................................................................................488

30.4.5 Current Timer Value Register (PIT_CVALn)............................................................................................... 488

30.4.6 Timer Control Register (PIT_TCTRLn)........................................................................................................ 489

30.4.7 Timer Flag Register (PIT_TFLGn)................................................................................................................490



30.5.2 Interrupts........................................................................................................................................................ 492

30.5.3 Chained timers............................................................................................................................................... 492

30.6 Initialization and application information.....................................................................................................................492

30.7 Example configuration for chained timers....................................................................................................................493

30.8 Example configuration for the lifetime timer............................................................................................................... 494

Chapter 31Low-Power Timer (LPTMR)

31.1 Chip-specific LPTMR information...............................................................................................................................497

31.1.1 LPTMR instantiation information..................................................................................................................497

31.1.2 LPTMR pulse counter input options..............................................................................................................497

31.1.3 LPTMR prescaler/glitch

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