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Towards End-to-end TEE Verification with Keystone Shweta Shinde UC Berkeley

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Page 1: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Towards End-to-end TEE Verification with Keystone

Shweta ShindeUC Berkeley

Page 2: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

TEEs reduce the Trusted Computing Base

Operating Systems

Hypervisor

CVEs in Linux [CVE-DB]

CVEs in Xen [CVE-DB]

150 KLOC

10 MLOCOS / Hypervisor

RAM

WebServer

Enclave

Ring 0 - 2

Ring 3

TrustedUntrusted

Enclave Memory

Other Apps

TrustworthyHardware

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Page 3: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

We strive for lower TCB for TEEsMakes them amenable to verification

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Page 4: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

What is the estimated Keystone TCB?

U-mode

S-mode

M-mode

User process

OS

Hypervisor

Root of Trust

Security Monitor

Enclave

Priv

ilege

High

er

Trusted

UntrustedLo

wer

Keystone Runtime

Around 10 KLoC4

Page 5: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Can we do an end-to-end verification of TEEs?

• Verify-then-trust model• What is the TCB of this stack?• What are the specifications of each

layer?• Under which threat model do the

properties hold true? • Can the upper layer verify & trust the

properties guaranteed by lower layers?RISC-V chip components

PMP spec and usage

Secure Boot

Attestation

SM, RT, SDK libraries

Untrusted and enclave APIs

Eapp Logic

SOC design & manufacturing

Some Open Challenges

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Page 6: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Ongoing Verification Efforts for TEEs

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Page 7: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Keystone Design Makes Verification Easier

• The modular design allows to reduce TCB per use-case • Each component has well-defined APIs and properties by design

• Existing components can be independently verified• Benefit from existing verification efforts in the TEE space• Easy to verify new components before integration

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Page 8: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Keystone Design Makes Verification Easier

Iago-Safe Filesytem APIPMP Implementation & Use

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• Three on-going efforts which demonstrate this:• Extending Trusted Abstract Platform (TAP) to Keystone: Formalization of

idealized enclave platforms along with a parameterized adversary• BesFS: Mechanized Proof of a Iago-Safe Filesystem for Enclaves• Friscy: Formal verification PMP implementation and use in the security

monitor

Page 9: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Effort #1 BesFS: Mechanized Proof of a Iago-Safe Filesystem for Enclaves• Iago Attacks: “Manipulate system call return values for arbitrary

computation at the malicious kernel’s behest” [ASPLOS’13]

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Original Application

Benign OS

EnclaveApplication

Untrusted OS

Transformation

Untrusted APISyscallAPI

Haven / Scone /Asylo / Panoply/Intel SGX SDK /

Keystone

Ad-hoc ChecksBest-effort

Page 10: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Iago Attacks via the Filesystem API• (A1) File Content Manipulation

• Maps same page to multiple files/ parts of a file

• (A2) Paths & File Descriptor Mismatch• Returns wrong file id, opens wrong file

• (A3) Size Mismatch• Under or over write/reads

• (A4) Error Code Manipulation• Returns success without doing the operation

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Why do we need a verified file system interface?Because checks are incomplete

Page 11: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

BesFS State Properties

• All the file and directory paths are unique, there are no circular paths in the file system• All open file IDs have to be registered in O • All open file IDs have unique entries• No overlaps between addresses & one-to-one mapping from virtual

address to content• Current cursor position can only take values between 0 and EOF

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Page 12: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

BesFS Transition Properties

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Page 13: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

BesFS Proof

• State Transition Safety. Given a good state S satisfying pre-conditions prei, then if we execute fi to reach state Sʹ, then Sʹ is always a good state and relation between S and Sʹ is valid according to the transition relation τi:

• Sequential Composition Safety. Given a good initial state S0 subject to a sequence of transitions τm1 , . . . , τmn always produces a good final state Sn

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Page 14: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

BesFS Summary of Results

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• TCB: 3676 LOC Coq, 1.5K LOC in C

• Do Proofs Help in Eliminating Bugs?

– Seek Specification Bug • if pos < size

– Write Implementation Bug• Variable scope overlaps

– Intel SGX SDK Bugs • enclave’s stack is corruption for large sizes

– Error Code Bugs • 7 distinct functions where error codes were

incorrect

Page 15: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Effort #2 Extending Trusted Abstract Platform (TAP) to Keystone• Prove secure remote execution for Keystone security monitor• SRE decomposed into separate proofs on integrity, confidentiality, and

measurement• Proofs verified under various parameterizations of the adversary

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Page 16: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Effort #3 FRISCY: Formal Verification of PMP Implementation & Use in the Security Monitor• Goal: Verify the Keystone memory isolation implementation in the SM• Extract the PMP Model from Rocket Chip SOC implementation • Prove PMP properties and use these properties to further check SM

implementation

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RISC-V RTL

FIRRTL for PMP

PMPCheckerModel

SoC Configuration

UCLID5

Page 17: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

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A long way to go until all the layers of the TEE are fully verified

Page 18: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

End-to-end Verified TEE Ecosystem

Let’s work together towards this grand vision!

üA well-defined adversary model, specifications of each layer, properties expected at the layer interfaces

üStandard way of composing and customizing components while retaining verification guarantees

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RISC-V chip components

PMP spec and usage

Secure Boot

Attestation

SM, RT, SDK libraries

Untrusted and enclave APIs

Eapp Logic

SOC design & manufacturing

Page 19: keystone verification v3 · RISC-V chip components PMP spec and usage Secure Boot Attestation SM, RT, SDK libraries Untrusted and enclave APIs EappLogic SOC design & manufacturing

Thank You!

Shweta Shinde [email protected]

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