key electronic products driving notable dft methodologies€¦ · traditional atpg uses fault...

May 2016

Kurian Varghese

DFT Applications Engineer

Key Electronic Products Driving Notable DFT Methodologies

www.mentor.com© Mentor Graphics Corp. Company Confidential

Key Test Technology MilestonesProvided Universal Benefits

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Scan Design, circa 1980

IEEE 1149.1 (JTAG), circa 1990

ATPG Compression, circa 2000

Enabled broad use of structural test

Provided standard access to test capabilities

Kept test costs in line with overall product costs


Need for Targeted Test Strategies

3

Growing design complexities driving need for specialized

test solutions to maximize effectiveness

Two notable segments needing attention:

Automotive ICs Giga-gate Designs


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Automotive ICsTest Challenges and Unique Solutions


A New Automotive Era

5

20th CenturyIncremental Mechanical Improvements

Coming YearsTechnology and electronics explosion


Fastest Growing Market Segment

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0% 2% 4% 6% 8%

IC Market Growth by Application

Source: IC Insights

Automotive

Comm

Ind/Med

All ICs

Computer

Consumer

(2014 – 2019 CAGR)


Automotive IC SuppliersIncreasingly Diverse Field

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Many new players beyond traditional automotive suppliers

13.2%

11.5%

10.0%

9.6%

8.9%

Others46.8%

Source: IC Insights – data for 2015


What’s the Impact to Semiconductors?

8

Devices must meet quality, reliability & safety requirementsDriven by standards like ISO 26262 & AEC 100

Key requirements—Zero DPM—In-field Self-Test—Field return analysis


Tessent Solutions for Automotive

Zero DPM In-Field Self-Test Field Return Analysis

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Field Return Analysis


In-Field Self-TestZero DPM

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Cell-Aware ATPG

Traditional ATPG uses fault models that do not target defects inside each cell

Cell-aware ATPG improves detection of defects internal to standard cells— Electrical defects mapped to cell-level transistor models— Spice simulation maps fault effects to Cell-Aware fault model— ATPG engine targets Cell-Aware faults

D0

D1

D2

S0

S1

Z

ATPG logical view

S

0

S

1

D

0

D

1

D

2

Z

0 0 0 x x 0

0 0 1 x x 1

x 1 x x 0 0

x 1 x x 1 1

1 0 x 0 x 0

1 0 x 1 x 1

SpiceSimulation

CA Model

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Cell-Aware Results

Customer Technology Wafer / Package Test

350 nm

1 Million parts tested

Additional test fallout

114 DPPM

32 nm28 nm

Over 50 Million parts tested

32nm 880 DPPM28nm 1500 DPPM

130 nm4 Million parts tested

Unique CAT test fallout

Over 20 companies350 nm down to less than 28nm

Over 100 Million parts tested withhigh additional test fallout

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Customer Activity

Won Bob Madge Innovation Award at last year’s ITC

Close to a dozen customers already using this technology

Over a dozen published joint papers with customers— International Test Conference

— DATE conference

— European Test Symposium

— Asian Test Symposium

— ISTFA Conference

— Transactions of CAD

Cell-aware Production Test Results from a 350nm Automotive Design

Friedrich Hapke1, Marek Hustava2

1 2

Juergen Schloeffel1, Vilem Bucek2, Wilfried Redemund1, Pieterjan Vyncke2, Anja Fast1, Radek Pospisil2, Janusz Rajski1

M.Beck1, F.Hapke2, R.Arnold1

M.Baby1, S.Straehle1, J.F.Goncalves1, A.Panait1, R.Behr1, G.Maugard1, A.Prashanthi1, J.Schloeffel2, W.Redemund2, A.Glowatz2, A.Fast2, J.Rajski2

Cell-aware Experiences in a High-Quality Automotive Test Suite

2 1

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Very low DPM In-Field Self-Test

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Logic Test Solution Targeting Safety Critical Applications

High quality (0 DPM) test Power-on self-test

Manufacturing In-System

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Hybrid TK/LBIST

Integrated ATPG compression and LBIST (both IP and flow)

Enables maximum optimization of defect coverage vs. test time

Addresses both manufacturing and in-system test needs

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Power-On Self-Test

POST key for addressing ISO 26262 requirements

Programmable POST solution — P2S conversion of instructions/data from memory — Data for the BIST registers provided via the IJTAG network— Complete flexibility on how the BIST controllers are run during

POST session

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Customer Feedback

Over 20 customers already using this solution

“The combination of compressed scan test and logic BIST gives Renesas a high-quality solution for both production test and Power-On Self-Test, which is required by the ISO 26262 standard in the automotive industry,”

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Very low DPM In-Field Self-Test

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“This directly results in more die becoming suitable for PFA”

“The search area is reduced to 11% or less of the original area”

Layout-Aware Diagnosis:Improves Resolution and Accuracy

Logic diagnosis Layout-aware diagnosis

Y.-J. Chang, et.al. (MGC, UMC, AMD), “Experiences with Layout-Aware Diagnosis,” EDFA Magazine, May 2010

M. Sharma, et.al. (MGC, TSMC, AMD), “Layout-aware Diagnosis Leads to Efficient and Effective Physical Failure Analysis,” ISTFA 2011

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Cell-Aware Diagnosis:Transistor Level Diagnosis

Improve resolution to defect locations inside cells— Works for all pattern types

Leverages cell-aware fault model— Internal defects mapped to input

excitation conditions

Data collection and diagnosis flow identical to traditional layout-aware diagnosis

ITC 2012

ATS 2014

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Customer Feedback

Several automotive customers using these solutions

ST, ISTFA 2011

85% reduction in root cause cycle time

Cypress, U2U 2012

From 10% to ~100% FA success rate

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“Tool helped identify exact location of failure on layout and coordinates for debugging PFA candidates. Close to 100% success on PFA.”

Avadh Tibrawal, Cypress Semiconductor

“Using the statistical analysis features of Tessent YieldInsight we are able to identify yield issues in days as well as determining the impact of process modifications.”

Davide Appello, STMicroelectronics


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Giga-Gate DesignsTest Challenges and Unique Solutions


Unique Challenges for Giga-gate Designs

ATPG run timeMultiple weeks to months not uncommon for large designs

Often in critical path to tapeout

Memory footprintVery large memory footprint limits machine availability

Test pattern volumeDirectly impacts test (and product) cost

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Tessent Solutions for Giga-Gate Designs

ATPG run time

ATPG memory footprint

Test pattern volume

Hierarchical ATPG

TestKompress &EDT Test Points

25


Hierarchical ATPG

Divide-and-conquer approach to break down the overall ATPG task into smaller, more manageable pieces

26

Patterns are first generated for each design core in isolation.

Patterns are then automatically retargeted to the chip level and merged to minimize test time


Hierarchical ATPGMain Benefits

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Significant reduction in run times

Significant reduction in compute resources

Reduction in pattern volume

Allows block-level ATPG early in flow

— Takes ATPG out of critical path


Hierarchical ATPGTypical Customer Results

5X+ reduction

in ATPG runtime

>5X reduction

in CPU memoryrequired

Saved 100’s of hours in gate-level

simulation

50% reduction in pattern

count

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Customer Feedback

Over 15 customers already using hierarchical ATPG solution

General business information

TM

Hierarchical DFT

Implementation at Freescale

Israel

Shlomi Sde-Paz

Freescale Israel

J a n 2 0 1 5

“Moving to Mentor’s Tessent hierarchical ATPG flow has allowed us to significantly reduce turnaround time on current designs. Because this solution is highly scalable, we expect to continue using it on our future designs”

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Evelyn Landman, VP Engineering, Mellanox Technologies


TestKompress & EDT Test PointsImproving Test Compression

Unlike “traditional” test points that target test coverage improvements, EDT Test Points target compression

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Impact of EDT Test Points

Average 2-4X improvement in compressionOn top of the average TestKompress base compression of 85X

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Customer Feedback

Over a dozen customers already using EDT Test Points

“We’ve not seen a block that doesn’t benefit in terms of pattern count reduction from EDT Test Points.”

“EDT Test Points results were presented to our CTO and the technology was approved for use on all production devices in our design center”

“With the 4X reduction we’re seeing from EDT Test Points, we don’t see any issues with data volume for the next 5-6 years.”

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Summary

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Increasing design complexities require targeted test solutions for maximum effectiveness— Automotive ICs require very high quality and reliability driven by

ISO 26262 standard— Giga-gate designs pushing limits of ATPG runtime and memory

usage

Tessent provides unique solutions to address these new challenges


THANK YOU!

key electronic products driving notable dft methodologies€¦ · traditional atpg uses fault...

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