katana3752 user’s manual, #10005594-02...10005594-02 katana®3752 user’s manual i regulatory...
TRANSCRIPT
Katana®3752: Three-Processor Blade for cPSB
User’s Manualfrom Emerson Network Power™
Embedded Computing
April 2008
The information in this manual has been checked and is believed to be accurate and reliable. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others.
Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Net-work Power, and the Emerson Network Power logo are trademarks and service marks of Emerson Network Power, Embedded Computing, Inc.© 2008 Emerson Network Power, Embedded Computing, Inc.
Copyright © 2005-2008 Emerson Network Power, Embedded Computing, Inc. All rights reserved.
Revision Level: Principal Changes: Date:10005594-00 Original release November 2005
10005594-01 Updates for RoHS, -03 artwork, P30 flash, ECR01059: added MTBF, cable info
January 2007
10005594-02 Updated format, Emerson contact and regulatory info, and monitor section
April 2008
Regulatory Agency Warnings & Notices
The Emerson Katana3752 meets the requirements set forth by the Federal Communica-tions Commission (FCC) in Title 47 of the Code of Federal Regulations. The following infor-mation is provided as required by this agency.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
FCC RULES AND REGULATIONS — PART 15
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason-able protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communica-tions. However, there is no guarantee that interference will not occur in a particular installa-tion. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna
• Increase the separation between the equipment and receiver
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
• Consult the dealer or an experienced radio/TV technician for help
Caution: Making changes or modifications to the Katana3752 hardware without the explicit consent of Emerson Network Power could invalidate the user’s authority to operate this equipment.
EMC COMPLIANCE
The electromagnetic compatibility (EMC) tests used a Katana3752 model that includes a front panel assembly from Emerson Network Power.
Caution: For applications where the Katana3752 is provided without a front panel, or where the front panel has been removed, your system chassis/enclosure must provide the required electromagnetic interference (EMI) shielding to maintain EMC compliance.
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10005594-02 Katana®3752 User’s Manual i
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EC Declaration of ConformityAccording to EN 45014:1998
Manufacturer’s Name: Emerson Network PowerEmbedded Computing
Manufacturer’s Address: 8310 Excelsior DriveMadison, Wisconsin 53717
Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives,
Product: Real-Time Processing Blade
Model Name/Number: Katana3752/10005238-xx
has been designed and manufactured to the following specifications:
EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and methods of measurement
EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods of measurement
EN300386 V.1.3.2:2003-05 Electromagnetic compatibility and radio spectrum matters (ERM);Telecommunication network equipment; EMC requirements
As manufacturer we hereby declare that the product named above has been designed to comply with the relevant sections of the above referenced specifications. This product complies with the essential health and safety requirements of the EMC Directive and RTTE Directive. We have an inter-nal production control system that ensures compliance between the manufactured products and the technical documentation.
Issue date: April 21, 2008
Bill FleuryCompliance Engineer
Katana®3752 User’s Manual 10005594-02ii
Contents
1 Overview Cache Memory . . . . . . . . . . . . . . . . . . . . 4-11
Components and Features . . . . . . . . . . . 1-1Functional Overview . . . . . . . . . . . . . . . . 1-3Additional Information . . . . . . . . . . . . . . 1-4
Product Certification . . . . . . . . . . . . . 1-4RoHS Compliance. . . . . . . . . . . . . . . . 1-5Terminology and Notation . . . . . . . . 1-5Technical References. . . . . . . . . . . . . 1-6
2 SetupElectrostatic Discharge . . . . . . . . . . . . . . 2-1Katana®3752 Circuit Board . . . . . . . . . . 2-1
JTAG/COP Break-Out Board . . . . . . . 2-6Identification Numbers . . . . . . . . . . . 2-6Connectors . . . . . . . . . . . . . . . . . . . . . 2-6
Katana®3752 Setup . . . . . . . . . . . . . . . . 2-7Power Requirements . . . . . . . . . . . . . 2-7Environmental Considerations . . . . 2-7
Troubleshooting . . . . . . . . . . . . . . . . . . . . 2-7Technical Support . . . . . . . . . . . . . . . 2-8Product Repair . . . . . . . . . . . . . . . . . . 2-9
3 Reset LogicGeneral Overview . . . . . . . . . . . . . . . . . . . 3-1Reset Sources . . . . . . . . . . . . . . . . . . . . . . 3-3
CompactPCI Reset Enable . . . . . . . . 3-3Power Monitor . . . . . . . . . . . . . . . . . . 3-3750GL Processor Reset . . . . . . . . . . . 3-3Ethernet Switch Reset . . . . . . . . . . . . 3-4
4 ProcessorsProcessor Overview . . . . . . . . . . . . . . . . . 4-1
Features . . . . . . . . . . . . . . . . . . . . . . . . 4-1Physical Memory Map . . . . . . . . . . . . 4-2
Processor Reset. . . . . . . . . . . . . . . . . . . . . 4-4Processor Initialization. . . . . . . . . . . . . . . 4-4
Hardware Implementation Dependent 0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Hardware Implementation Dependent 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Hardware Implementation Dependent 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Exception Handling . . . . . . . . . . . . . . . . . 4-8Exception Processing . . . . . . . . . . . . . . . . 4-9
L1 Cache . . . . . . . . . . . . . . . . . . . . . . 4-11L2 Cache . . . . . . . . . . . . . . . . . . . . . . 4-11
JTAG/COP Header Access . . . . . . . . . . . 4-13Console Serial Ports . . . . . . . . . . . . . . . . 4-16
5 System ControllersOverview . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1CPU Interface . . . . . . . . . . . . . . . . . . . . . . .5-2SDRAM Controller . . . . . . . . . . . . . . . . . . .5-2Device Controller Interface. . . . . . . . . . . .5-3Internal (IDMA) Controller . . . . . . . . . . . .5-3Timer/Counters . . . . . . . . . . . . . . . . . . . . .5-3PCI Interface . . . . . . . . . . . . . . . . . . . . . . . .5-4
PCI Configuration Space. . . . . . . . . . 5-4PCI Device and Vendor ID Assignment
5-4PCI Read/Write. . . . . . . . . . . . . . . . . . 5-4PCI Interface Registers . . . . . . . . . . . 5-5
Doorbell Registers . . . . . . . . . . . . . . . . . . .5-5Outbound Doorbells . . . . . . . . . . . . . 5-5Inbound Doorbells. . . . . . . . . . . . . . . 5-5
Watchdog Timer . . . . . . . . . . . . . . . . . . . .5-6Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6On-Card Memory . . . . . . . . . . . . . . . . . . . .5-6
User Flash . . . . . . . . . . . . . . . . . . . . . . 5-6SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . 5-7EEPROMs . . . . . . . . . . . . . . . . . . . . . . . 5-7
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . .5-7GPIO Signal Definitions . . . . . . . . . . . . . . .5-9
6 Device Bus PLDsReset Registers . . . . . . . . . . . . . . . . . . . . . .6-1Interrupt Registers . . . . . . . . . . . . . . . . . . .6-3Product Identification . . . . . . . . . . . . . . . .6-4PCI Enumeration. . . . . . . . . . . . . . . . . . . . .6-4Revision Registers . . . . . . . . . . . . . . . . . . .6-5Board Configuration Registers. . . . . . . . .6-5Hot Swap Register . . . . . . . . . . . . . . . . . . .6-6
7 Real-Time ClockBlock Diagram. . . . . . . . . . . . . . . . . . . . . . .7-1Operation . . . . . . . . . . . . . . . . . . . . . . . . . .7-1Clock Operation . . . . . . . . . . . . . . . . . . . . .7-2
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8 EthernetSwitch Features. . . . . . . . . . . . . . . . . . . . . .8-1Switch Configuration . . . . . . . . . . . . . . . . .8-3Ethernet Addresses . . . . . . . . . . . . . . . . . .8-3Front Panel Ethernet Port Connector . . .8-4
9 IPMI ControllerSMB/IPMI Overview . . . . . . . . . . . . . . . . . .9-1I/O Interface . . . . . . . . . . . . . . . . . . . . . . . .9-4I2C Interfaces . . . . . . . . . . . . . . . . . . . . . . .9-5IPMI Message Protocol . . . . . . . . . . . . . . .9-6IPMI Network Function Codes . . . . . . . . .9-7IPMI Completion Codes. . . . . . . . . . . . . . .9-9Zircon PM IPMI Commands . . . . . . . . . 9-10
Get Sensor Reading (Sensor/Event) . . .9-11
Master Write-Read I2C (Application) . .9-14
Write Setting (OEM) . . . . . . . . . . . .9-15Read Setting (OEM) . . . . . . . . . . . . .9-16Set Heartbeat (OEM) . . . . . . . . . . . .9-17Get Heartbeat (OEM). . . . . . . . . . . .9-18
IPMI FRU Information. . . . . . . . . . . . . . . 9-18IPMI Device SDR Repository . . . . . . . . . 9-19IPMI Event Messages . . . . . . . . . . . . . . . 9-20
10 Hot SwapcPCI Reset Blocking . . . . . . . . . . . . . . . . 10-1Power Supply Monitoring . . . . . . . . . . . 10-1Hot Swap LED and Ejector Switch Control . .
10-2HEALTHY* Signal . . . . . . . . . . . . . . . . . . 10-2
11 Backplane SignalsOverview . . . . . . . . . . . . . . . . . . . . . . . . . 11-1Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
12 MonitorCommand-Line Features. . . . . . . . . . . . 12-1Basic Operation. . . . . . . . . . . . . . . . . . . . 12-3
Power-Up/Reset Sequence. . . . . . .12-3Monitor Memory Usage . . . . . . . . .12-6POST Diagnostic Results . . . . . . . . .12-6
Monitor Recovery and Updates . . . . . . 12-7Recovering the Monitor . . . . . . . . .12-7
Updating the Monitor. . . . . . . . . . . 12-8Resetting Environment Variables . 12-8
Monitor Command Reference . . . . . . . 12-9Command Syntax . . . . . . . . . . . . . . 12-9Typographic Conventions . . . . . . . 12-9
Boot Commands . . . . . . . . . . . . . . . . . 12-10bootd . . . . . . . . . . . . . . . . . . . . . . . . 12-10bootelf . . . . . . . . . . . . . . . . . . . . . . . 12-10bootm . . . . . . . . . . . . . . . . . . . . . . . 12-10bootp . . . . . . . . . . . . . . . . . . . . . . . . 12-10bootv . . . . . . . . . . . . . . . . . . . . . . . . 12-10bootvx . . . . . . . . . . . . . . . . . . . . . . . 12-11rarpboot . . . . . . . . . . . . . . . . . . . . . 12-11tftpboot. . . . . . . . . . . . . . . . . . . . . . 12-11
Memory Commands . . . . . . . . . . . . . . 12-11cmp . . . . . . . . . . . . . . . . . . . . . . . . . 12-11cp . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12find . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12md . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12mm. . . . . . . . . . . . . . . . . . . . . . . . . . 12-13mw . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13nm . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Flash Commands . . . . . . . . . . . . . . . . . 12-14cp . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14erase . . . . . . . . . . . . . . . . . . . . . . . . 12-14flinfo. . . . . . . . . . . . . . . . . . . . . . . . . 12-14protect. . . . . . . . . . . . . . . . . . . . . . . 12-15
EEPROM / I2C Commands. . . . . . . . . . 12-15eeprom . . . . . . . . . . . . . . . . . . . . . . 12-16icrc32 . . . . . . . . . . . . . . . . . . . . . . . . 12-16iloop . . . . . . . . . . . . . . . . . . . . . . . . . 12-16imd . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16imm . . . . . . . . . . . . . . . . . . . . . . . . . 12-16imw . . . . . . . . . . . . . . . . . . . . . . . . . 12-16inm . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16ipmifirmload. . . . . . . . . . . . . . . . . . 12-17iprobe . . . . . . . . . . . . . . . . . . . . . . . 12-17
Environment Commands . . . . . . . . . . 12-17envinit . . . . . . . . . . . . . . . . . . . . . . . 12-17printenv. . . . . . . . . . . . . . . . . . . . . . 12-17saveenv . . . . . . . . . . . . . . . . . . . . . . 12-18setenv . . . . . . . . . . . . . . . . . . . . . . . 12-18
Test Commands . . . . . . . . . . . . . . . . . . 12-18diags. . . . . . . . . . . . . . . . . . . . . . . . . 12-18mtest . . . . . . . . . . . . . . . . . . . . . . . . 12-18um . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
Other Commands. . . . . . . . . . . . . . . . . 12-18
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Contents (continued)
autoscr . . . . . . . . . . . . . . . . . . . . . . .12-18base . . . . . . . . . . . . . . . . . . . . . . . . .12-19boardreset. . . . . . . . . . . . . . . . . . . .12-19coninfo . . . . . . . . . . . . . . . . . . . . . . .12-19crc16. . . . . . . . . . . . . . . . . . . . . . . . .12-19crc32. . . . . . . . . . . . . . . . . . . . . . . . .12-19echo . . . . . . . . . . . . . . . . . . . . . . . . .12-19enumpci. . . . . . . . . . . . . . . . . . . . . .12-19fpledoff . . . . . . . . . . . . . . . . . . . . . .12-20fruget . . . . . . . . . . . . . . . . . . . . . . . .12-20frugetuser . . . . . . . . . . . . . . . . . . . .12-20frusetuser . . . . . . . . . . . . . . . . . . . .12-20gethvr. . . . . . . . . . . . . . . . . . . . . . . .12-20getmonver. . . . . . . . . . . . . . . . . . . .12-20getspr . . . . . . . . . . . . . . . . . . . . . . . .12-20go . . . . . . . . . . . . . . . . . . . . . . . . . . .12-20help. . . . . . . . . . . . . . . . . . . . . . . . . .12-21iminfo . . . . . . . . . . . . . . . . . . . . . . . .12-21isdram . . . . . . . . . . . . . . . . . . . . . . .12-21loop. . . . . . . . . . . . . . . . . . . . . . . . . .12-21
memmap . . . . . . . . . . . . . . . . . . . . 12-21moninit . . . . . . . . . . . . . . . . . . . . . . 12-21pci. . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22reset . . . . . . . . . . . . . . . . . . . . . . . . . 12-22run . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22setspr . . . . . . . . . . . . . . . . . . . . . . . . 12-22script . . . . . . . . . . . . . . . . . . . . . . . . 12-23showmac. . . . . . . . . . . . . . . . . . . . . 12-23showpci . . . . . . . . . . . . . . . . . . . . . . 12-23sleep. . . . . . . . . . . . . . . . . . . . . . . . . 12-23version . . . . . . . . . . . . . . . . . . . . . . . 12-23
Environment Variables . . . . . . . . . . . . 12-23Troubleshooting. . . . . . . . . . . . . . . . . . 12-26Download Formats. . . . . . . . . . . . . . . . 12-26
Binary. . . . . . . . . . . . . . . . . . . . . . . . 12-26Motorola S-Record . . . . . . . . . . . . 12-27
13 Acronyms
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Figures
Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 2-1: Katana®3752 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2: Component Map, Top (Rev. 03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 2-3: Component Map, Bottom (Rev. 03). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-4: Jumper and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 3-1: Katana®3752 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2: 750GL Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 4-1: 750GL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-2: 750GL Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-3: JTAG/COP Break-Out-Board Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Figure 4-4: Standard Console Cable Wiring, #10007665-00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Figure 5-1: MV64460 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Figure 5-2: I2C Interface Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Figure 7-1: M41T00 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Figure 8-1: Ethernet Ports Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Figure 9-1: IPMB Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Figure 12-1: Example Monitor Start-up Display for CPU1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Figure 12-2: Example Monitor Start-up Display for CPU2 and CPU3 . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Figure 12-3: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
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Tables
Table 1-1: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Table 1-2: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 4-1: Katana®3752 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Table 4-2: Katana®3752 Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-3: CPU Internal Register Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-4: 750GL Exception Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table 4-5: 750GL JTAG/COP Interface Pin Assignments, P1—P3, P5 . . . . . . . . . . . . . . . . . . . . . . . 4-13
Table 4-6: Serial Console Port Pin Assignments, (P2, P3, P4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Table 5-1: PCI Device and Vendor IDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Table 5-2: NVRAM Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Table 5-3: GPIO Signals Definitions for Processor #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Table 5-4: GPIO Signals Definitions for Processors #2 and #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 7-1: RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 8-1: Front Panel Ethernet Port Pin Assignments, P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Table 9-1: Zircon PM General Purpose I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Table 9-2: Zircon PM Analog-to-Digital Input Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Table 9-3: IPMB Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Table 9-4: Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Table 9-5: Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Table 9-6: Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Table 9-7: Completion Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Table 9-8: Zircon PM IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Table 9-9: Get Sensor Reading Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Table 9-10: Master Write-Read I2C Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Table 9-11: Write Setting Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Table 9-12: Read Setting Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Table 9-13: Set Heartbeat Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Table 9-14: Get Heartbeat Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Table 9-15: FRU Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Table 9-16: IPMI Event Messages Generating Sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Table 9-17: Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Table 9-18: System Firmware Progress OEM Event Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Table 11-1: cPCI Connector Pin Assignments, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Table 11-2: cPCI Connector Pin Assignments, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Table 11-3: cPSB Connector Pin Assignments, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Table 12-1: Debug LEDs per CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Table 12-2: POST Diagnostic Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Table 12-3: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
Table 12-4: VLAN Port Name Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
10005594-02 Katana®3752 User’s Manual ix
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ual 10005594-02
Registers
Register 4-1: 750GL Hardware Implementation Dependent (HID0) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Register 4-2: 750GL Hardware Implementation Dependent (HID1) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Register 4-3: 750GL Hardware Implementation Dependent (HID2) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Register 4-4: CPU Machine State (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Register 4-5: L2 Cache Control Register (L2CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Register 6-1: Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Register 6-2: Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Register 6-3: Reset Out Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Register 6-4: Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Register 6-5: Interrupt Pending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Register 6-6: Product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Register 6-7: EReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Register 6-8: Hardware Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Register 6-9: PLD Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Register 6-10: Board Configuration 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Register 6-11: Board Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Register 6-12: Board Configuration 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Register 6-13: Hot Swap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Register 8-1: BCM5691 PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Register 8-2: MAC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Register 12-1: Monitor POST Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
10005594-02 Katana®3752 User’s Manual i
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(blank page)
ual 10005594-02
10005594-02 Katana®3752
Section 1
Overview
The Emerson Katana®3752 is a high-performance processing blade for use in a Compact-PCI Packet-Switched Backplane (cPSB). The Katana®3752 draws processing power from up to three IBM PowerPC® 750GL microprocessors, running at a speed of up to 800MHz. The microprocessors interface with each other by means of a local Peripheral Component Inter-connect (PCI) bus. A managed, gigabit Ethernet switch provides the core of the packet switching functionality. The switch routes two 1000BaseT Ethernet ports to the cPSB con-nector, four ports to the microprocessors, and one port to the front panel. The Katana®3752 supports various memory configurations, user flash memory, three front-panel serial ports, and a front-panel 10/100/1000BaseT Ethernet port.
COMPONENTS AND FEATURES
The following is a brief summary of the Katana®3752 hardware components and features:
CPUs: The Katana®3752 features three IBM 750GL central processing units (CPUs), operating at a rate of up to 800MHz. Each CPU is a 32-bit PowerPC RISC microprocessor with 32-kilobyte, Level-1, data and instruction caches, as well as a one-megabyte, four-way, set-associative, Level-2 cache. The CPUs are identical, except that processor #1 is configured as the PCI host with a bank of socketed flash memory.
System Controller / PCI Bridge:
The Katana®3752 employs three identical system controller / PCI bridge devices from Mar-vell. The Discovery™ III MV64460 is a single-chip solution that provides a high-speed (up to 200 MHz) 60x bus interface, double-data rate (DDR) SDRAM controller, a 64-bit 66-MHz PCI interface, three 10/100/1000BaseT Ethernet MAC controllers, two multi-protocol serial controllers (MPSC), an interrupt controller, and 32 general-purpose input/output (I/O) sig-nals.
SDRAM: The Katana®3752 allows for a 72-bit Small-Outline Dual In-Line Memory Module (SO-DIMM) of up to one gigabyte (when available) for each of the three CPUs. This SDRAM sup-ports 400MHz double data rate (DDR) operations and has Error-Correcting Code (ECC).
FLASH: The Katana®3752 supports up to 64 megabytes of soldered user flash memory for each CPU. It also supports 512 kilobytes of socketed flash for processor #1. The flash memory conforms to the Intel StrataFlash™ architecture. Each CPU is capable of booting from flash memory.
Ethernet Switch: A BCM5691 gigabit Ethernet multilayer switch from Broadcom connects two 1000BaseT Ethernet ports from processor #1, one from processor #2, one from processor #3, two from the CompactPCI packet-switched backplane (cPSB), and one 10/100/1000 Ethernet port from the front panel. Processor #1 can configure all the PHY devices through the switch’s MDI interfaces.
User’s Manual 1-1
Overview: Components and Features
Serial I/O: Each of the IBM 750GL CPUs provide an asynchronous console serial port, which supports EIA-232 signal levels. These serial ports are accessible via three micro-DB9 connectors on the Katana®3752 front panel.
IPMI: The Katana®3752 supports an Intelligent Platform Management Interface (IPMI) by using a Zircon PM controller device from QLogic Corporation.
Hot Swap: The Katana®3752 provides limited Hot Swap capability by supporting multiple inser-tion/removal cycles without impacting normal system operation.
Katana®3752 User’s Manual 10005594-021-2
Overview: Functional Overview
FUNCTIONAL OVERVIEW
The following block diagram provides a functional overview for the Katana®3752.
Figure 1-1: General System Block Diagram
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10005594-02 Katana®3752 User’s Manual 1-3
Overview: Additional Information
ADDITIONAL INFORMATION
This section lists the Katana®3752 hardware’s regulatory certifications and briefly dis-cusses the terminology and notation conventions used in this manual. It also lists general technical references.
Mean time between failures (MTBF) has been calculated at 177,328 hours using Telcordia SR-232, Issue 1, Reliability Prediction for Electronic Equipment at 40°C.
Product CertificationThe Katana®3752 hardware has been tested to comply with various safety, immunity, and emissions requirements as specified by the Federal Communications Commission (FCC), Underwriters Laboratories (UL), and others. The following table summarizes this compli-ance.
Table 1-1: Regulatory Agency Compliance
Type: Specification: Safety UL60950, CSA C22.2 No. 60950 – Safety of Information
Technology Equipment, including Electrical Business Equipment (BI-National)
IEC60950/EN60950 – Safety of Information Technology Equipment (Western Europe)
Global IEC – CB Scheme Report IEC60950, all country deviations
AS/NZS 60950 – 60950, Australia and New Zealand
Environmental NEBS: Telecordia GR-63 – Section 4.1.1 Transportation and Storage Environmental
Criteria; Section 4.3 Equipment Handling Criteria; Section 4.4.1 Earthquake Environment and Criteria;Section 4.4.3 Office Vibration Environment and Criteria; Section 4.4.4 Transportation Vibration CriteriaSection 5 Airborne Contaminants
EMC FCC Part 15, Class B – Title 47, Code of Federal Regulations, Radio Frequency Devices
ICES 003, Class B – Radiated and Conducted Emissions, Canada
NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack level testing only)
ETSI EN300386 – Electromagnetic Compatibility and Radio Spectrum Matters (ERM), Telecommunication Network Equipment, Electromag-netic Compatibility (EMC) Requirements
AS/NZS 3548 – Radiated and Conducted Emissions, Australia and New Zealand
Katana®3752 User’s Manual 10005594-021-4
Overview: Additional Information
Emerson maintains test reports that provide specific information regarding the methods and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or a poorly grounded chassis may adversely affect the Katana®3752 hardware’s ability to comply with any of the stated specifications.
The UL web site at ul.com has a list of Emerson’s UL certifications. To find the list, search in the online certifications directory using Emerson’s UL file number, E190079. There is a list for products distributed in the United States, as well as a list for products shipped to Can-ada. To find the Katana®3752, search in the list for 10005238-xx, where xx changes with each revision of the printed circuit board.
RoHS ComplianceThe Katana3752 is compliant with the European Union’s RoHS (Restriction of Use of Haz-ardous Substances) directive created to limit harm to the environment and human health by restricting the use of harmful substances in electrical and electronic equipment. Effec-tive July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexavalent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphe-nyl ethers (PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with lead-free solder. Configurations that are 5-of-6 are built with tin-lead solder per the lead-in-solder RoHS exemption.
To obtain a certificate of conformity (CoC) for the Katana3752, send an e-mail to [email protected] or call 1-800-356-9602. Have the part number (e.g.,C000####-##) for your configuration available when contacting Emerson.
Terminology and Notation
Active low signals: An active low signal is indicated with an asterisk * after the signal name.
Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to 32 bits, double long word refers to 64 bits.
PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also known as FPGA, CPLD, EPLD, etc.).
Radix 2 and 16: Hexadecimal numbers end with a subscript 16. Binary numbers are shown with a subscript 2.
10005594-02 Katana®3752 User’s Manual 1-5
Overview: Additional Information
Technical ReferencesFurther information on basic operation and programming of the Katana®3752 compo-nents can be found in the following documents.
Table 1-2: Technical References
Device/Interface: Type: Document: 1 CompactPCI CompactPCI® Specification
(PCI Industrial Computers Manufacturers Group, PICMG® 2.0 R3.0, Oct. 1, 1999)
Hot Swap Specification(PICMG® 2.1 R2.0, Jan. 17, 2001)
System Management Specification(PICMG® 2.9 R1.0, Feb. 2, 2000)
PCI Telecom Mezzanine/Carrier Card Specification(PICMG® 2.15 R1.0, Apr. 11, 2001)
Packet Switching Backplane Specification(PICMG® 2.16 R1.0, Sept. 5, 2001)
http://www.picmg.org
CPU 750GL IBM PowerPC™ 750GX and 750GL RISC Microprocessor User’s Manual(IBM Corporation, Version 1.2, March 27, 2006)
IBM PowerPC™ 750GL RISC Microprocessor Revision Level DD1.X Datasheet(IBM Corporation, Preliminary, Version 1.2, March 13, 2006)
PowerPC™ Microprocessor Family: The Programming Environments for 32-Bit Microprocessors(IBM Corporation, G522-0290-01)
PowerPC™ Microprocessor Family: The Bus Interface for 32-Bit Microprocessors(IBM Corporation, G522-0291-00)
http://www.ibm.com
Katana®3752 User’s Manual 10005594-021-6
Overview: Additional Information
Ethernet BCM5461S, BCM5691
BCM5461S 10/100/1000Base-T Gigabit Ethernet Transceiver Advance Data Sheet(Broadcom Corp., 5461S-DS07)
BCM5691 12-Port Gigabit Ethernet Multilayer Switch Advance Data Sheet(Broadcom Corp., 5691-DS01-R, March 28, 2002)
StrataXGS™ BCM5690 Programmer’s Reference Guide(Broadcom Corp., 5690-PG100-R, Sept. 18, 2002)
http://www.broadcom.com
IEEE Standard for Information Technology: IEEE Std 802.3, 2000 Edition(IEEE: New York, NY)
http://www.ieee.org
Hot Swap Controller LTC1643L LTC1643L/LTC1643L-1/LTC1643H PCI-Bus Hot Swap Controller Data Sheet(Linear Technology Corp., 1998)
http://www.linear.com
IPMI/IPMB IPMI — Intelligent Platform Management Interface Specification v1.5(Intel Corp., Hewlett-Packard Co., NEC Corp., Dell Computer Corp., Rev. 1.1, Feb. 20, 2002)
IPMI — Intelligent Platform Management Bus Communications Protocol Specification v1.0(Intel Corp., Hewlett-Packard Co., NEC Corp., Dell Computer Corp., Rev. 1.0, Sept. 16, 1998)
http://www.intel.com/design/servers/ipmi/spec.htm
IPMI Controller Zircon PM Zircon PM Technical Manual (QLogic Corp., 36000-510-03, Rev. C, Apr. 2002)
http://www.qlogic.com
PCI/PCI-X PCI Local Bus Specification (PCI Special Interest Group, Revision 2.3, 2002)
PCI-X Protocol Addendum to the PCI Local Bus Specification Revision 2.0(PCI Special Interest Group, July 29, 2002)
http://www.pcisig.com
PMC IEEE Standard for a Common Mezzanine Card (CMC) Family: IEEE Std 1386-2001(IEEE: New York, NY)
IEEE Standard for Physical and Environmental Layers for PCI Mezzanine Cards: IEEE Std 1386.1-2001(IEEE: New York, NY)
http://www.ieee.org
Device/Interface: Type: Document: 1 (continued)
10005594-02 Katana®3752 User’s Manual 1-7
Overview: Additional Information
If you have questions, please call Emerson Technical Support at 1-800-327-1251, visit the web site at http://www.emersonembeddedcomputing.com, or send e-mail to [email protected].
SerialInterface
EIA-232-F TIA/EIA-232-F: Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data Interchange(Electronic Industries Association, October 1997)
http://www.eia.com/
System Controller MV64460 MV6446x System Controller for PowerPC Processors(Marvell, MV-S101286-01, Rev. A, June 19, 2003)
http://www.marvell.com
1. Frequently, the most current information regarding addenda/errata for specific documents may be found on the corresponding web site.
Device/Interface: Type: Document: 1 (continued)
Katana®3752 User’s Manual 10005594-021-8
10005594-02 Katana®3752
Section 2
Setup
This chapter describes the physical layout of the boards, the setup process, and how to check for proper operation once the boards have been installed. This chapter also includes troubleshooting, service, and warranty information.
ELECTROSTATIC DISCHARGE
Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the Katana®3752 hardware. Electronic devices, especially those with programmable parts, are susceptible to ESD, which can result in oper-ational failure. Unless you ground yourself properly, static charges can accumulate in your body and cause ESD damage when you touch the board.
Caution: Use proper static protection and handle Katana®3752 boards only when absolutely necessary. Always wear a wriststrap to ground your body before touching a board. Keep your body grounded while handling the board. Hold the board by its edges–do not touch any components or circuits. When the board is not in an enclosure, store it in a static-shielding bag.
To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a static-shielding bag does not provide any protection–place it on a grounded dissipative mat. Do not place the board on metal or other conductive surfaces.
KATANA®3752 CIRCUIT BOARD
The Katana®3752 circuit board is 6U CompactPCI card assembly. It uses a 14-layer printed circuit board with the following dimensions.
Table 2-1: Circuit Board Dimensions
The following figures show the front panel, component maps, and jumper locations for the Katana®3752 circuit board.
Width: Depth: Height:9.19 in. (233.35 mm) 6.30 in. (160 mm) < 0.8 in. (< 20.32 mm)
!
User’s Manual 2-1
Setup: Katana®3752 Circuit Board
Figure 2-1: Katana®3752 Front Panel
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Katana®3752 User’s Manual 10005594-022-2
Setup: Katana®3752 Circuit Board
Figure 2-2: Component Map, Top (Rev. 03)
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C19
C91
C203
C200
C116
C177C9
5
C46
JP1
C172C153
L17
L16
U21
U28
C88
C57
C41
C115
C110
C31
C69
C129
C30
JP3
RN47RN46
RN45RN44RN2RN1 RN4 RN7RN3 RN32RN30RN26 RN28RN23
RN64
RN60RN59RN52RN50
RN48
RN49
RN61RN54 RN55 RN57 RN63
RN43
RN42
RN20
RN22
RN14RN12
RN21
RN17RN16RN11RN8
RN5
RN6
RN29RN9 RN33RN18 RN19 RN38RN36RN34
RN24
RN25
RN39RN31RN13 RN15 RN40
RN62
RN27 RN41
RN37
RN58
L9
L10
C150
C36
C45
C25
C32C24
C28
C87
C132
C106
C42
C109
C62
C135
C23
C77
C114C78
L8
JP4
RN10RN35
RN51 RN53 RN56
C17U4
U13
U22
Y3 U23
C85 C102
C59
C141
C143
C136
C166
C171
L13
C130
C60
C18
C118
C121
C113
C124
C128
C131
C186
C194
C197
C180
C191
C98
C89
C80
C111
C82
C3
C14
C12
C10
C4 C8
C183
C105
U39U26U1
Y1
JP2
Y2
U37
U12
U19 U29 U33
U38
U9
C144
C108
C193
C196
C190
C188
C185
C182
C168
C179
C167
C178
C195
C192
C189
C187
C184
C181
U27
C90
U10
U31
C125 C138 C146
C156
C160
C163
C164
C175C20
C33 C39
C35 C68 C93 L12L11 L15L14L7L6L2L1
L3 L4
C133C13 C63 C137
C151
C152
U8
U36
U35
C15
4
C1
C2 C50
C49
C99
C10
7
C86
C97
C104
C103
C12
0
R20R40
R21
R24R44
R41
R61 R64R2
5
R80
R19
R39
R22
R23R43
R42
R59
R85
R86
R26
R58
R60
R79 R81
R84
R82
R83
R1R2
R3
R4
R5R6 R7
R8R9
R10
R12
R13
R14
R15
R11
R17
R18
R16
R32
R33
R34
R35
R46
R38
R45
R47
R48
R50
R49
R51
R52
R53
R54
R55
R57
R62
R63
R65
R66
R67
R68
R69
R71
R72
R70 R7
3
R74
R75
R76
R77
R78
R56
R27
C169C170
C16
R30
R31
R28
R29
R36R37
E190079
C1214
C1215
R125
5
R1256
C12
16R1
257 U30
J1 — cPCI Connector
J2 — cPCI Connector
J3 — cPSB Connector
U16SO-DIMMDDR RAM
U2SO-DIMMDDR RAM
U24SO-DIMMDDR RAM
U5MV64460
System Controller
U17MV64460
System Controller
U25MV64460
System Controller
P4EIA-232
Micro D
B9
P3EIA-232
Micro D
B9
P2EIA-232
Micro D
B9
SW1Reset
Switch
P1100BASE-T
RJ45
CR1Hot Swap
LED
CR3 — Ethernet LEDs
CR4 — Ethernet LEDs
J4Hot Swap
Header
CR5 — Ethernet LEDs
U15BCM5691
12-Port GigabitEthernet Switch
U32Socketed
Flash
J7ISP/JTAG
CR2Power LED
P5IBM750GLCOP/JTAG
U11IBM750GLProcessor
#3
U20IBM750GLProcessor
#2
U34IBM750GLProcessor
#1
U6HSLPLD
10005594-02 Katana®3752 User’s Manual 2-3
Setup: Katana®3752 Circuit Board
Figure 2-3: Component Map, Bottom (Rev. 03)
U57
U80
U76
C879
C873
C874
C872
C918
C595
C599
C259
C257
C260
C263 C217
C256
C258
C262
R742
R1037
10005238-03 REVA
*
*
*
**
*
*
**
**
*
* *
*
*
*
*
*
*
*
*
*
*
*
*
**
*
*
*
*
*
*
COPYRIGHT 2006CR22
CR21
F2
U70
R403
R430
R1166
R116
4
R101
4R1162
R769
R398
R966R1124 R724 R370
R122
5
R1223
R122
2
R1220
R1114R1150
R114
5
R117
4
R1009
R595
R323
R1149
L54
L63
L47
L35
L48
L57
L49
L50
L37
L46
L39
L34
L24
L31
L45
R770
RN523
RN521
RN519
RN517
RN522
RN520
RN518
RN514
RN153
RN152
U52
U82
U49U53
U63
Y7
Y6
Y5
U69
U59
U42
U62
U74
U83
U78
U61U60
U41U40
U77U81
U71 U68
Y8
L53
F1
CR27 CR15 CR10
R1136
R1165
R1143R1144
CR19
R1171
R451
R161
R157
R1104R1105R1106R1107 R721
R720R719R718
R409R408R407R406
U67
RN262RN436 RN429 RN406
RN394RN110
RN119
RN98RN134 RN113RN282 RN251RN284 RN277
RN75
RN74
RN73
RN72
RN68RN67
RN66RN65
RN96
RN95
RN94
RN90
RN89
RN88
RN87
RN70
RN69
RN92
RN91
RN71
RN93
RN97
RN227
RN226
RN225
RN224
RN220
RN219
RN218
RN21
7
RN250
RN249
RN248
RN247
RN243
RN242
RN241
RN240
RN222
RN221
RN245
RN244
RN223RN246
RN395
RN365
RN396
RN366
RN397
RN367
RN398
RN368
RN401
RN372
RN402
RN373
RN403 RN3
74
RN404
RN375
RN369RN3
90
RN370RN399
RN400
RN371
RN115
RN356
RN289 RN276
RN391
RN392
RN393
RN461
RN462
RN460
RN311
RN312
RN304
RN156
RN157
RN155
RN453RN5
13
RN363
RN116
RN433 RN430
RN418RN434 RN431
RN364
RN480
RN476 RN471
RN511
RN512
RN348
RN516
RN515
RN362
RN112
RN331
RN477
RN509
RN203
RN204
RN205
RN194
RN239
RN197
RN498RN163
RN164RN170
RN140 RN135
RN120RN141 RN114
RN357
RN358
RN359
RN355
RN360
RN307RN279RN283RN286
RN285
RN488
RN208
RN487
RN306RN313
RN305 RN281
RN131
RN463 RN457
RN323RN349
RN335 RN330 RN316RN322
RN193 RN186
RN187
RN185 RN180 RN171RN207
RN473
RN486 RN478 RN468
RN490
RN491
RN321RN329RN345RN351 RN138RN144RN160RN165RN507
RN86
RN85
RN84
RN83
RN79
RN78
RN77RN76
RN109
RN108
RN107
RN106
RN102
RN101
RN100
RN99
RN81
RN80
RN104
RN103
RN105 RN82
RN238
RN237
RN236
RN235
RN231
RN230
RN229
RN228
RN274
RN273
RN272
RN271
RN267
RN266
RN265
RN264
RN233
RN232
RN269
RN268
RN270
RN234
RN407
RN377
RN408
RN378
RN409
RN379
RN410
RN380
RN414
RN384
RN415
RN385
RN416 RN3
86
RN417
RN387
RN381
RN411
RN382RN4
12
RN383RN413
RN492
RN489
RN465 RN441RN452 RN449RN317 RN294RN309 RN301 RN195 RN174RN189 RN177
RN143
RN111
L58
L32
L40
CR28CR29CR30
CR11CR12CR13
CR16CR17CR18
CR14 CR8CR25CR20
CR31
CR32
CR33
CR34
CR23R108
8
CR24
R1172
R1062
R1025R1026R1027
R1024R1061
RN148RN145
RN147
RN191
RN192
RN161
RN146
RN184
RN296RN295
RN303
RN347
RN346
RN298RN297
RN483
RN456RN334
RN484
RN455
RN445RN444
RN442RN443
RN166RN178
RN199
RN198
RN175
RN169
RN179 RN167
RN183
RN200
RN333 RN326
RN352
RN353
RN354
RN475
RN494
RN495
RN496
RN497
RN469
RN319
RN318
RN327 RN310
RN315RN459
RN479 RN470 RN466
R158
M2
M1
U43
U45
L56 L44
L43
L25
L26
R897
C836
C880
CR26
R379
R207R208
R340
R377
R848 L30
L33
L55
RN151
RN154
R816
R794
R817
RN118
CR9CR7
R101
R337
L29L41L52
R778
R714
R655R699
R712
R775R776R777
R417
R401
R347R384
R404
R414R415R416
R1054
R1184
R1086
R1108
R1110
R1153R1154R1185
C445
U51
RN435
RN427
RN428
RN425
RN424
RN423
RN422
RN419
RN421
RN420
RN432RN437RN446RN448RN451RN458RN464RN472RN481
RN499RN500
RN501RN508
RN502RN503
RN504RN505
RN506
RN426
RN485
RN275
RN260
RN261
RN258
RN257
RN256
RN255
RN252
RN254
RN253
RN263RN280RN287RN288RN293RN300RN302RN314RN324
RN336RN337
RN338RN339
RN340RN341
RN342RN343
RN332
RN259
RN328
RN142
RN129
RN130
RN127
RN126
RN125
RN124
RN121
RN123
RN122
RN136RN158 RN150RN162RN168RN176RN181RN188RN196
RN209RN210
RN211RN212
RN213RN214
RN215RN216
RN206
RN128
RN201
RN439RN440RN467
RN454
RN474
RN482
RN510
RN493
RN291RN292RN3
20
RN308
RN325
RN344
RN361
RN350
RN172
RN182
RN202
RN190
RN132RN133RN1
73
RN159
U54
C230
C229
C271 C243
C249
L18L19
L20L21
L22L23
RN139RN149RN290RN299RN438RN447RN450
C1056
C115
9
R104
8
R1199 R862
R128
R1226 R898
R102
R117
3
R185
R111
9
R947
R546
R245
R948
R994
R978
RN137
U50
L51 L38 L27
C278
C1091
L42
L36
L64
L65
L28
R331
R236
CR6
C1103
U65
C402C401
C395C396C397C398C399C400
RN388
R1120
R259
R846
C118
6
C1185
C272
RN405 RN278 RN117
U66
U64
L61
L62
L59L60
C108
4
C222C254
C283
C273C274
C275
C449
C305
C527
C610
C609
C646
C624
C626
C621
C804
C805
C868C935
C938
C942
C945
C901
C930
C108
3
C450
C277
C301
C1092C111
4
C576
C845
C239
C291
C366
C431
C387
C474
C502C503
C551C526
C542
C550C556
C581C586
C632
C618C642
C715C716
C769C768
C798C797
C810C809
C855
C838
C899C904
C910
C103
1
C1073C1080
C1123
C1151
C117
4C1
173
C1140C1141
C1157
C1162
C114
4
C1160
C1156
C1163
C1158
C1143C1128
C112
9
C1155
C1161
C906
C208
C204
C212
C210
C219
C225
C226
C220
C213
C223
C268
C224
C207
C269
C209 C205
C216
C235
C247C246
C236
C221
C238
C244
C255
C231
C211
C233
C234
C265
C276
C251
C279
C843
C227
C228
C237
C261
C266
C245
C270
C293
C250
C294
C363
C420
C280
C281
C282
C285
C304
C297
C298
C300
C302
C309
C267
C340C329
C330
C331
C332
C299
C308
C369
C357
C358
C346
C361
C347
C307
C311
C310
C372 C359
C360
C362
C324C325
C303
C426
C418C312
C383
C384C373
C349
C350
C351
C348
C339
C417
C320
C390
C392
C385
C365
C515
C424
C375
C318C423
C410
C391
C393
C413
C296
C367
C419
C480
C427
C411
C412
C394
C341
C314
C428
C386
C432
C434
C378
C319
C442
C435
C436
C429
C430
C403
C326
C342
C343
C353
C376
C443
C444
C415
C451C452
C458
C459
C421
C440
C425
C441
C381
C461
C439
C453
C462
C463
C468
C469C470
C471
C455
C422
C464
C465
C466
C481
C460
C476
C477
C478
C479
C382
C499
C482C483
C485
C525
C295
C500
C501
C504
C494C495
C484
C508
C509
C1064
C538
C511
C553C554
C513C512
C541
C557
C591
C505
C506
C242
C510
C519
C653
C552
C534
C528
C537
C531
C532
C539
C543
C514
C521
C548
C549
C564
C567
C568
C569
C566
C580
C582C570
C619
C592
C571
C529
C620
C593
C535
C625
C575
C615
C563
C579
C577
C583
C641
C584
C585
C587
C573
C622
C536
C598C597
C601
C600
C602
C823
C608
C645
C611C612
C613
C614
C616
C617
C623
C627
C635
C639
C728
C544
C634
C636
C637
C638
C640
C649
C650
C651
C652
C654
C633
C757
C520
C733
C647
C648
C659
C660
C661
C678C662
C663
C522
C644
C656
C657
C658
C677
C694
C679
C680
C771
C675
C688
C676
C689
C690
C691
C693
C704
C705
C696
C718C707
C745
C687
C701
C702
C717
C695
C516
C780
C777
C828
C605
C774
C700C703
C712
C692
C754
C714
C681
C682
C665
C710C711
C724
C725
C545
C749
C734
C735
C736
C565
C738
C739
C773
C829
C827
C674
C747C748
C750
C751
C752
C753
C765
C726
C755
C770
C720
C698
C697
C764
C794C766
C767
C760
C761
C762
C763
C785
C786
C787
C788
C789
C790
C791
C792
C793
C795
C796
C799
C778C800
C781
C782C783
C784
C814
C730
C740
C811
C779
C801
C808
C812
C818
C819
C807C806
C746
C815
C816C817
C820
C821
C723
C824
C830
C831
C832
C833
C737
C837
C856
C850
C840
C844C846
C847
C839
C849
C713
C851
C870
C861
C884
C922
C876
C863
C875
C852
C857
C934
C892
C893
C883
C869
C896
C925
C871
C886C885
C902
C887
C912C931
C932
C895
C939
C921
C891
C915
C862
C940
C897
C941
C903
C900
C905
C950
C929
C976C977
C978
C979
C992
C913
C968C969
C988
C989
C990
C991
C1008
C919
C943
C920
C924C936
C923
C888
C926
C927 C898
C858C955
C1006
C1009
C948
C911C961
C1002
C987
C1018
C1019
C100
7
C981
C106
6
C1052
C952
C986
C102
7
C1028
C1020
C964
C965
C944
C966
C967
C956
C1035
C1036
C102
9C1
038
C994
C982
C101
7
C1050
C101
3
C971
C864
C1012
C1054
C1069
C1037C1055
C1065
C995
C867
C101
0
C1051
C953
C1077C1070
C107
1
C334
C1085
C100
5
C1078
C1079
C1021
C103
0
C1022
C890
C1086C1087
C108
9C1
090
C323
C1060
C1042C1043
C1049
C102
6
C928
C1011
C103
4
C1061
C1062C1063
C1067
C1040
C1068C1041
C1093
C1094
C1095
C1096
C1057
C1058
C1059
C1074
C107
5
C1023
C104
4
C107
6
C1032
C103
3
C1099
C1100C1101
C110
2
C1081
C110
9
C108
2
C866
C1111
C1108C1112
C111
3
C1104
C1105C1106
C1088
C1154
C1110
C1115C1116
C1119C1133
C1127
C1152
C1130C1131
C1132
C113
4
C1146
C1122
C1164
C1166
C116
7
C1168
C116
9
C1170
C1150
C116
5
C1136C1137
C1138C1139
C1145
C114
7C1
148
C113
5
C1196
C1178
C1180
C1181
C1182
C118
4
C1149
C1189
C1191
C1198
C1195
C1176
C643
C727
C603
C604
C834
C835
C547
C555
C562
C497
C487
C498
C558
C493
C518
C561
C488C489
C491
C490
C559
C560
C546
C524
C492
C523
C507
C517
C284
C253
C364
C374
C980
C933
C606
C578
C333 C322
C993
C119
7
C206
C306
C252
C859
C853
C1192 C1183 C1177 C1172
C1175C1187 C1179 C1171
C337
C335
C336
C338
C894 C607
C352
C848
C889
C865
C907
C972
C101
4
C1045
C1048C1047C1046
C951
C984
C100
0
C102
4C699
C954
C959
C1053
C962C974
C1003
C960
C1015
C985
C1016
C958C957
C973
C100
4
C970
C963
C999
C975
C100
1
C937
C949
C1025
C629C630
C729
C772
C741
C706
C776
C719
C775
C683
C655C7
58
C664
C686
C756
C722
C743
C685
C759
C709
C670
C668
C673
C742
C669
C666C667
C672C671
C744
C684
C731C732C721
C708
C286
C406
C407
C377
C241
C486
C388
C368
C496
C380
C457
C289
C405
C345
C409
C404
C356 C3
28
C321
C370C379C389
C248
C408
C355
C371
C240
C354
C327
C313
C344
C315
C317C316
C878
C914
C917
C916
C882C881
C877
R95
R103
R104
R105
R106R107R108
R109R110
R111
R112
R113
R114R115
R116
R117
R172
R173R174R175 R133
R176R177R178R179
R180
R181
R182
R183
R184
R196
R469
R482
R483
R484
R485R486R487
R488R489
R490
R491
R492
R493R494
R466
R495
R551R552
R553R554R555
R556
R557R558R559
R560
R561
R525
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R276
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R329
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R348R349
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R605R606
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Katana®3752 User’s Manual 10005594-022-4
Setup: Katana®3752 Circuit Board
Figure 2-4: Jumper and Switch Locations, Top
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10005594-02 Katana®3752 User’s Manual 2-5
Setup: Katana®3752 Circuit Board
JTAG/COP Break-Out BoardEmerson supplies an optional break-out-board (#10005840-00) with three headers for eas-ier access to each processor’s JTAG port. Please refer to page 4-13 for additional details regarding the break-out-board.
Identification NumbersBefore you install the Katana®3752 circuit board in a system, you should record the follow-ing information:
❐ The board serial number: 682— _______________________________________ .The board serial number appears on a bar code sticker located on the back of the board.
❐ The board product identification: _____________________________________ .This sticker is located near the board serial number.
❐ The monitor version: _______________________________________________ .The version number of the monitor is on the start-up display.
❐ The operating system version and part number:__________________________ .This information is labeled on the master media supplied by Emerson or another vendor.
❐ Any custom or user ROM installed, including version and serial number:________________________________________________________________ .
It is useful to have these numbers available if you need to contact Technical Support at Emerson Network Power, Embedded Computing.
ConnectorsThe Katana®3752 circuit board has various connectors (see the figures beginning on page 2-3), summarized as follows:
P1: P1 is an RJ45 connector that provides front panel access to the 10/100/1000BaseT BCM5691 Ethernet switch. See Table 8-1 for pinouts.
P2, P3, P4: These are 9-pin micro-DB9 connectors on the front panel that provide EIA-232 console port access for each of the three 750GL processors. See “Console Serial Ports” on page 4-16 for pinouts.
P5: P5 is a 32-pin header on the circuit board for the 750GL COP/JTAG interface to all three pro-cessors. See Table 4-5 for pinouts.
J1—J2: J1 and J2 are 110-pin connectors that route to the cPCI backplane. (The Katana®3752 does not provide cPCI interface signals.) See “Section” on page 11-1 for pinouts.
J3: J3 is a 95-pin connector that routes packet switched (cPSB) signals to the backplane. See Table 11-3 for pinouts.
Katana®3752 User’s Manual 10005594-022-6
Setup: Katana®3752 Setup
J4: J4 is a 3-pin header on the circuit board (factory use only).
J7: J7 is a 10-pin header on the circuit board that provides an in-system programmable (ISP) JTAG interface to the programmable logic (PLD) devices (factory use only).
KATANA®3752 SETUP
You need the following items to set up and check the operation of the Emerson Katana®3752:
❐ Emerson Katana®3752 board
❐ Card cage and power supply
❐ Serial interface cable (EIA-232)
❐ Terminal
Save the antistatic bag and box for future shipping or storage.
Power RequirementsThe Emerson Katana®3752 circuit board typically requires from 58 to 68 watts of power. The exact power requirements for the Katana®3752 circuit board depend upon the applica-tion, board configuration, and ambient operating temperature. Please contact Emerson Technical Support at 1-800-327-1251 if you have specific questions regarding the board’s power requirements.
Note: The power value is an approximate–not measured–value.
Environmental ConsiderationsThe Emerson Katana®3752 circuit board is specified to operate in an ambient air tempera-ture range of 0° to +55° Centigrade. This range meets and exceeds the NEBS Telecordia GR-63 specification. The entire chassis must be cooled with forced air. The exact air flow requirement depends upon the chassis configuration and the ambient air temperature. The Katana®3752 board’s relative humidity and storage temperature ranges fully comply with NEBS Telecordia GR-63 specification.
TROUBLESHOOTING
In case of difficulty, use this checklist:
❐ Be sure the Katana®3752 circuit board is seated firmly in the card cage.
❐ Be sure the system is not overheating.
❐ Check the cables and connectors to be certain they are secure.
10005594-02 Katana®3752 User’s Manual 2-7
Setup: Troubleshooting
❐ If you are using the Katana®3752 monitor, run the power-up diagnostics and check the results. “Power-Up/Reset Sequence” on page 12-3 describes the power-up diagnostics.
❐ Check your power supply for proper DC voltages. If possible, use an oscilloscope to look for excessive power supply ripple or noise (over 50 mVpp below 10 MHz).
❐ Check that your terminal is properly connected to a console port.
❐ The Katana®3752 monitor uses values stored in on-card NVRAM (I2C EEPROM) to configure and set the baud rates for its console port. The lack of a prompt might be caused by incorrect terminal settings, incorrect configuration of the NVRAM, or a malfunctioning NVRAM. Try holding down the s character during a reset to abort autoboot using NVRAM parameters. If the prompt comes up, the NVRAM console parameters are probably configured incorrectly. Enter the command printenv to check the console configuration.
For more information about configuring the console, as well as instructions on how to recover or update the monitor, please refer to page 12-7.
Technical SupportIf you need help resolving a problem with your Katana®3752, visit http://www.emersonembeddedcomputing.com on the Internet or send e-mail to [email protected]. Please have the following information handy:
• Katana®3752 serial number and product identification from the stickers on the board
• baseboard model number and BIOS revision level (if applicable)
• version and part number of the operating system (if applicable)
• whether your board has been customized for options such as a higher processor speed or additional memory
• license agreements (if applicable)
If you do not have Internet access, please call Emerson for further assistance:
(800) 327-1251 or (608) 826-8006 (US)
44-131-475-7070 (UK)
Katana®3752 User’s Manual 10005594-022-8
Setup: Troubleshooting
Product RepairIf you plan to return the board to Emerson Network Power for service, visit http://www.emersonembeddedcomputing.com on the internet or send e-mail to [email protected] to obtain a Return Merchandise Authorization (RMA) number. We will ask you to list which items you are returning and the board serial number, plus your pur-chase order number and billing information if your Katana3752 hardware is out of war-ranty. Contact our Test and Repair Services Department for any warranty questions. If you return the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally shipped. Send it prepaid to:
Emerson Network Power, Embedded ComputingTest and Repair Services Department8310 Excelsior DriveMadison, WI 53717
RMA #____________
Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA num-ber.
10005594-02 Katana®3752 User’s Manual 2-9
Katana®3752 User’s Manual 10005594-022-10
(blank page)
10005594-02 Katana®3752
Section 3
Reset Logic
This chapter provides a system-level overview of the reset logic for the Katana®3752. It also describes the various reset sources.
GENERAL OVERVIEW
The Katana®3752 uses custom logic on a programmable logic device (PLD) to implement the reset circuitry. Fig. 3-1 on the following page shows an overview of the reset signals and logic.
User’s Manual 3-1
Reset Logic: General Overview
Figure 3-1: Katana®3752 Reset Diagram
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Katana®3752 User’s Manual 10005594-023-2
Reset Logic: Reset Sources
RESET SOURCES
The Katana®3752 circuit board can be reset from the following sources:
• Power-On Reset (POR) circuitry
• CompactPCI Reset
• Power Monitor Reset
• 750GL Processor Reset
• Remote IPMI Reset
• Front Panel Reset
• Watchdog Timer Reset
CompactPCI Reset EnableThe Katana®3752 has a configuration jumper at JP3 (see Fig. 2-4). When installed, this jumper enables the cPCI reset signal to drive a local PCI reset to all PCI-related devices. When the jumper is not installed (default condition), the Katana®3752 ignores the cPCI reset signal.
Power MonitorThe Katana®3752 has a power monitor circuit that detects low voltage conditions on any of the power supply sources. The circuit will hold the oscillators off and drive the power-on reset (POR) for as long as the low voltage condition exists.
750GL Processor ResetThe 750GL processor #1 on the Katana®3752 connects a MV64460 system controller gen-eral-purpose input/output (GPIO) signal to each of the other two 750GL processors. This signal can generate a hard reset on the corresponding processor complex. Fig. 3-2 shows the processor reset logic.
10005594-02 Katana®3752 User’s Manual 3-3
Reset Logic: Reset Sources
Figure 3-2: 750GL Reset Diagram
Ethernet Switch ResetIssuing a reset (other than a soft reset) to the 750GL processor #1 on the Katana®3752 causes the programmable logic device’s ETH_RST pin to drive the reset to the BCM5691 Ethernet switch controller and associated PHYs.
SolderedFlash
flash_rst
MV64460
sysrst
pci0_rst
pci1_rst
gt_wde
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hreset
sreset
trst
CPLD
cop_hreset
cop_sreset
cop_trst
pmc_rst
gt_wde
por_rst
aux_por_rst
osc_en gt_pci0
gt_pci1
start_lrst
cpu_hreset
cpu_sreset
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Katana®3752 User’s Manual 10005594-023-4
10005594-02 Katana®3752
Section 4
Processors
The Katana®3752 is designed to use three processor complexes. Each complex consists of a processor and a system controller/PCI bridge device (see “System Controllers” on page 5-1) with associated memory and input/output interfaces. The processor complexes are identi-cal, with the exception of processor #1, which is configured as the PCI host processor. Pro-cessor #1 also has a bank of socketed user flash memory.
PROCESSOR OVERVIEW
This chapter provides an overview of the processor logic on the Katana®3752. It includes information on the CPU, exception handling, and cache memory. The Katana®3752 utilizes the IBM PowerPC™ 750GL microprocessor, for more detailed information please refer to the following document: IBM PowerPC™ 750GX and 750GL RISC Microprocessor User’s Man-ual.
FeaturesThe following table outlines some of the key features for the 750GL CPU.
Table 4-1: Katana®3752 CPU Features
The following block diagram provides an overview of the IBM 750GL architecture.
Category: 750GL Key Features:Instruction Set 32-bit
CPU Speed (internal) Up to 800MHz
Data Bus 64-bit
Address Bus 32-bit
Four stage pipeline control Fetch, dispatch/decode, execute, complete/write back
Cache (L1) 32KB Instruction, 32KB Data, 8-way set associative
Cache (L2) 1MB, 4-way set associative, ECC checking
Execution Units Branch Processing, Dispatch, Decode, Load/Store, Fixed-point, Floating-point, System
Dual issue superscalar control
Maximum of two instructions completed plus one branch folded per cycle
Voltages Internal, 1.40V; input/output, 2.5V
User’s Manual 4-1
Processors: Processor Overview
Figure 4-1: 750GL Block Diagram
Physical Memory MapThe Katana®3752 monitor (see page 12-1) initializes the devices required to configure the memory map for the 750GL bus. The following figure shows the 750GL physical memory map (applicable to all three processors).
Completion
SystemUnit
Dispatch BHT/BTIC
Instruction FetchBranch Unit
Control Unit
32KB I-Cachewith Parity
LSU
FPRs
RenameBuffers
FPU
GPRs
RenameBuffers
FXU2FXU1
32KB D-Cachewith Parity
L2 Tagswith Parity
1MB
L2 Cachew/ECC
Enhanced 60xBIU
Katana®3752 User’s Manual 10005594-024-2
Processors: Processor Overview
Figure 4-2: 750GL Memory Map
8000,0000
B000,0000
CPLD Registers
FF80,0000
Boot Mirror
E800,0000
Flash/ROM Socket
FFFF,FFFF
32-BitHex Address:
F820,0000
F810,0000
MV64460 Registers
F800,0000
4004,0000
4000,0000 MV64460 SRAM
0000,0000
SDRAM(up to 1GB)
ReservedF824,0000
B400,0000
ReservedEC00,0000
ReservedF808,0000
ReservedF811,0000
FLASH(up to 64MB)
Reserved
Reserved
PCI Memory
PCI I/O
10005594-02 Katana®3752 User’s Manual 4-3
Processors: Processor Reset
This table summarizes the physical addresses for the 750GL on the Katana®3752 board and provides a reference to more detailed information:
Table 4-2: Katana®3752 Address Summary
PROCESSOR RESET
Circuitry on the Katana®3752 resets the processor and the board. Please refer to “Reset Logic” on page 3-1 for details.
PROCESSOR INITIALIZATION
Initially, the Katana®3752 powers up with specific values stored in the CPU registers. The initial power-up state of the Hardware Implementation Dependent register (HID0) and the Machine State register (MSR) are given in Table 4-3.
Table 4-3: CPU Internal Register Initialization
Hex Address (32-bit):
Access Mode: Description: See Page:
FF80,0000 R Boot Mirror page 4-3
F824,0000 — Reserved –
F820,0000 R/W PLD Registers page 6-1
F811,0000 — Reserved –
F810,0000 R/W MV64460 Registers page 5-1
F808,0000 — Reserved –
F800,0000 R/W Flash/ROM socket page 5-6
EC00,0000 — Reserved –
E800,0000 R/W Flash (up to 64MB) page 5-6
B400,0000 — Reserved –
B000,0000 R/W PCI I/O Space page 5-4
8000,0000 R/W PCI Memory Space page 5-4
4004,0000 — Reserved –
4000,0000 R/W MV64460 SRAM page 5-7
0000,0000 R/W SO-DIMM SDRAM (up to 1GB) page 5-7
Register: Default After Initialization (Hex): Notes:HID0 8000,0000 (icache and dcache off) Hardware Implementation Dependent
register. (See Section )8000,C000 (icache and dcache on)
MSR 0000,B032 Machine State register. (See Section )
Katana®3752 User’s Manual 10005594-024-4
Processors: Processor Initialization
Hardware Implementation Dependent 0 RegisterThe Hardware Implementation Dependent 0 Register (HID0) contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the Katana®3752. Please refer to the IBM PowerPC documentation for more detailed descrip-tions of the HIDx registers. The following register map summarizes HID0 for the 750GL CPU:
Register 4-1: 750GL Hardware Implementation Dependent (HID0)
EMCP: Enable Machine Check Pin. Initially enabled on the Katana®3752.
DBP: Disable 60x Bus address and data Parity generation (in conjunction with EBA/EBD).
EBA: Enable 60x Bus Address parity checking.
EBD: Enable 60x Bus Data parity checking.
PAR: Disable Precharge of ARTRY* and shared signals.
DOZE: Select low-power doze.
NAP: Select low-power nap.
SLEEP: Select low-power sleep.
DPM: Enable Dynamic Power Management.
NHR: Not Hard Reset (software use only).
ICE/DCE: Instruction and Data Cache Enables.
I/DLOCK: Instruction and Data Cache Lock bits.
ICFI/DCFI: Instruction and Data Cache Flash Invalidate bits.
SPD: DCache and ICache Speculative access disable.
IFEM: Enable M bit on bus for Instruction Fetches.
SGE: Store Gathering Enable.
DCFA: Data Cache Flush Assist.Force data cache to ignore invalid sets on miss replacement selection.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15EMCP DBP EBA EBD Reserved PAR DOZE NAP SLEEP DPM Reserved NHR
16 17 18 19 20 21 22 23 24 25 2627 28 29
30 31
ICE DCE ILOCK DLOCK ICFI DCFI SPD IFEM SGE DCFA BTIC R ABE BHT R NOOPTI
10005594-02 Katana®3752 User’s Manual 4-5
Processors: Processor Initialization
BTIC: Branch Target Instruction Cache enable.
ABE: Address Broadcast Enable (for cache ops, eieio, sync).
BHT: Branch History Table enable.
NOOPTI: No-op the dcbt/dcbst instructions.
Hardware Implementation Dependent 1 RegisterThe 750GL includes two phase-lock loops (PLL0 and PLL1), which allow the processor clock frequency to be changed to one of the PLL frequencies via software control. The HID1 regis-ter contains:
• Fields that specify the frequency range of each PLL
• The clock multiplier of each PLL
• External or internal control of PLL0
• A bit to choose which PLL is selected (source of the processor clock at any given time)
Register 4-2: 750GL Hardware Implementation Dependent (HID1)
PCE: PLL External Configuration bits (read only).
PRE: PLL External Range bits (read only).
PSTAT1: PLL Status (not supported in DD1.x).0 = PLL0 is the processor clock source1 = PLL1 is the processor clock source
ECLK: Enable the CLKOUT pin (set to 1).
ICLK: Select the Internal Clock to be output on the CLKOUT pin with the following decode:000 = Factory use only001 = PLL0 core clock (freq/2)010 = Factory use only011 = PLL1 core clock (freq/2)100 = Factory use only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15PCE PRE PSTAT1 ECLK ICLK Reserved PI0 PS
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31PC0 PR0 Res. PC1 PR1 Res.
Katana®3752 User’s Manual 10005594-024-6
Processors: Processor Initialization
101 = Core clock (freq/2)Other = Reserved(Note: These clock configuration bits reflect the state of the PLL_CFG[0:4] pins.)
PI0: PLL 0 Internal configuration select.0 = Select external configuration and range bits to control PLL01 = Select internal fields in HID1 to control PLL0
PS: PLL Select.0 = Select PLL0 as source for processor clock1 = Select PLL1 as source for processor clock
PC0: PLL0 Configuration bits.
PR0: PLL0 Range select bits.
PC1: PLL1 Configuration bits.
PRI: PLL1 Range bits.
Hardware Implementation Dependent 2 RegisterParity is implemented for the following arrays: I-Cache, I-Tag, D-Cache, D-Tag, and L2 Tag. Status bits are set when a parity error is detected and cleared when the HID2 register is written.
Register 4-3: 750GL Hardware Implementation Dependent (HID2)
mumd: Cache-inhibited MuM disable.0 = enable1 = disable MuM to CI space
nortea: Nortel TEA feature.
FICBP: Force I-Cache bad parity.
FITBP: Force I-Tag bad parity.
FDCBP: Force D-Cache bad parity.
FDTBP: Force D-Tag bad parity.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Reserved mumd Reserved norte
aReserved
1619 20 21 22 23 24 25 26 27 28 29 30 31
Reserved FICBP FITBP FDCBP FDTBP FL2TBP ICPS DCPS L2PS Res. ICPE DCPE L2PE
10005594-02 Katana®3752 User’s Manual 4-7
Processors: Exception Handling
FL2TBP: Force L2-Tag bad parity.
ICPS: L1 I-Cache/I-Tag Parity Error Status/Mask.
DCPS: L1 D-Cache/D-Tag Parity Error Status/Mask.
L2PS: L2 Tag Parity Error Status/Mask.
ICPE: L1 I-Cache/I-Tag Parity checking Enable.
DCPE: L1 D-Cache/D-Tag Parity checking Enable.
L2PE: L2 Tag Parity checking Enable.
EXCEPTION HANDLING
Each CPU exception type transfers control to a different address in the vector table. The vector table normally occupies the first 2000 bytes of RAM (with a base address of 0000,000016) or ROM (with a base address of F800,000016). An unassigned vector position may be used to point to an error routine or for code or data storage. Table 4-4 lists the exceptions recognized by the processor from the lowest to highest priority.
Table 4-4: 750GL Exception Priorities
Exception:Vector Address Hex Offset: Notes:
Trace 00D00 Lowest priority. Due to MSR[SE]=1 or MSR[BE]=1 for branches.
Data Storage (DSI) 00300 DABR address match.
TLB page protection violation.
Any access except cache operations to T=1 (bit 5 of DSISR) or T=0->T=1 crossing.
BAT page protection violation.
Due to eciwx, ecowx with EAR(E)=0 (bit 11 of DSIDSR).
Alignment 00600 Any alignment exception condition.
Program (PI) 00700 Due to a floating-point enabled exception.
Due to an illegal instruction, a privileged instruction, or a trap.
Floating Point Unavailable (FPA) 00800 Any floating-point unavailable exception.
System call (SC) 00C00 Execution of system call (sc) instruction.
Instruction Address Breakpoint (IABR)
01300 Any IABR exception condition.
Instruction Storage (ISI) 00400 Instruction fetch exceptions.
Thermal Management (TMI) 01700 Junction temperature exceeds the threshold specified in THRM1 or THRM2, and MSR[EE]=1.
Katana®3752 User’s Manual 10005594-024-8
Processors: Exception Processing
EXCEPTION PROCESSING
When an exception occurs, the address saved in Machine Status Save/Restore register 0 (SRR0) helps determine where instruction processing should resume when the exception handler returns control to the interrupted process. Machine Status Save/Restore register 1 (SRR1) is used to save machine status on exceptions and to restore those values when an rfi instruction is executed.
When an exception is taken, the 750GL controller uses SRR0 and SRR1 to save the contents of the Machine State register (MSR) for the current context and to identify where instruc-tion execution resumes after the exception is handled.
The Machine State register (MSR) configures the state of the 750GL CPU. On initial power-up of the Katana®3752, most of the MSR bits are cleared. Please refer to the IBM PowerPC documentation for more detailed descriptions of the individual bit fields.
Register 4-4: CPU Machine State (MSR)
Decrementer (DEC) 00900 Decrementer passed through zero.
Performance Monitor (PMI) 00F00 Programmer-specified.
External (EI) 00500 INT* (Refer to Section for description of interrupt sources and interrupt handling.)
System Management (SMI) 01400 MSR[EE]=1 and SMI* is asserted.
Machine check 00200 Assertion of TEA*, 60x Address Parity Error, 60x Data Parity Error, L2 ECC Double Bit Error, MCP*, L2-Tag Parity Error, D-Tag Parity Error, I-Tag Parity Error, I-Cache Parity Error, D-Cache Parity Error, or locked L2 snoop hit.
System reset 00100 Soft reset (SRESET*).
Highest priority. Hard reset (HRESET* and POR).
– 00000 Reserved.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Reserved POW Res. ILE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31EE PR FP ME FE0 SE BE FE1 Res. IP IR DR Res. PM RI LE
Exception:Vector Address Hex Offset: Notes: (continued)
10005594-02 Katana®3752 User’s Manual 4-9
Processors: Exception Processing
POW: Power Management enable. Setting this bit enables the programmable power manage-ment modes: nap, doze, or sleep. These modes are selected in the HID0 register. This bit has no effect on dynamic power management.0= Power management disabled (normal operation mode)1= Power management enabled (reduced power mode)
ILE: Exception Little-Endian mode.
EE: External interrupt Enable. This bit allows the processor to take an external interrupt, system management interrupt, or decrementer interrupt.0= External interrupts and decrementer exception conditions delayed.1= External interrupt or decrementer exception enabled.
PR: Privilege level. 0= User- and supervisor-level instructions are executed1= Only user-level instructions are executed
FP: Floating-Point available. This bit is set on initial power-up.0= Prevents floating-point instructions dispatch (loads, stores, moves).1= Executes floating-point instructions.
ME: Machine check Enable. 0= Machine check exceptions disabled.1= Machine check exceptions enabled.
FE0/FE1: These bits define the Floating-point Exception mode.
SE: Single-step trace Enable.0= Executes instructions normally.1= Single-step trace exception generated.
BE: Branch trace Enable.0= Executes instructions normally.1= Branch type trace exception generated.
IP: Exception Prefix. Initially, this bit is cleared so that the exception vector table is placed at the base of RAM (0000,000016). When this bit is set, the vector table is placed at the base of ROM (FFF0,000016).
FE0: FE1: FP Exception Mode:0 0 Disabled
0 1 Imprecise nonrecoverable
1 0 Imprecise recoverable
1 1 Precise
Katana®3752 User’s Manual 10005594-024-10
Processors: Cache Memory
IR/DR: Instruction and Data address translation enables.0= Address translation disabled.1= Address translation enabled.
PM: Marks a process for the Performance Monitor.0= Process is not marked.1= Process is marked.
RI: Recoverable exception enable for system reset and machine check. This feature is enabled on initial power-up.0= Exception is not recoverable.1= Exception is recoverable.
LE: Little-endian mode enable.0= Big-endian mode (default).1= Little-endian mode.
CACHE MEMORY
The 750GL processor provides both level 1 (L1) and level 2 (L2) cache memory. This section describes this memory.
L1 CacheThe 750GL processor has separate, on-chip, 32-kilobyte, Level 1 (L1) instruction and data caches with eight-way, set-associative translation look aside buffers (TLBs). The CPU sup-ports the modified/exclusive/invalid (MEI) cache coherency protocol. The data bus width for bus interface unit (BIU) accesses of the L1 data cache array is 256 bits. This enables cache line data burst to be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. The 750GL also employs pseudo-least recently used (PLRU) replacement algorithms for enhanced performance.
L2 CacheThe internal L2 cache is four-way set associative. Each way contains 4096 blocks, and each block consists of two 32-byte sectors. It can be configured with any combination of individ-ual ways locked. It can lock half or all of the ways, or it can unlock them all. When unlocked, the L2 cache is four-way set associative. Each way contains 262144 blocks, and each block consists of two 32-byte sectors.
The L2 cache can be configured to contain instructions or data only. Array read and write operations execute in one processor cycle—writes are 64 bits wide and reads are 256 bits wide. The L2 has a 1MB SRAM which includes an 8-bit ECC for every 64-bit word in memory that can be used to correct most single bit errors and detect multiple bit errors.
10005594-02 Katana®3752 User’s Manual 4-11
Processors: Cache Memory
The L2 cache control register (L2CR) configures and enables the L2 cache. The L2CR is read/write and contents are cleared during power-on reset.
Register 4-5: L2 Cache Control Register (L2CR)
L2E: L2 Enable.Enables and disables the operation of the L2 cache, starting with the next transaction.
L2CE: L2 double bit error Checkstop Enable.
L2DO: L2 Data-Only.Setting this bit inhibits the caching of instructions in the L2 cache. All accesses from the L2 instruction cache are treated as cache-inhibited by the L2 cache.
L2I: L2 global Invalidate.Setting this bit invalidates the L2 cache globally by clearing the L2 status bits.
L2WT: L2 Write-Through.Setting this bit selects write-through mode (rather than default copy-back mode) so all writes to the L2 cache also write through to the 60x bus.
L2TS: L2 Test Support.Setting this bit causes cache block pushes from the L1 data cache that result from dcbf and dcbst instructions to be written only into the L2 cache and marked valid. Also causes single-beat store operations that miss in the L2 cache to be discarded.
L2L0CKLO: L2 cache locking: lock ways 0 and 1.
L2LOCKHI: L2 cache locking: lock ways 2 and 3.
SHEE: Snoop Hit in locked line Error Enable.
SHERR: Snoop Hit in locked line Error.
L2LOCK0: Lock way 0 if either bit 20 or bit 24 is set to one.
L2LOCK1: Lock way 1 if either bit 20 or bit 25 is set to one.
L2LOCK2: Lock way 2 if either bit 21 or bit 26 is set to one.
L2LOCK3: Lock way 3 if either bit 21 or bit 27 is set to one.
0 1 2 8 9 10 11 12 13 14 15L2E L2CE Reserved L2DO L2I Res. L2WT L2TS Reserved
16 19 20 21 22 23 24 25 26 27 28 29 30 31Reserved L2
L0CKLO
L2 LOCK
HI
SHEE SHERR L2LOCK0
L2LOCK1
L2LOCK2
L2LOCK3
L2IO Reserved L2IP
Katana®3752 User’s Manual 10005594-024-12
Processors: JTAG/COP Header Access
L2IO: L2 Instruction-Only.Setting this bit inhibits data caching in the L2 cache.
L2IP: L2 global Invalidate in Progress.This read only bit indicates whether an L2 global invalidate is occurring.
JTAG/COP HEADER ACCESS
The Katana®3752 provides a dedicated test access port (TAP) for user access to the three 750GL CPUs. The TAP is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The internal common-on-chip (COP) debug processor allows access to internal scan chains for debugging purposes and can also be used as a serial connection to the core for emulator support.
Emerson supplies an optional break-out-board (#10005840-00) with three headers for eas-ier access to each processor’s JTAG port. The break-out-board simply plugs on to the P5 header on the top side of the Katana®3752 circuit board (refer to Fig. 4-3 for location).
Connectors P1—P3 (on the break-out-board) and connector P5 on the Katana®3752 all have the same pinouts, as described in the following table.
Table 4-5: 750GL JTAG/COP Interface Pin Assignments, P1—P3, P5
Pin: Signal: I/O: Description:1 TDO1 Output Test Data Out (TDO) for CPU #1
TDO is a standard JTAG signal. This is the scan path output, driven by the falling edge of the TCK signal and sampled on the rising edge of TCK.
2 TRST1 Input Test Reset (TRST) for CPU #1TRST is a standard JTAG signal. When this signal is active (low), the JTAG logic is reset and inactive, allowing normal operation of the 750GL.
3 TDI1 Input Test Data In (TDI) for CPU #1TDI is a standard JTAG signal and is the input data for the scan path. TDI is driven by the JTAG controller on the falling edge of TCK and sampled on the rising edge of TCK by the JTAG slave.
4 GND — Ground
5 TCK1 Input Test Clock (TCK) for CPU #1TCK is a standard JTAG signal and is the clock for the JTAG machine. JTAG signals are driven according to the TCK falling edge and sampled over its rising edge.
6 GND — Ground
10005594-02 Katana®3752 User’s Manual 4-13
Processors: JTAG/COP Header Access
7 TMS1 Input Test Mode Select (TMS) for CPU #1TMS is a standard JTAG signal. This signal, along with TCK, controls the TAP controller state machine allowing movement between its different states. When high, it causes a change in the TAP controller state on the rising edge of TMS. When low, the TAP controller state machine remains in its current state.
8 CKSTP1 Output Checkstop (CKSTP) for CPU #1CKSTP indicates a halted condition for the CPU.
9 SRST1 Input Soft Reset (SRST) for CPU #1SRST is required to enable the debug station to either generate a Soft Reset sequence or observe the 750GL taking a Soft Reset sequence.
10 PWR1 Output Power (PWR) for CPU #1This indicates to the debug st ation the voltage at which the target processor is powered.
11 HRST1 Input Hard Reset (HRST) for CPU #1HRST is required to enable the debug station to either generate a Hard Reset sequence or observe the 750GL taking a Hard Reset sequence.
12 HRST2 Input HRST for CPU #2
13 TDO2 Output TDO for CPU #2
14 TRST2 Input TRST for CPU #2
15 TDI2 Input TDI for CPU #2
16 GND — Ground
17 TCK2 Input TCK for CPU #2
18 GND — Ground
19 TMS2 Input TMS for CPU #2
20 CKSTP2 Output CKSTP for CPU #2
21 SRST3 Input SRST for CPU #3
22 SRST2 Input SRST for CPU #2
23 HRST3 Input HRST for CPU #3
24 PWR2 Output PWR for CPU #2
25 TDO3 Output TDO for CPU #3
26 TRST3 Input TRST for CPU #3
27 TDI3 Input TDI for CPU #3
28 GND — Ground
29 TCK3 Input TCK for CPU #3
30 GND — Ground
31 TMS3 Input TMS for CPU #3
32 CKSTP3 Output CKSTP for CPU #3
Pin: Signal: I/O: Description: (continued)
Katana®3752 User’s Manual 10005594-024-14
Processors: JTAG/COP Header Access
Figure 4-3: JTAG/COP Break-Out-Board Location
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10005594-02 Katana®3752 User’s Manual 4-15
Processors: Console Serial Ports
CONSOLE SERIAL PORTS
Each of the three processor complexes on the Katana®3752 has an asynchronous console serial port on the front panel. These ports operate at EIA-232 signal levels, but do not pro-vide any handshaking functionality. The connectors for the console ports are micro-DB9 connectors, with the following pin assignments.
Table 4-6: Serial Console Port Pin Assignments, (P2, P3, P4)
The standard Emerson console cable (#10007665-00) is cross-pinned, as shown in the fig-ure below. A straight-through 9-pin cable (#10007664-00) also is available.
Figure 4-4: Standard Console Cable Wiring, #10007665-00
Note: Cable part numbers are subject to change. Please check with Emerson before ordering replacement cables.
Pin: Signal: Pin: Signal:1 no connection 6 no connection
2 RXD (Data In) 7 no connection
3 TXD (Data Out) 8 no connection
4 no connection 9 no connection
5 ground
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Katana®3752 User’s Manual 10005594-024-16
10005594-02 Katana®3752
Section 5
System Controllers
The Katana®3752 has three processor complexes. Each complex consists of a processor (see “Processors” on page 4-1) and a system controller/PCI bridge device with associated memory and input/output interfaces. This chapter describes the Marvell MV64460 system controller/PCI bridge device implementation.
OVERVIEW
The Discovery™ III PowerPC® System Controller (MV64460) from Marvell is an integrated system controller with a PCI interface and communication ports for high performance con-trol applications. The MV64460 has a five bus architecture:
• A 64-bit interface to the CPU bus
• A 64-bit interface to DDR SDRAM
• A 32-bit interface to devices
• A 64-bit PCI interface (PCI1)
Note: Proprietary information on the Marvell MV64460 device is not available in this user’s manual. Please refer to the Marvell web site at http://www.marvell.com for available documentation.
The five buses function independently which enables simultaneous operation of the CPU bus, PCI device, and access to memory.
The MV64460 communications unit includes the following:
• Three Gigabit Ethernet ports (For the Katana®3752 implementation, processor complex #1 has two ports, and processor complexes #2 and #3 each have one port.)
• Two multi-protocol serial controllers (MPSC)(The Katana®3752 uses one MPSC.)
• Ten serial DMAs (SDMA)
• Two baud rate generators (BRG)
• I2C interface
The crossbar fabric, or central routing unit, controls the data path routing. It contains pro-grammable arbitration mechanisms to optimize device performance.
User’s Manual 5-1
System Controllers: CPU Interface
Figure 5-1: MV64460 Block Diagram
CPU INTERFACE
CPU interface features include:
• 32-bit address and 64-bit data bus
• 60x bus
• Up to 200 MHz CPU bus frequency
• CPU address remapping to PCI
• Support for access, write, and cache protection to a configurable address range
• Support for up to 16 pipelined address transactions
SDRAM CONTROLLER
The MV64460 supports double data rate (DDR) synchronous dynamic random access memory (SDRAM). The SDRAM controller supports up to four banks of SDRAMs. It has a 16-bit address bus (M_DA[13:0] and M_BA[1:0]) and a 72-bit data bus (M_DQ[63:0] and M_CB7[7:0]). The SDRAM controller supports both registered and unbuffered SDRAM devices. Other features include:
• 64-bit wide (+ 8-bit ECC) SDRAM interface
• Up to 200-MHz SDRAM frequency
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Katana®3752 User’s Manual 10005594-025-2
System Controllers: Device Controller Interface
• Support for DDR SDRAM devices
• Up to two gigabytes address space per DRAM bank
• Supports both physical and virtual bank interleaving
The MV64460 has a number of SDRAM registers. Refer to the Marvell web site for available documentation.
DEVICE CONTROLLER INTERFACE
The device controller supports up to five banks of devices. Each bank’s supported memory space can be programmed separately in one megabyte quantities up to 512 megabytes of address space with a total device space of 2.5 gigabytes. Other features include:
• Dedicated 32-bit multiplexed address/data bus (separate from the SDRAM bus)
• Up to 133 MHz bus frequency
• Five chip selects, each with programmable timing
• Use as a high bandwidth interface to user specific logic
• Supports many types of standard memory and I/O devices
Each bank has its own parameter register and can be programmed to 8, 16, or 32-bits wide. The device interface consists of 128 bytes of write buffer and 128 bytes of read buffer.
INTERNAL (IDMA) CONTROLLER
Each of the four DMA engines can move data between any source and any destination, such as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by moving large amounts of data without significant CPU intervention. Read and write are handled independently and concurrently.
TIMER/COUNTERS
Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a counter. Each timer/counter increments with every Tclk rising edge. In counter mode, the counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the timer counts down, issues an interrupt on terminal count, reloads itself to the programmed value, and continues to count. Reads from the counter or timer are completed directly from the counter, and writes are to the timer/counter register.
10005594-02 Katana®3752 User’s Manual 5-3
System Controllers: PCI Interface
PCI INTERFACE
The MV64460 supports two 64-bit PCI interfaces, which comply with the PCI Local Bus Spec-ification revision 2.3. Only PCI1 is functional on the Katana®3752. Other features include:
• Supports P2P memory, I/O, and configuration transactions
• PCI bus speed up to 66 MHz with zero wait states
• Operates either synchronous or asynchronous to CPU clock; at slower, equal, or faster clock frequency
• 32/64-bit PCI master and target operations
PCI Configuration SpaceThe PCI slave supports Type 00 configuration space header as defined in the PCI specifica-tion. The MV64460 is a multi-function device and the header is implemented in all eight functions. The PCI interface implements the configuration header and this space is accessi-ble from the CPU or PCI bus.
PCI Device and Vendor ID AssignmentThe Katana®3752 has been assigned the following PCI identification numbers.
Table 5-1: PCI Device and Vendor IDs
PCI Read/WriteThe MV64460 becomes a PCI bus master when the CPU, IDMA, gigabit Ethernet switch, or MPSC SDMAs initiate a bus cycle to a PCI device. Conventional PCI mode allows unlimited DMA bursts between PCI and memory. It supports all PCI commands including 64-bit addressing using dual access cycles (DAC).
The MV64460 acts as a target when a PCI device initiates a memory access (or an I/O access in the case of internal registers, or a P2P transaction). It responds to all memory read and write accesses, including DAC, and to all configuration and I/O cycles in the case of internal registers. Its internal buffers allow unlimited burst reads and writes, and they can support up to four pending delayed reads in conventional PCI mode.
Vendor ID: Device ID: Description:0x1223 0x0041 Reported by the PCI bridge for processor #1
0x1223 0x0042 Reported by the PCI bridge for processor #2
0x1223 0x0043 Reported by the PCI bridge for processor #3
Katana®3752 User’s Manual 10005594-025-4
System Controllers: Doorbell Registers
PCI Interface RegistersPCI0 and PCI1 contain the same set of internal registers, but are located at different offsets. A CPU access to the MV64460 PCIx Configuration register is performed via the PCIx Config-uration Address and Data registers. Only PCI1 is functional on the Katana®3752.
All PCI configuration registers are located at their standard offset in the configuration header, as defined in the PCI specification, when accessed from their corresponding PCI bus. For example, if a master on PCI1 performs a PCI configuration cycle on PCI’s Status and Command register, the register is located at 0x004.
The Katana®3752 may generate interrupts to other PCI devices by accessing doorbell-type interrupt-generating registers or address ranges within their PCI bridges. The board will respond to interrupts caused by another PCI device when it accesses a programmable range of local memory, as provided by the MV64460 memory controller. In addition, it may monitor the state of the PCI bus INTA*—INTD* signals, routed through the PLD to the mem-ory controller. The MV64460 contains registers that control the masking, unmasking, and priority of the PMC interrupts as inputs to the processor.
DOORBELL REGISTERS
The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts on both the PCI and CPU buses. There are two types of doorbell registers:
Outbound: These are set by the MV64460’s local CPU to request an interrupt service on the PCI bus.
Inbound: These are set by an external PCI agent to request interrupt service from the local CPU.
Outbound DoorbellsThe local CPU generates an interrupt request to the PCI bus by setting bits in the Outbound Doorbell register (ODR). The interrupt may be masked in the Outbound Interrupt Mask reg-ister (OIMR), but that does not prevent the bit from being set in the ODR. The ODR is located at PCI_0 offset 0x1C2C.
The CPU or the PCI interface can set the ODR bits. this allows for passing interrupt requests between CPU and PCI interfaces.
Inbound DoorbellsThe PCI bus generates an interrupt request to the local CPU by setting bits in the Inbound Doorbell register (IDR). The interrupt may be masked in the Inbound Interrupt Mask regis-ter (IIMR), but masking the interrupt does not prevent the bit from being set in the IDR. The IDR is located at PCI_0 offset 0x1C20.
10005594-02 Katana®3752 User’s Manual 5-5
System Controllers: Watchdog Timer
The interrupt request triggered from the PCI bus can be targeted to the CPU or to the PCI interface, depending on the software setting of the interrupt mask registers.
WATCHDOG TIMER
The 32-bit count down watchdog timer generates a nonmaskable interrupt or resets the system in the event of unpredictable software behavior. After the watchdog is enabled, it is a free-running counter that requires periodic servicing to prevent its expiration. After reset, the watchdog is disabled.
RESET
Circuitry on the Katana®3752 resets the entire board if the voltages fall out of tolerance or if the optional on-board reset switch is activated. Please refer to “Reset Logic” on page 3-1 for additional information.
ON-CARD MEMORY
The Katana®3752 has various types of on-card memory to support the MV64460 system controller and the 750GL processor. It has user Flash, SDRAM for data storage, and several serial EEPROMs for non-volatile memory storage. The following subsections describe these memory devices.
User FlashThe Katana®3752 user flash memory interface supports two, soldered, 16-bit devices of 16 or 32 megabytes for each processor complex. This memory is arranged in one bank to pro-vide a maximum of 64 megabytes of contiguous memory. The MV64460 controls this memory, located at E800,000016 on the processor 60x bus. Each 750GL processor can boot from its soldered flash memory.
In addition to the soldered flash memory, the Katana®3752 also supports a single flash memory device of up to 512 kilobytes for the 750GL processor #1 complex. This memory device is socketed and located at F800,000016 on the processor 60x bus. The 750GL pro-cessor #1 can write to and boot from this memory.
By default, the MV64460 system controllers enable a slave window for the soldered flash on processors #2 and #3, so that processor #1 can read/write to/from this memory across the PCI interface upon initial power-up or in the event the flash becomes corrupted. Also by default, processor #1 boots from the soldered flash (see Jumper JP1 location on page 2-5).
Katana®3752 User’s Manual 10005594-025-6
System Controllers: I2C Interface
SDRAMThe Katana®3752 supports up to one gigabyte of 72-bit wide synchronous dynamic ran-dom access memory (SDRAM) for each 750GL processor complex. The SDRAM interface implements eight additional bits to allow for error correcting code (ECC).
The SDRAM is in the form of a small-outline, dual in-line memory module (SO-DIMM) device. A serial EEPROM on the SO-DIMM provides configuration information, accessible via the I2C interface at address AE16. The SDRAM occupies physical addresses from 0000,000016 to 7FFF,FFFF16 on the processor 60x bus. The MV64460 controls the SDRAM and supports a double data rate (DDR) interface that allows for transfer speeds of up to 400MHz.
EEPROMsEach MV64460 uses a 64-kilobyte serial EEPROM at hex location A416 on the I2C bus to store configuration data. Each MV64460 also has a second, 64-kilobyte, serial EEPROM at hex location A616 on the I2C bus to provide additional non-volatile memory space, allo-cated as follows.
Table 5-2: NVRAM Allocation
By default, Emerson does not provide any code in the EEPROM at A416. If you do use this memory, be aware that the Emerson monitor initialization may overwrite values set by your code.
I2C INTERFACE
Each MV64460 has a built-in inter-integrated circuit (I2C) interface that supports master and slave I2C devices. The following devices connect to the I2C bus:
• SO-DIMM SDRAM
• two 64-kilobyte serial EEPROMs
• real-time clock (RTC) device
• Zircon PM IPMI controller and associated devices
Hex Byte Offset: Description: Window Size:1E00—1FFF Reserved 512 bytes
1DDC—1DFF BootVerify Parameters 36 bytes
1DD8—1DDB POST Diagnostic Results 4 bytes
1800—1DD7 Monitor Configuration Parameters 1496 bytes
1600—17FF VxWorks 512 bytes
0000—15FF User-Defined 5632 bytes
10005594-02 Katana®3752 User’s Manual 5-7
System Controllers: I2C Interface
Figure 5-2: I2C Interface Diagram
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Katana®3752 User’s Manual 10005594-025-8
System Controllers: GPIO Signal Definitions
GPIO SIGNAL DEFINITIONS
Each of the three MV64460 system controllers on the Katana®3752 has 32 general-pur-pose input output (GPIO) pins that are used for various purposes. The following table describes the GPIO pin assignments for processor #1.
Table 5-3: GPIO Signals Definitions for Processor #1
Pin: Direction: Description:0 output console port transmit data
1 input console port receive data
2 output processor #2 PCI grant
3 input processor #2 PCI request
4 output processor #3 PCI grant
5 input processor #3 PCI request
6 output BCM5691 PCI grant
7 input BCM5691 #3 PCI request
8 input PCI INTA (BCM5691)
9 input PCI INTB (processor #2)
10 input PCI INTC (processor #3)
11 output INIT_ACT, driven to indicate the bridge is loading from serial ROM
12 input hot swap interrupt, active low indicates a latch state change
13 output driven low to turn off front panel LED once processor section is up and running
14 output driven high to reset processor #3
15 output driven high to reset processor #2
16 output watchdog NMI
17 output watchdog expired
18 – reserved
19 output watchdog expired to IPMI controller
20 output clear out watchdog event to IPMI controller
21 output driven to processor #2 and processor #3 indicating and EVENT has occurred
22 input EREADY, driven high by processor #2 and processor #3 when they are ready for configuration.
23 input IPMI Timerout, driven by IPMI microcontroller when there is a time-out condition
24 output POST indicator to IPMI controller, driven low to indicate sucessful POST
25 output driven high to put the IPMI microcontroller in reset
26 input driven high to flash the front panel LED
27 input GA0
28 input GA1
10005594-02 Katana®3752 User’s Manual 5-9
System Controllers: GPIO Signal Definitions
The GPIO pin assignments for processor #2 and processor #3 are as follows.
Table 5-4: GPIO Signals Definitions for Processors #2 and #3
29 input GA2
30 input GA3
31 input GA4
Pin: Direction: Description:0 output console port transmit data
1 input console port receive data
2 input input from processor #1 indicating an EVENT condition
3—10 input unused
11 output INIT_ACT, driven to indicate the bridge is loading from serial ROM
12 input input from CPLD, used as synchronous versions of PERR and SERR
13 output driven low to turn off front panel led once processor section is up and running
14 input unused
15 — reserved
16 output watchdog NMI
17 output watchdog expired
18 input low = processor #2, high = processor #3
19 output watchdog expired, active low
20 input driven low to clear latched watchdog expiration event
21—23 input unused
24 output POST indicator to IPMI controller, driven low to indicate successful POST
25 input unused
26 input Input from CPLD, can be used at WDNMI input
27 input GA0
28 input GA1
29 input GA2
30 input GA3
31 input GA4
Pin: Direction: Description: (continued)
Katana®3752 User’s Manual 10005594-025-10
10005594-02 Katana®3752
Section 6
Device Bus PLDs
Each of the three processor complexes on the Katana®3752 has a programmable logic device (PLD) that provides control logic for the 750GL device bus. These PLDs implement various registers relating to reset control, interrupt handling, product identification, PCI enumeration, and board configuration. This chapter describes the device bus PLD registers.
RESET REGISTERS
The device bus PLD routes and distributes the reset signals. Three registers support this functionality. The read-only Reset Event register at hex location F820,000016 indicates the reason for the last reset as follows.
Register 6-1: Reset Event
InitAct: Initialization Active:Set to 1 when the MV64460 InitAct pin does not go inactive after reset
WD: Watchdog:Set to 1 when a reset was caused by the expiration of the MV64460 watchdog timer
COPS: Soft Reset:Set to 1 when a COP header soft reset (SRESET) has occurred
COPH: Hard Reset:Set to 1 when a COP header hard reset (HRESET) has occurred
CPCI: CPCI:Set to 1 when a cPCI reset (RST* signal) has occurred
FP: Front Panel:Set to 1 when the front panel switch caused a reset
7 6 5 4 3 2 1 0InitAct Reserve
dWD COPS COPH Reserve
dCPCI FP
User’s Manual 6-1
Device Bus PLDs: Reset Registers
The Reset Command register at hex location F820,100016 forces one of several types of resets, as shown below. After a reset sequence is initiated by writing a one to a valid bit, the bit is automatically cleared.
Register 6-2: Reset Event
Note: For bits 5—0, only set one bit at a time when writing to this register.
SCL: Direct control for I2C clock signal:1=Tri-states the PLD0=Drives logic low
SDA: Direct control for I2C data signal:1=Tri-states the PLD0=Drives logic low
I2C: I2C initialization:1=Causes the I2C bus to be initialized into a known state0=No I2C initialization
FR: Flash Reset command:1=Causes Flash to be reset0=No Flash reset (default)
HR: Hard Reset command:1=Causes a hard reset on board0=No hard reset (default)
The Reset Out Enable register at hex location F820,E00016 only applies to processor com-plex #1. This register determines the functionality of the BCM5221 PHY reset signal and allows access to the IPMI interface, as follows.
Register 6-3: Reset Out Enable
PORT_SEL: IPMI Port Selection:Allow processor complex #1 access to the IPMI controller and temperature sensors1=Disabled (default)0=Enabled
7 6 5 4 3 2 1 0SCL SDA Reserve
dI2C FR Reserved HR
7 6 5 4 3 2 1 0PORT_SEL Reserve
dWD Reserve
dCOPH Reserve
dPCI FP
Katana®3752 User’s Manual 10005594-026-2
Device Bus PLDs: Interrupt Registers
WD: WatchDog:PCI reset driven when on-board reset is caused by a time-out of the WatchDog timer1=Enabled0=Disabled (default)
COPH: Hard RESET:PCI reset driven when reset is caused by a COP HRESET1=Enabled0=Disabled (default)
PCI: PCI reset driven when on-board reset is caused by the assertion of PCI reset (PCI RESET)1=Enabled0=Disabled (default)
FP: Front Panel:PCI reset driven when on-board reset is caused by the front panel push button1=Enabled (default)0=Disabled
INTERRUPT REGISTERS
The system error and parity error interrupts from the PCI bus route to the device bus PLD. These signals are active low, and the falling edge is detected asynchronously to the bus clock. The following signals route to the appropriate MV64460 MPP pin:
• PERR and SERR have two loads. These are combined in the PLD to a single interrupt and route to MPP12.
• The non-maskable watchdog timer routes to MPP26.
The Interrupt Enable register at hex location F820,200016 contains two enable bits, as fol-lows.
Register 6-4: Interrupt Enable
SREN: PCI SERR Enable interrupt routed from PCI SERR to MV64460:1=Enabled to generate an interrupt0=Disabled (default)
PREN: PCI PERR Enable interrupt routed from PCI PERR to MV64460:1=Enabled to generate an interrupt0=Disabled (default)
7 6 5 4 3 2 1 0Reserved SREN PREN
10005594-02 Katana®3752 User’s Manual 6-3
Device Bus PLDs: Product Identification
The Interrupt Pending register at hex location F820,300016 allows software to determine which source has caused an interrupt, as follows.
Register 6-5: Interrupt Pending
SERR: PCI SERR Enable1=SERR has occurred and is enabled (IER SR1EN=1).0=No SERR (default).
PERR: PCI PERR Enable1=PERR has occurred and is enabled (IER PR1EN=1).0=No PERR (default).
PRODUCT IDENTIFICATION
The read-only Product ID register at hex location F820,400016 identifies the Katana®3752.
Register 6-6: Product ID
PIR: Product Identification register:0316=Katana®3752
PCI ENUMERATION
The Katana®3752 provides a register for status and control of enumeration. In a Monarch system, the EReady register at hex location F820,500016 is readable to indicate that other boards in the system are ready for enumeration. In a non-Monarch system, the register is writeable to indicate the Katana®3752 is ready for enumeration.
Register 6-7: EReady
ERdy: Monarch (read):1=PCI devices are ready to be enumerated0=PCI devices not ready to be enumerated
7 6 5 4 3 2 1 0Reserved SERR PERR
7 6 5 4 3 2 1 0PIR
7 6 5 4 3 2 1 0R ERdy
Katana®3752 User’s Manual 10005594-026-4
Device Bus PLDs: Revision Registers
Non-Monarch (write): (default for non-Monarch)1=PMC is ready to be enumerated0=PMC is not ready to be enumerated
REVISION REGISTERS
The Katana®3752 device bus PLD provides two read only registers to track hardware and PLD revisions. The Hardware Version register at hex location F820,700016 provides a hard-coded tracking number for the hardware.
Register 6-8: Hardware Version
HVR: Hardware version number:This is changed with every major PCB version. Version starts at 0016.
The PLD Version register at hex location F820,800016 provides a hard-coded tracking num-ber for the PLD code.
Register 6-9: PLD Version
PVR: Code version number:This is hard coded in the PLD and changed with every major code change. Version starts at 0016.
BOARD CONFIGURATION REGISTERS
Three byte-wide, read-only Board Configuration registers allow the monitor software to easily determine specific hardware configurations, including Monarch status, flash size, and system clock speed.
The Board Configuration 3 register at hex location F820,C00016 indicates if the module is a Monarch.
Register 6-10: Board Configuration 3.
7 6 5 4 3 2 1 0HVR
7 6 5 4 3 2 1 0PVR
7 6 5 4 3 2 1 0Reserved Mon Reserved
10005594-02 Katana®3752 User’s Manual 6-5
Device Bus PLDs: Hot Swap Register
Mon: Processor PMC Monarch indication:1=PMC is Monarch0=PMC is non-Monarch
The Board Configuration 1 register at hex location F820,A00016 provides status informa-tion about the flash memory, as follows.
Register 6-11: Board Configuration 1
Boot Socket: Boot from socketed flash or from soldered flash:1=Boot from socketed flash0=Boot from soldered flash
Flash Bank: Number of flash banks:1=Two banks0=One bank
Flash Size: Flash bank size:11=128 MB10=64 MB01=32 MB00=16 MB
The Board Configuration 0 register at hex location F820,900016 indicates the system clock speed, as follows.
Register 6-12: Board Configuration 0
SysCLK: System clock speed:11=133 MHz10=166 MHz01=100 MHz00=200 MHz
HOT SWAP REGISTER
The Hot Swap register (HSR) at hex location F820,B00016 indicates the state of the ejector latch and extraction interrupt. It also allows for control of the Hot Swap LED.
7 6 5 4 3 2 1 0Reserved Boot
SocketFlashBank
Flash Size
7 6 5 4 3 2 1 0SysCLK Reserved
Katana®3752 User’s Manual 10005594-026-6
Device Bus PLDs: Hot Swap Register
Register 6-13: Hot Swap
STATE: Indicates ejector latch state:1=open0=closed
INT: State of interrupt indicating extraction event (i.e., latch state changed from closed to open):1=interrupt pending0=interrupt cleared
CLR: Writing a one to this bit clears out a pending extraction event interrupt
LED: Controls the blue Hot Swap LED:1=turns on LED0=turns off LED
7 6 5 4 3 2 1 0STATE INT CLR LED Reserved
10005594-02 Katana®3752 User’s Manual 6-7
Katana®3752 User’s Manual 10005594-026-8
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10005594-02 Katana®3752
Section 7
Real-Time Clock
Each processor complex on the Katana®3752 has a standard real-time clock (RTC), consist-ing of an M41T00 device from STMicroelectronics. The M41T00 has an integrated year-2000-compatible RTC, power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function. It is powered from the +3.3-V rail during normal operation. Each M41T00 device connects to an I2C bus (see page 5-7) for the corresponding processor complex. The three M41T00 devices are backed up by power from a single, super capacitor, which will hold a charge for at least two hours.
BLOCK DIAGRAM
The following block diagram shows the basic structure of the M41T00 device.
Figure 7-1: M41T00 Real-Time Clock Block Diagram
OPERATION
The M41T00 clock operates as a slave device on the serial bus. To obtain access, the proces-sor implements a start condition followed by the correct slave address (D016). Access the eight bytes in the following order:
1 Seconds register
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User’s Manual 7-1
Real-Time Clock: Clock Operation
2 Minutes register
3 Century/Hours register
4 Day register
5 Date register
6 Month register
7 Years register
8 Control register
The M41T00 clock continually monitors the supply voltage (Vcc) for an out of tolerance condition. If Vcc falls below switch-over voltage (Vso), the M41T00:
• Terminates an access in progress
• Resets the device address counter
• Does not recognize inputs (prevents erroneous data from being written)
At power-up, the M41T00 uses Vcc at Vso and recognizes inputs.
CLOCK OPERATION
Read the seven Clock registers one byte at a time or in a sequential block. Access the Con-trol register (address location 7) independently. An update to the Clock registers is delayed for 250 ms to allow the read to be completed before the update occurs. This delay does not alter the actual clock time. The eight byte clock register sets the clock and reads the date and time from the clock, as summarized in Table 7-1.
Table 7-1: RTC Register Map
Address: Data: Function/Range:D7 D6 D5 D4 D3 D2 D1 D0 BCD Format:
00 ST 10 Seconds Seconds Seconds 00—59
01 X 10 Minutes Minutes Minutes 00—59
02 CEB CB 10 Hours Hours Century/Hours 0-1/00-23
03 X X X X X Day Day 01—07
04 X X 10 Date Date Date 01—31
05 X X X 10 M Month Month 01—12
06 10 Years Years Years 00—99
07 OUT FT S Calibration Control —
Katana®3752 User’s Manual 10005594-027-2
Real-Time Clock: Clock Operation
ST: Stop bit. 1=Stops the oscillator0=Restarts the oscillator within one second
CEB: Century Enable Bit. 1=Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century0=CB will not toggle
CB: Century Bit.
Day: Day of the week.
Date: Day of the month.
OUT: Output level. 1=Default at initial power-up0=FT/OUT (pin 7) driven low when FT is also zero
FT: Frequency Test bit. 1=When oscillator is running at 32,768 Hz, the FT/OUT pin will toggle at 512 Hz0=The FT/OUT pin is an output driver (default at initial power-up)
S: Sign bit. 1=Positive calibration0=Negative calibration
Calibration: Calibration bits. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, neg-ative calibration) or split (added, positive calibration) depends on this five-bit byte. Adding counts accelerates the clock, and subtracting counts slows the clock down.
X: Don’t care bit.
10005594-02 Katana®3752 User’s Manual 7-3
Katana®3752 User’s Manual 10005594-027-4
(blank page)
10005594-02 Katana®3752
Section 8
Ethernet
The Katana®3752 supports one front panel 10/100/1000BaseT Ethernet port directly from the switch, two 1000BaseT Ethernet ports from processor complex #1, and one 1000BaseT Ethernet port from each of the other two processor complexes. The MV64460 system con-trollers each provide up to three Ethernet Media Access Control (MAC) units. A Broadcom BCM5691 12-port Multilayer Switch provides an SGMII/SerDes interface for full-duplex gigabit Ethernet operation.
SWITCH FEATURES
The Broadcom BCM5691 12-Port Gigabit Ethernet Multilayer Switch is a highly integrated device which is programmable via the PCI interface. Some features include:
• up to eight Class of Service (CoS) queues per port
• head of line blocking prevention
• packet aging mechanism
• back pressure handling mechanism
• per-port packet rate control
• port mirroring
• spanning tree support
• IEE 802.1D and IEEE 8021Q support
• IP multicasting
• trunking or port bundling
• traffic metering/shaping
• network management support
User’s Manual 8-1
Ethernet: Switch Features
The following block diagram shows how the BCM5691 connects the Ethernet ports.
Figure 8-1: Ethernet Ports Block Diagram
Processor #3
Processor #2
Processor #1
VLAN A VLAN B
cPSBPort #1
cPSBPort #2
port 0
port 0
port 5 port 8
port 10
port 2
10/100/1000BaseT
port 0 port 12
port 1 port 11GT1 – 1000BaseT only
GT0 – 1000BaseT only
GT0 – 1000BaseT only
GT0 – 1000BaseT only
Front PanelRJ45
port 110/100/1000BaseT
Front panel VLAN is disconnected by default.(see monitor environment variables for
configuration options) BCM5691Gigabit Switch
(12 ports, 1–12)
10/100/1000BaseT
Katana®3752 User’s Manual 10005594-028-2
Ethernet: Switch Configuration
SWITCH CONFIGURATION
The BCM5691 switch has various configuration and control registers. These include PCI configuration, CMIC, MMU, gigabit MAC, SGMII/SerDes PHY, statistics counters, and oth-ers.
The following register map shows the PCI configuration space header.
Register 8-1: BCM5691 PCI Configuration
Specific configuration of the BCM5691 control registers depends upon the application. Please refer to the StrataXGS™ BCM5690 Programmer’s Reference Guide (see listing in Table 1-
2) for complete details on programming these registers.
ETHERNET ADDRESSES
The Katana®3752 has seven unique Ethernet addresses for the board that must not be altered. Each address consists of 48 bits divided into two equal parts. The upper 24 bits define a unique identifier that has been assigned to Emerson Network Power, Embedded Computing by IEEE. The lower 24 bits are defined by Emerson to identify each of our prod-ucts.
The Ethernet addresses for the Katana®3752 are binary numbers, referenced as 12 hexa-decimal digits separated into pairs. Each pair represents eight bits. The addresses assigned to the Katana®3752 have the following form:
00 80 F9 7x yy zz
00 80 F9 is Emerson’s identifier. 7 is defined by Emerson and is specific to the Katana®3752 product group. x, yy, and zz are calculated. For the purpose of this calculation, the entire MAC address can be thought of as a 48-bit register, as shown below.
PCI HexOffset 31 16 15 0
00 PCI Device ID (569116) PCI Vendor ID (14E416)
04 PCI Command / Status
08 PCI Class Code (2800016) PCI Rev. ID
0C Built-In Self Test Header Type Bus Latency Timer Cache Line Size
10 Base Address Register Low
14 Base Address Register High
18—28 Reserved
2C Subsystem ID Subsystem Vendor ID
30—38 Reserved
3C PCI Max_LAT PCI Min_Gnt PCI Int. Pin PCI Int. Line
40 Reserved TRDY Time-out Retry Count
10005594-02 Katana®3752 User’s Manual 8-3
Ethernet: Front Panel Ethernet Port Connector
Register 8-2: MAC Calculation
To determine the last 17 bits of the MAC address (x, yy, and zz):
1 Subtract 1000 from the decimal serial number, convert it to hex, and place the 14-bit result in MAC[16:3].
2 Set the remaining three bits, MAC[2:0], according to the following list:001 = processor #1 Port A, MAC address #1010 = processor #1 Port A, MAC address #2011 = processor #1 Port B100 = processor #2 MAC address #1 101 = processor #2 MAC address #2110 = processor #3 MAC address #1111 = processor #3 MAC address #2
So for example, if the Katana®3752 serial number is 1377, the eight Ethernet addresses are:
Processor #1 Port A, MAC address #1 00:80:F9:7E:0B:C9Processor #1 Port A, MAC address #200:80:F9:7E:0B:CAProcessor #1 Port B00:80:F9:7E:0B:CBProcessor #2 MAC address #100:80:F9:7E:0B:CCProcessor #2 MAC address #200:80:F9:7E:0B:CDProcessor #3 MAC address #100:80:F9:7E:0B:CEProcessor #3 MAC address #200:80:F9:7E:0B:CF
FRONT PANEL ETHERNET PORT CONNECTOR
The Katana®3752 has a 10/100/1000BaseT Ethernet port on the front panel with direct access to the switch. This is a standard RJ45 connector, with the following pin assignments.
Table 8-1: Front Panel Ethernet Port Pin Assignments, P1
Pin: Signal: Pin: Signal:1 TRD0P 5 TRD2N
2 TRD0N 6 TRD1N
3 TRD1P 7 TRD3P
4 TRD2P 8 TRD3N
0000
00
0000 1000
80
0000 1111
F9
1001 0111
7x
x yyyy
yy
yyyy zzzz
zz
zzzz
MAC[47:0]
2:0LIST
16:3CALCULATED
23:17FIXED
47:24FIXED
Katana®3752 User’s Manual 10005594-028-4
10005594-02 Katana®3752
Section 9
IPMI Controller
The Katana®3752 implements a System Management Bus (SMB), as defined in the Com-pactPCI System Management Specification (see Table 1-2). It also supports the Intelligent Platform Management Interface (IPMI) Version 1.5 and Intelligent Platform Management Bus (IPMB) Version 1.0 specifications. At the core of SMB/IPMI interface is a Zircon PM device from QLogic Corporation. This device is a microprocessor-based Intelligent Platform Management Controller that implements all the standard IPMI commands and provides hardware interfaces for other system management features.
SMB/IPMI OVERVIEW
The basic features for the Katana®3752 SMB/IPMI implementation include:
• conformance to IPMI version 1.5 and IPMB version 1.0
• geographical addressing according to PICMG 2.9
• ability to read and write Field Replaceable Unit (FRU) data
• ability to reset from SMB or local processor
• ability to read two airflow temperature sensors
• ability to read six board voltage sensors
• ability to read a watchdog sensor for each 750GL processor
• ability to send event messages to a specified receiver
• all sensors can generate assertion and/or de-assertion event messages
• ability to control GPIO to assert resets to various sections of the board
• ability to broadcast a heartbeat message to a specified receiver
• support for field updates of firmware via SMB or local processor
User’s Manual 9-1
IPMI Controller: SMB/IPMI Overview
The Katana®3752 system management interface uses the Zircon PM device’s general-pur-pose input/output (GPIO) pins for the following functions:
• watchdog sensor inputs (from 750GL processors)
• GPIO (to 750GL processors)
• reset outputs (to 750GL processors)
• IPMI reset control
• cPCI Geographical Addressing inputs
The Zircon PM controller also has input pins to sense all on-board voltage supplies. Fig. 9-1 on the following page shows a block diagram of the Intelligent Platform Management Bus (IPMB) connections for the Katana®3752.
The Katana®3752 system management features include two inter-integrated circuit (I2C) interfaces, as follows:
• master/slave interface for 750GL communications
• master-only interface for accessing the two IPMI read-only memory (ROM) devices and temperature sensors
Katana®3752 User’s Manual 10005594-029-2
IPMI Controller: SMB/IPMI Overview
Figure 9-1: IPMB Connections Block Diagram
IPMB (SCL, SDA, PWR)
Katana3752
3
750GL#1
IPMI Microcontroller
I2C #2IPMI
BootcodeROM
IPMIBootloaderand FRU
ROM
I2C #1
ipmi_rst*
VoltageMonitor
IPMI PowerReset
A-to-D 1A-to-D 2
A-to-D 3A-to-D 4
A-to-D 5
A-to-D 6 5 V3.3 V2.5 V1.8 VCPU Core
IPM
I_RE
SET,
latc
hed
WD
E,G
PIO
(1)
One set of these signals toeach 750GL
GPIO[0:23]
BCM5691Core
mv1_port1_sel
Priv
ate
IPM
B
Public IPMB
TempSensor
TempSensor
10005594-02 Katana®3752 User’s Manual 9-3
IPMI Controller: I/O Interface
I/O INTERFACE
The Zircon PM provides 24 user-definable input/output (I/O) pins. The following table shows how the Katana®3752 implements these pins.
Table 9-1: Zircon PM General Purpose I/O Pin Functions
In addition to the General Purpose I/O, there are six analog-to-digital (A2D) input pins that are used for sensing the various power supplies on the board. The following table describes the Katana®3752 implementation of these pins.
Zircon PM Pin: Signal Name: Function:GPIO0 TEMP1_OS unused
GPIO1 TEMP2_OS unused
GPIO2 750GL3_IPMI_RST_R* active low IPMI reset output to 750GL processor #3
GPIO3 750GL2_IPMI_RST_R* active low IPMI reset output to 750GL processor #2
GPIO4 750GL1_IPMI_RST_R* active low IPMI reset output to 750GL processor #1
GPIO5 – unused
GPIO6 IPMI_TIMEROUT_D unused
GPIO7 750GL3_WD_LATCH active high input that signals a watchdog expiration event on 750GL processor #3
GPIO8 POST_FAULT active high input that signals a POST failure
GPIO9 750GL2_WD_LATCH active high input that signals a watchdog expiration event on 750GL processor #2
GPIO10 I2C_holdoff active high input that signals Zircon PM off the #1 I2C bus
GPIO11 750GL1_WD_LATCH active high input that signals a watchdog expiration event on 750GL processor #1
GPIO12 ZPM_4 unused
GPIO13 HS_FAULT_R* active low output that shuts power down to the board via the Hot Swap controller
GPIO14 – unused
GPIO[15:19] GA[4:0] Geographical Address inputs
GPIO20 – unused
GPIO21 – reserved
GPIO22 – reserved
GPIO23 – reserved
Katana®3752 User’s Manual 10005594-029-4
IPMI Controller: I2C Interfaces
Table 9-2: Zircon PM Analog-to-Digital Input Pin Functions
I2C INTERFACES
The Zircon PM controller supports three I2C interfaces. Port 0 is a master/slave interface which connects to the public IPMB. Port1 is a master/slave interface which connects to the I2C bus for 750GL processor #1. Port 2 is a master-only interface for accessing the two IPMI bootloader and boot code ROM devices, as well as the inlet/outlet temperature sensors.
Note: The Zircon PM device must be held in reset when the I2C Port 2 master-only interface is being used by 750GL processor #1 to access the serial EEPROM devices.
The 750GL processor #1 can master Port 2 while the Zircon PM is in reset. This allows for access to the IPMI serial EEPROMs, which is useful for programming the Zircon PM applica-tion code. An alternate method for accessing the IPMI serial EEPROMs from the 750GL is to use IPMI commands on I2C Port 1.
The 750GL processor #1 can master Port 1 to send IPMI requests and receive responses from the Zircon PM. All IPMI commands supported on the public IPMB are also supported on the private IPMB.
According to the IPMB specification, IPMI devices must use I2C Master Write cycles on the IPMB. All IPMI messages overlay the I2C Master Write data, including the I2C command byte. Using this format, the first byte of an IPMI message transmitted on the bus is also the I2C command byte.
Zircon PM Pin: Signal Name: Function:A2D1 1_25V connects directly to the Ethernet switch power
supply
A2D2 CPU_CORE connects directly to the 750GL processor #1 core power supply
A2D3 1_8V connects directly to the 1.8V power supply, which is used by the GbE PHYs
A2D4 MON_2_5V connects to the 2.5V power supply via a resistor divider network with a 0.796 ratio1
1. The A2D inputs on the Zircon PM have a maximum input voltage rating of 2.5V, which is the A2D power supply voltage. Therefore, any sensed voltage that has a value greater than 2.5V must be divided down.
A2D5 MON_3_3V connects to the 3.3V power supply via a resistor divider network with a 0.617 ratio1
A2D6 MON_5V connects to the 5V power supply via a resistor divider network with a 0.377 ratio1
10005594-02 Katana®3752 User’s Manual 9-5
IPMI Controller: IPMI Message Protocol
The PICMG 2.9 specification defines addressing on the public and private IPMBs. It defines the slave addresses assigned to the chassis, power supplies, and peripheral boards based on geographical addressing. Table 9-3 lists the slave address of each peripheral board, based on its geographical address.
Table 9-3: IPMB Slave Addresses
IPMI MESSAGE PROTOCOL
The IPMI message protocol is designed to be robust and support many different physical interfaces. The Zircon PM supports IPMI messages over the IPMB interface. Messages are defined as either a request or a response, as indicated by the least significant bit in the Net-work Function Code of the message. Table 9-4 shows the format of an IPMI request mes-sage.
Table 9-4: Format for IPMI Request Message
Geographical Address [0:4]:
IPMB Address (Hex):
Geographical Address [0:4]:
IPMB Address (Hex):
0 disabled 16 D0
1 B0 17 D2
2 B2 18 D4
3 B4 19 D6
4 B6 20 D8
5 B8 21 DA
6 BA 22 DC
7 BC 23 DE
8 BE 24 E0
9 C0 25 E2
10 C4 26 E4
11 C6 27 E6
12 C8 28 E8
13 CA 28 EA
14 CC 30 EC
15 CE 31 disabled
Byte: Bits:7: 6: 5: 4: 3: 2: 1: 0:
1 rsSA
2 netFn rsLUN
3 Checksum
4 rqSA
5 rqSeq rqLUN
Katana®3752 User’s Manual 10005594-029-6
IPMI Controller: IPMI Network Function Codes
The first byte contains the responder’s Slave Address, rsSA. The second byte contains the Network Function Code, netFn, and the responder’s Logical Unit Number, rsLUN. The third byte contains the two’s-complement checksum for the first two bytes. The fourth byte con-tains the requester’s Slave Address, rqSA. The fifth byte contains the requester’s Sequence Number, rqSeq, and requester’s Logical Unit Number, rqLUN. The Sequence number may be used to associate a specific response to a specific request. The sixth byte contains the Command Number. The seventh byte and beyond contain parameters for specific com-mands (if required). The final byte is the two’s-complement checksum of all of the message data after the first checksum.
An IPMI response message (see Table 9-5) is similar to a IPMI request message. The main dif-ference is that the seventh byte contains the Completion Code, and the eighth byte and beyond hold data received from the controller (rather than data to send to the controller). Also, the Slave Address and Logical Unit Number for the requester and responder are swapped.
Table 9-5: Format for IPMI Response Message
IPMI NETWORK FUNCTION CODES
All IPMI messages contain a Network Function Code field, which defines the category for a particular command. Each category has two codes assigned to it–one for requests and one for responses. The code for a request has the least significant bit of the field set to zero,
6 Command
7:N Data
N+1 Checksum
Byte: Bits:7: 6: 5: 4: 3: 2: 1: 0:
1 rqSA
2 netFn rqLUN
3 Checksum
4 rsSA
5 rsSeq rsLUN
6 Command
7 Completion Code
8:N Data
N+1 Checksum
Byte: Bits:7: 6: 5: 4: 3: 2: 1: 0:
10005594-02 Katana®3752 User’s Manual 9-7
IPMI Controller: IPMI Network Function Codes
while the code for a response has the least significant bit of the field set to one. Table 9-6 lists the network function codes (as defined in the IPMI specification) used by the Zircon PM.
Table 9-6: Network Function Codes
Hex Code Value(s): Name: Type: Description:00, 01 Chassis chassis device
requests/responses
00 = command/request, 01 = response:common chassis control and status functions
02, 03 Bridge bridge requests/responses
02 = request, 03 = response: message contains data for bridging to the next bus. Typically, the data is another message, which also may be a bridging message. This function is only present on bridge nodes.
04, 05 Sensor/Event
sensor and event requests/responses
04 = command/request, 05 = response: for configuration and transmission of Event Messages and system Sensors. This function may be present on any node.
06, 07 App application requests/responses
06 = command/request, 07 = response:message is implementation-specific for a particular device, as defined by the IPMI specification
08, 09 Firmware firmware transfer requests/responses
firmware transfer messages match the format of application messages, as determined by the particular device
0A, 0B Storage non-volatile storage requests/responses
may be present on any node that provides nonvolatile storage and retrieval services
0C-2F Reserved – reserved: 36 network functions (18 pairs)
30-3F OEM – vendor specific: 16 network functions (8 pairs). The vendor defines functional semantics for cmd and data fields. The cmd field must hold the same value in requests and responses for a given operation to support IPMI message handling and transport mechanisms. The controller’s Manufacturer ID value identifies the vendor or group.
Katana®3752 User’s Manual 10005594-029-8
IPMI Controller: IPMI Completion Codes
IPMI COMPLETION CODES
All IPMI response messages contain a hexadecimal Completion Code field that indicates the status of the operation. Table 9-7 lists the Completion Codes (as defined in the IPMI specifi-cation) used by the Zircon PM.
Table 9-7: Completion Codes
Code: Description:Generic Completion Codes 00, C0-FF
00 Command completed normally
C0 Node busy–command could not be processed because command-processing resources are temporarily unavailable
C1 Invalid command–indicates an unrecognized or unsupported command
C2 Command invalid for given LUN
C3 Time-out while processing command, response unavailable
C4 Out of space–command could not be completed because of a lack of storage space required to execute the given command operation
C5 Reservation canceled or invalid Reservation ID
C6 Request data truncated
C7 Request data length invalid
C8 Request data field length limit exceeded
C9 Parameter out of range–one or more parameters in the data field of the Request are out of range. This is different from Invalid data field code (CC) because it indicates that the erroneous field(s) has a contiguous range of possible values.
CA Cannot return number of requested data bytes
CB Requested sensor, data, or record not present
CC Invalid data field in Request
CD Command illegal for specified sensor or record type
CE Command response could not be provided
CF Cannot execute duplicated request–for devices that cannot return the response returned for the original instance of the request. These devices should provide separate commands that allow the completion status of the original request to be determined. An Event Receiver does not use this completion code, but returns the 00 completion code in the response to (valid) duplicated requests.
D0 Command response could not be provided, SDR Repository in update mode
D1 Command response could not be provided, device in firmware update mode
D2 Command response could not be provided, BMC initialization or initialization agent in progress
D3 Destination unavailable–cannot deliver request to selected destination. (This code can be returned if a request message is targeted to SMS, but receive message queue reception is disabled for the particular channel.)
D4 Cannot execute command, insufficient privilege level
D5 Cannot execute command, parameter(s) not supported in present state
10005594-02 Katana®3752 User’s Manual 9-9
IPMI Controller: Zircon PM IPMI Commands
ZIRCON PM IPMI COMMANDS
The Zircon PM peripheral management controller supports IPMI commands to query board information and to control the behavior of the board. These commands provide a means to:
• identify the controller
• reset the controller
• return the controller’s self-test results
• read and write the controller’s SROMs
• read the temperature, voltage, and watchdog sensors
• get specific information, such as thresholds, for each sensor
• read and write the Field Replaceable Unit (FRU) data
• reserve and read the Sensor Data Record (SDR) repository
• configure event broadcasts
• bridge an IPMI request to the public IPMB and return the response
• read and write the controller’s general-purpose I/O (GPIO)
• configure heartbeat broadcasts
Table 9-8 lists the IPMI commands supported by the Zircon PM along with the hexadecimal values for each command’s Network Function Code (netFn), Logical Unit Number (LUN), and Command Code (Cmd).
Table 9-8: Zircon PM IPMI Commands
FF Unspecified error
Device-Specific (OEM) Codes 01-7E
01-7E Device specific (OEM) completion codes–command-specific codes (also specific for a particular device and version). Interpretation of these codes requires prior knowledge of the device command set.
Command-Specific Codes 80-BE
80-BE Standard command-specific codes–reserved for command-specific completion codes (described in this chapter)
Command: netFn: LUN: Cmd:Set Event Receiver Sensor/Event 04, 05 00 00
Get Event Receiver Sensor/Event 04, 05 00 01
Platform Event (Transmit Only) Sensor/Event 04, 05 00 02
Code: Description: (continued)
Katana®3752 User’s Manual 10005594-029-10
IPMI Controller: Zircon PM IPMI Commands
The Zircon PM implements many standard IPMI commands. Please refer to the IPMI specifi-cation (listed in Table 1-2) for details about each command’s request and response data. The remainder of this section describes standard commands that have Zircon PM-specific request/response data.
Get Sensor Reading (Sensor/Event)The Get Sensor Reading command provides access to the Zircon PM’s internal or external sensors. The Zircon PM has six analog-to-digital converters, two temperature sensors, and three processor watchdog sensors. All of the analog-to-digital converters connect to the board’s power supplies, allowing the Zircon PM to monitor board voltages. Two on-board temperature sensors monitor the front-side airflow temperature. Three watchdog sensors monitor the operations on each 750GL processor. Table 9-9 shows the request/response data parameters for the Get Sensor Reading command.
Get Device SDR Information Sensor/Event 04, 05 00 20
Get Device SDR Sensor/Event 04, 05 00 21
Reserve Device SDR Repository Sensor/Event 04, 05 00 22
Get Sensor Reading Factors Sensor/Event 04, 05 00 23
Set Sensor Thresholds Sensor/Event 04, 05 00 26
Get Sensor Thresholds Sensor/Event 04, 05 00 27
Get Sensor Reading Sensor/Event 04, 05 00 2D
Set Get Sensor Type Sensor/Event 04, 05 00 2E
Get Sensor Type Sensor/Event 04, 05 00 2F
Get Device ID Application 06, 07 00 01
Broadcast 'Get Device ID' Application 06, 07 00 01
Cold Restart Application 06, 07 00 02
Warm Restart Application 06, 07 00 03
Get Self Test Results Application 06, 07 00 04
Send Message (private IPMB only) Application 06,07 00 34
Master Write-Read I2C Application 06, 07 00 52
Get FRU Inventory Area Info Storage 0A, 0B 00 10
Read FRU Inventory Data Storage 0A, 0B 00 11
Write FRU Inventory Data Storage 0A, 0B 00 12
Enter SDR Repository Update Mode Storage 0A, 0B 00 2A
Exit SDR Repository Update Mode Storage 0A, 0B 00 2B
Write Setting OEM 30, 31 00 00
Read Setting OEM 30, 31 00 01
Set Heartbeat OEM 30, 31 00 02
Get Heartbeat OEM 30, 31 00 03
Command: (continued) netFn: LUN: Cmd:
10005594-02 Katana®3752 User’s Manual 9-11
IPMI Controller: Zircon PM IPMI Commands
Table 9-9: Get Sensor Reading Parameters
Type: Byte: Data Field:Request Data
1 Sensor Number (hex)
41=1.25V Voltage Monitor42=CPU_CORE Voltage Monitor43=1.8V Voltage Monitor44=2.5V Voltage Monitor45=3.3V Voltage Monitor46=5.0V Voltage Monitor50=750GL #1 Watchdog51=750GL #2 Watchdog52=750GL #3 Watchdog60=Outflow Temperature Sensor61=Inflow Temperature Sensor70=750GL CPU #1 System Firmware Error71=750GL CPU #2 System Firmware Error72=750GL CPU #3 System Firmware Error
Response Data
1 Completion Code
2 Sensor Reading
Bits[0:7], byte of reading. Ignore on read if sensor does not return a numeric (analog) reading.
3 Bit[7], 0=All event messages disabled from this sensor
Bit[6], 0=Sensor scanning disabled
Bit[5], 1=Initial update in progress. When set, this bit indicates that a rearm or Set Event Receiver command has requested an update (which has not yet occurred) of the sensor status. Software should use this bit to avoid getting an incorrect status while the first sensor update is in progress. This bit is only necessary if the controller can receive and process a Get Sensor Reading or Get Sensor Event Status command for the sensor before the update has completed. For example, a fan RPM sensor may require seconds to accumulate the first reading after a re-arm.
Bits[4:0], Reserved. Ignore on read.
Katana®3752 User’s Manual 10005594-029-12
IPMI Controller: Zircon PM IPMI Commands
Response Data (continued)
4 Present Threshold Comparison Status
For threshold-based sensors:Bits[7:6], Reserved. Returned as 1 (binary). Ignore on read.Bit[5], 1=at or above (ε) upper non-recoverable thresholdBit[4], 1=at or above (ε) upper critical thresholdBit[3], 1=at or above (ε) upper non-critical thresholdBit[2], 1=at or below (δ) lower non-recoverable thresholdBit[1], 1=at or below (δ) lower critical thresholdBit[0], 1=at or below (δ) lower non-critical threshold
For discrete reading sensors:Bit[7], 1=state 7 assertedBit[6], 1=state 6 assertedBit[5], 1=state 5 assertedBit[4], 1=state 4 assertedBit[3], 1=state 3 assertedBit[2], 1=state 2 assertedBit[1], 1=state 1 assertedBit[0], 1=state 0 asserted
5 For Discrete Reading Sensors Only (optional, otherwise 0x00)
Bit[7], Reserved. Returned as 1 (binary). Ignore on read.Bit[6], 1=state 14 assertedBit[5], 1=state 13 assertedBit[4], 1=state 12 assertedBit[3], 1=state 11 assertedBit[2], 1=state 10 assertedBit[1], 1=state 9 assertedBit[0], 1=state 8 asserted
Type: Byte: Data Field: (continued)
10005594-02 Katana®3752 User’s Manual 9-13
IPMI Controller: Zircon PM IPMI Commands
Master Write-Read I2C (Application)The Master Write-Read I2C command allows for direct accesses to I2C devices. This com-mand can read from or write to any of the Zircon PM’s private I2C devices, such as SROMs or temperature sensors. Typically, you would use it to update the Zircon PM’s firmware from the management controller. Table 9-10 shows the request/response data parameters for this command.
Table 9-10: Master Write-Read I2C Parameters
Type: Byte: Data Field:Request Data
1 Bus ID
Bits[7:4], Channel Number. Write as 0000 (binary).
Bits[3:1], Bus ID, zero-based000=Public IPMB 001=Private I2C Bus #1, Private IPMB111=Private I2C Bus #2
Bit[0], Bus Type0=Public (IPMB)1=Private Bus
2 Bits[7:1], Slave Address of RecipientBit[0], Reserved. Write as zero.
3 Read Count. Number of bytes to read, one-based.0=No bytes to read.
4:M Data to Write
Response Data
1 Completion Code
A management controller shall return an error Completion Code if an attempt is made to access an unsupported bus.
Generic, plus following command-specific codes (hex):81=Lost Arbitration82=Bus Error83=NAK on Write84=Truncated Read
2:N Bytes read from specified slave address. This field will be absent if the read count is 0. The controller terminates the I2C transaction with a STOP condition after reading the requested number of bytes.
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IPMI Controller: Zircon PM IPMI Commands
Write Setting (OEM)The Write Setting command provides the ability to write a value to a general-purpose input/output (GPIO) pin on the Zircon PM. By toggling certain GPIO pins, software can reset or power-down the board. Table 9-11 shows the request/response data parameters for the Write Setting command.
Table 9-11: Write Setting Parameters
Type: Byte: Data Field:Request Data
1 Bits[7:1], Device Slave AddressBit[0], Reserved. Write as zero.
Currently defined to be zero.
2 Zircon Port Number
4=GPIO
3 Device Type
192=Zircon
4 Device Type Modifier
5=Inverted Output6=Normal Output
5 Sub-Device
GPIO2=Reset to 750GL #3, Active LowGPIO3=Reset to 750GL #2, Active LowGPIO4=Reset to 750GL #1, Active LowGPIO13=Hot-Swap Fault (Board Power), Active Low
6 Action Setting
0=De-assert output1=Assert output
7 Base Units
66=Bit setting
Response Data
1 Completion Code
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IPMI Controller: Zircon PM IPMI Commands
Read Setting (OEM)The Read Setting command provides the ability to read the value of a general-purpose input/output (GPIO) pin on the Zircon PM. Software can read certain GPIO pins to deter-mine if the board is in reset or powered-down. Table 9-12 shows the request/response data parameters for the Read Setting command.
Table 9-12: Read Setting Parameters
Type: Byte: Data Field:Request Data
1 Bits[7:1], Device Slave AddressBit[0], Reserved. Write as zero.
Currently defined to be zero.
2 Zircon Port Number
4=GPIO
3 Device Type
192=Zircon
Request Data (continued)
4 Device Type Modifier
3=Inverted Input4=Normal Input
5 Sub-Device
GPIO8=Input from 750GL #3GPIO10=Input from 750GL #2GPIO12=Input from 750GL #1GPIO13=Hot-Swap Fault (Board Power), Active LowGPIO15:19=Geographical Address 4..0, Active High
Response Data
1 Completion Code
2 Action Setting
0=Input is de-asserted1=Input is asserted
3 Base Units
66=Bit setting
Katana®3752 User’s Manual 10005594-029-16
IPMI Controller: Zircon PM IPMI Commands
Set Heartbeat (OEM)The Set Heartbeat command configures the Zircon PM to send a heartbeat message to a receiver on the IPMB or private I2C bus at a specific interval. The interval can range between 100 milliseconds and 25.6 seconds. The heartbeat message data may be a string of bytes or a command that gets processed at each interval. Table 9-13 shows the request/response data parameters for the Set Heartbeat command.
Table 9-13: Set Heartbeat Parameters
Type: Byte: Data Field:Request Data
1 Bus ID
Bits[7:4, Reserved
Bits[3:1], Bus ID, zero-based000=Public IPMB001=Private IIC Bus #1, Private IPMB111=Private IIC Bus #2
Bit[0], Bus Type0=Public (IPMB)1=Private Bus
2 Bits[7:1], Slave Address of RecipientBit[0], Reserved. Write as zero.
3 Send Interval
The interval in 100-millisecond counts between heartbeat transmissions. Writing zero disables the heartbeat.
Request Data (continued)
4 Command/Data
0=Following is a command to be processed. Its reply data is to be sent for the heartbeat data.
1=Following is constant data to be sent for the heartbeat data.
5:N Command or Constant Data
If the data is a command to be processed, this field must contain a properly formatted IPMB message, minus the first byte containing the slave address.
Response Data
1 Completion Code
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IPMI Controller: IPMI FRU Information
Get Heartbeat (OEM)The Get Heartbeat command returns the current configuration of the heartbeat function for a specified interface. The response data has the same definition as the Set Heartbeat request data (see “Set Heartbeat (OEM)” on page 9-17). Table 9-14 shows the request/response data parameters for the Get Heartbeat command.
Table 9-14: Get Heartbeat Parameters
IPMI FRU INFORMATION
The Zircon PM stores Field Replaceable Unit (FRU) information in its boot memory (SROM). The data structure contains information such as the product name, part number, serial number, and manufacturing date. Please refer to the IPMI specification for complete details on the FRU data structure. Table 9-15 lists the general contents of the Katana®3752’s FRU information.
Table 9-15: FRU Definition
Type: Byte: Data Field:Request Data
1 Bus ID
Bits[7:4], Reserved
Bits[3:1], Bus ID, zero-based000=Public IPMB001=Private I2C Bus #1, Private IPMB111=Private I2C Bus #2
Bit[0], Bus Type0=Public (IPMB)1=Private Bus
Response Data
1 Completion Code
2 Bits[7:1], Slave Address of recipientBit[0], Reserved. Returned as zero. Ignore on read.
3 Send Interval.
The interval in 100-millisecond counts between heartbeat transmissions. Zero indicates that the heartbeat is disabled.
4 Command/Data
0=Following is a command to be processed. Its reply data is to be sent for the heartbeat data.
1=Following is constant data to be sent for the heartbeat data.
5:N Command or Constant Data
Item: Description:Internal Use Area
Return Counter Count of how many times the board has been returned to Emerson (one byte at hex offset 0x0001)
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IPMI Controller: IPMI Device SDR Repository
IPMI DEVICE SDR REPOSITORY
The Zircon PM implements a Device SDR Repository that contains Sensor Data Records for the Zircon PM, the FRU device, and each sensor. A system management controller may use the Get Device SDR command to read the repository and dynamically discover the capabili-ties of the board. Please refer to the IPMI specification (listed in Table 1-2) for more informa-tion on using Sensor Data Records and the Device SDR Repository.
Repair Counter Count of how many times a hardware defect was found and repaired, excluding firmware or ECO updates (one byte at hex offset 0x0002)
Reserved by Emerson 0x0003—0x00FF
Customer Area 0x0100—0x017F
Board Information Area
Manufacturing Date/Time Variable, expressed as the number of minutes since 12:00 AM on January 1, 1996
Board Manufacturer “Emerson Network Power, Embedded Computing”
Board Product Name “Katana®3752”
Board Serial Number Variable, formatted as “P682-XXXX”
Board Part Number Variable, formatted as “10XXXXXX-YY-Z”
FRU File ID Variable, for example: “smbFruInit.c” if the VxWorks tools were used to program the FRU information
Manufacturing Locale “Madison, WI, USA”
Product Information Area
Manufacturer Name “Emerson Network Power, Embedded Computing”
Product Name “Katana®3752”
Product Part/Model Number Variable, formatted as “10XXXXXX-YY-Z”
Product Version Not used, same information is provided by the part number
Product Serial Number Variable, formatted as “P682-XXXX”
Asset Tag Not Used
FRU File ID Variable, for example: “smbFruInit.c” if the VxWorks tools were used to program the FRU information
Item: Description: (continued)
10005594-02 Katana®3752 User’s Manual 9-19
IPMI Controller: IPMI Event Messages
IPMI EVENT MESSAGES
Under certain circumstances, some sensors connected to the Zircon PM can generate Event Messages for the system management controller, as described below in Table 9-16.
Table 9-16: IPMI Event Messages Generating Sensors
To enable these messages, the system management controller must send a Set Event Receiver command to the Zircon PM, along with the address of the Event Receiver. Table 9-
17 shows the format of an Event Message.
Table 9-17: Event Message Format
Sensor Name:Sensor Type:
Event/Reading Type:
Sensor Number:
Event Generator:
Proc1Progress 0x0F 0x6F 0x70 Yes
Proc1Watchdog 0x23 0x6F 0x50 Yes
Proc2Progress 0x0F 0x6F 0x71 Yes
Proc2Watchdog 0x23 0x6F 0x51 Yes
Proc3Progress 0x0F 0x6F 0x72 Yes
Proc3Watchdog 0x23 0x6F 0x52 Yes
OutflowTemp 0x01 0x01 0x60 Yes
InflowTemp 0x01 0x01 0x61 Yes
+5.0V 0x02 0x01 0x46 Yes
+3.3V 0x02 0x01 0x45 Yes
+2.5V 0x02 0x01 0x44 No
+1.8V 0x02 0x01 0x43 No
PPC750FX 0x02 0x01 0x42 No
BCM5691 0x02 0x01 0x41 No
Byte:1 Field: Description:0 RsSA Responder’s Slave Address (Address of Event Receiver)
1 NetFn/RsLUN Net Function Code (0x04) in upper 6 bits; Responder’s LUN in lower 2 bits
2 Chk1 Checksum #1
3 RqSA Requester’s Slave Address (Address of our board on IPMB)
4 RqSeq/RqLUN Request Sequence number in upper 6 bits; Requester’s LUN in low 2 bits
5 Cmd Command (Always 0x02 for event message)
6 EvMRev Event Message Revision (0x04 for IPMI 1.5)
7 Sensor Type Indicates event class or type of sensor that generated the message
8 Sensor Number A unique number indicating the sensor that generated the message
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IPMI Controller: IPMI Event Messages
Event-generating sensors with a Threshold Event/Reading Type (0x01) initiate an event message when a sensor reading crosses the defined threshold. The default thresholds for a particular sensor are retrieved by sending the Zircon PM a Get Sensor Thresholds com-mand. The system management controller must send the Zircon PM a Get Sensor Reading command to retrieve the current sensor reading. (See the IPMI specification listed in Table 1-2 for further details regarding these commands.)
Watchdog 2 Type (0x23) sensors (Proc1Watchdog, Proc2Watchdog, and Proc3Watchdog) generate an event when the 750FX1_WD_LATCH signal (see Table 9-1) for a particular sen-sor is asserted. A timeout in the watchdog mechanism of the Marvell system controller asserts this signal. An associated de-assertion event occurs when the system software on the Katana®3752 has recovered and the 750FX1_WD_LATCH signal has been cleared.
On the Katana®3752, sensor numbers 0x70, 0x71, and 0x72 are System Firmware Progress sensors. This type of sensor (0x0F) generates events to communicate Power On Self-Test (POST) and boot failures. Table 9-18 shows the OEM values defined for the data associated with this type of sensor.
Table 9-18: System Firmware Progress OEM Event Data
9 Event Dir / Event Type
Upper bit indicates direction (0 = Assert, 1 = Deassert); Lower 7 bits indicate type of threshold crossing or state transition
10 Event Data 0 Data for sensor and event type
11 Event Data 1 (Optional) Data for sensor and event type
12 Event Data 2 (Optional) Data for sensor and event type
13 Chk2 Checksum #2
1. Each byte has eight bits.
Description:Event Data 0(Byte 10):
Event Data 1(Byte 11):
Event Data 2(Byte 12):
Memory POST failed 0xA0(101000002)
0x01(000000012)
0xFF(111111112)
I2C POST failed 0xA0(101000002)
0x40(010000002)
0xF0(111100002)
Flash POST failed 0xA0(101000002)
0x50(010100002)
0xF0(111100002)
PCI Enumerated w/o EREADY 0xA0(101000002)
0xFE(111111102)
0x01(000000012)
Ethernet Switch POST failed 0xA0(101000002)
0x60(011000002)
0xFF(111111112)
Byte:1 Field: Description: (continued)
10005594-02 Katana®3752 User’s Manual 9-21
IPMI Controller: IPMI Event Messages
The Event Data 0 byte has three fields: Bits 7:6 describe the contents of Event Data 1 (set to 102 when an OEM code is present in Event Data 1). Bits 5:4 describe the contents of Event Data 2 (also set to 102 when an OEM code is present). Bits 3:0 store the Sensor-specific Off-set value for the System Firmware Progress sensor (zero indicates a POST Error). Please see the IPMI specification for further information on these fields.
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10005594-02 Katana®3752
Section 10
Hot Swap
The Katana®3752 baseboard incorporates two Maxim MAX5925 Hot Swap™ controller devices. The board complies with the CompactPCI (cPCI) Hot Swap Specification (listed in Table 1-2), except for the early power pins1. Katana®3752 circuit boards allow for High Availability Hot Swap systems, including cPCI/PSB systems (without a cPCI interface). Some basic Hot Swap features include:
• Ejector switch indication and Hot Swap LED control
• Back-end voltage isolation using the BD_SEL* signal and power supply health indication using the CPCI_HEALTHY* signal
• Minimal capacitive loading on power supplies and I/O pins, according to the Hot Swap Specification
• Back-end, in-rush, current limiting
CPCI RESET BLOCKING
The Katana®3752 implements a jumper, JP3 (see Fig. 2-4), which can prevent the cPCI_RST signal from resetting the board. This allows system designers the flexibility to choose whether or not the Katana®3752 uses the cPCI reset signal (from the backplane). When pins 1 and 2 of JP3 are jumpered, the cPCI_RST signal is enabled. With no jumper installed (default), the Katana®3752 ignores the cPCI_RST signal.
POWER SUPPLY MONITORING
The Katana®3752 continuously monitors all on-board switching power supplies. In the event of a voltage or current fault, the blade automatically performs a complete shutdown.
1. The long pins for early power do have resistive current limiting to all devices supplied by early power, but not to the early power planes themselves.
User’s Manual 10-1
Hot Swap: Hot Swap LED and Ejector Switch Control
There are three options for recovering from this shutdown condition:
1 The system controller / shelf manager can toggle the CONN_CPCI_BD_SEL* signal at the backplane connector, J1, pin D15.
2 The IPMI controller can toggle the blade shutdown.
3 The operator can manually cycle power to the blade. (That is, turn it off and back on.)
Each of these recovery methods applies a fresh power cycle to the blade. If the original fault condition is removed and there is no permanent damage, the blade will power up normally.
HOT SWAP LED AND EJECTOR SWITCH CONTROL
The LED/ejector switch control mechanism works in conjunction with the Power Good indi-cation from the Hot Swap controller circuit. The Hot Swap logic functions as follows when a board is inserted into a slot:
1 The Hot Swap LED illuminates immediately when the board is inserted. This functionality is enabled by two things:
• The Hot Swap Logic (HSL) programmable logic device (PLD) is indicating power supply voltages are not within the proper tolerance or when the BDSEL* signal is not driven low (active) to the HSL PLD.
• The MV64460 system controller/bridge is held in reset.
2 As soon as the power is good and the MV64460 comes out of reset, the blue Hot Swap LED turns off. At this point, the LED is under the control of the software, and the board is set for normal operation.
The Hot Swap logic functions as follows when a board is removed from a slot:
1 The operator opens the ejector handle (but does not yet remove the board from the slot). This sends an interrupt to the MV64460 via MPP12.
2 The processor performs board quiescence tasks. Upon completion, the software clears the interrupt and turns on the blue Hot Swap LED via the HSR register in the device bus PLD (see Register Map 6-13 for details).
3 Now the board can be removed safely from the system.
HEALTHY* SIGNAL
The Katana®3752 logic asserts the HEALTHY* signal whenever the Hot Swap Logic (HSL) programmable logic device (PLD) indicates that all power supplies are within the appropri-ate range. Other logic, including board reset signals, does not affect the HEALTHY* signal.
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10005594-02 Katana®3752
Section 11
Backplane Signals
This chapter describes the Katana®3752 board’s backplane signals. It lists the pinouts for connectors J1, J2, and J3 on the CompactPCI backplane.
OVERVIEW
Connector J1 carries Intelligent Platform Management Interface (IPMI) control signals to/from the CompactPCI (cPCI) backplane. Connector J2 carries power supply source sig-nals from the cPCI backplane to the Katana®3752 circuit board. Connector J3 carries giga-bit Ethernet signals to/from the packet-switched CompactPCI backplane (cPSB).
PINOUTS
J1 is a 110-pin female connector (Emerson #01899062-00) that routes IPMI signals to the CompactPCI backplane, as listed in the table below.
Table 11-1: cPCI Connector Pin Assignments, J1
Pin: Row A: Row B: Row C: Row D: Row E:1 EP_5V EP_NEG12V no connection EP_POS12V EP_5V
2 no connection EP_5V no connection no connection no connection
3 no connection no connection no connection EP_5V1 no connection
4 IPMB_PWR CONN_HEALTHY*
LJ1_EPVIO no connection no connection
5 no connection no connection CONN_CPCI_RST*
ground no connection
6 no connection no connection EP_3_3V1 no connection no connection
7 no connection no connection no connection ground no connection
8 no connection ground EP_VIO no connection no connection
9 no connection no connection no connection ground no connection
10 no connection ground EP_3_3V no connection no connection
11 no connection no connection no connection ground no connection
12—14 keying keying keying keying keying
15 EP_3_3V no connection no connection CONN_CPCI_BD_SEL*
no connection
16 no connection no connection EP_VIO no connection no connection
17 EP_3_3V IPMB_SCL_R IPMB_SDA_R ground no connection
18 no connection ground EP_3_3V no connection no connection
19 EP_3_3V no connection no connection ground no connection
20 no connection ground EP_VIO no connection no connection
21 EP_3_3V no connection no connection no connection no connection
22 no connection no connection EP_3_3V1 no connection no connection
23 EP_3_3V no connection no connection EP_5V1 no connection
User’s Manual 11-1
Backplane Signals: Pinouts
J2 is a 110-pin female connector (Emerson #01899063-00) that routes power signals from the CompactPCI backplane, as listed in the table below:
Table 11-2: cPCI Connector Pin Assignments, J2
24 no connection EP_5V LJ1_EPVIO no connection no connection
25 EP_5V no connection EP_3_3V EP_3_3V EP_5V
1. These long pins for early power do not have resistive current limiting. Therefore, they do not meet the CompactPCI specification for early power usage.
Pin: Row A: Row B: Row C: Row D: Row E:1 no connection ground no connection no connection no connection
2 no connection no connection no connection no connection no connection
3 no connection ground no connection no connection no connection
4 EP_VIO no connection no connection ground no connection
5 no connection no connection EP_VIO no connection no connection
6 no connection no connection no connection ground no connection
7 no connection ground EP_VIO no connection no connection
8 no connection no connection no connection ground no connection
9 no connection ground EP_VIO no connection no connection
10 no connection no connection no connection ground no connection
11 no connection ground EP_VIO no connection no connection
12 no connection no connection no connection ground no connection
13 no connection ground EP_VIO no connection no connection
14 no connection no connection no connection ground no connection
15 no connection ground no connection no connection no connection
16 no connection no connection no connection ground no connection
17 no connection ground no connection no connection no connection
18 no connection no connection no connection ground no connection
19 ground ground no connection no connection no connection
20 no connection ground no connection ground no connection
21 no connection ground no connection no connection no connection
22 GA4 (pulled up) GA3 (pulled up) GA2 (pulled up) GA1 (pulled up) GA0 (pulled up)
Pin: Row A: Row B: Row C: Row D: Row E:
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J3 is a 95-pin female connector (Emerson #01899064-00) that routes Ethernet differential signals to the cPSB backplane, as listed in the table below.
Table 11-3: cPSB Connector Pin Assignments, J3
Pin: Row A: Row B: Row C: Row D: Row E:1—14 no connection no connection no connection no connection no connection
15 CPSB2_TRD1P CPSB2_TRD1N MGND CPSB2_TRD3P CPSB2_TRD3N
16 CPSB2_TRD0P CPSB2_TRD0N MGND CPSB2_TRD2P CPSB2_TRD2N
17 CPSB1_TRD1P CPSB1_TRD1N MGND CPSB1_TRD3P CPSB1_TRD3N
18 CPSB1_TRD0P CPSB1_TRD0N MGND CPSB1_TRD2P CPSB1_TRD2N
19 MGND MGND MGND MGND MGND
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Katana®3752 User’s Manual 10005594-0211-4
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10005594-02 Katana®3752
Section 12
Monitor
The Katana®3752 monitor is based on the Embedded PowerPC Linux Boot Project (PPC-Boot) boot program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.emerson-embeddedcomputing.com, send an e-mail to [email protected], or call Emerson at 1-800-327-1251. This chapter describes the monitor’s basic features, operation, and con-figuration sequences. This chapter also serves as a reference for the monitor commands and functions.
COMMAND-LINE FEATURES
The Katana®3752 monitor uses a command-line interface with the following features:
Auto-Repeat: After entering a command, you can re-execute it simply by pressing the up arrow and ENTER or RETURN key.
TFTP Boot : You can use the TFTP protocol to load application images via Ethernet into the Katana®3752’s memory.
Auto-Boot : You can store specific boot commands in the environment to be executed automatically after reset.
Flash Programming: You can write application images into flash via the PPCBoot command line.
At power-up or after a reset, the monitor runs diagnostics and reports the results in the start-up display, see Fig. 12-1 and Fig. 12-2. During the power-up sequence, the monitor con-figures the board according to the environment variables (see page 12-23) and settings in the Board Configuration registers (see page 6-5). If the configuration indicates that auto-boot is enabled, the monitor attempts to load the application from the specified device. If the monitor is not configured for autoboot or a failure occurs during power-up, the monitor enters normal command-line mode.
User’s Manual 12-1
Monitor: Command-Line Features
Figure 12-1: Example Monitor Start-up Display for CPU1
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Katana®3752 User’s Manual 10005594-0212-2
Monitor: Basic Operation
Figure 12-2: Example Monitor Start-up Display for CPU2 and CPU3
BASIC OPERATION
The Katana®3752 monitor performs various configuration tasks upon power-up or reset. This section describes the monitor operation during initialization of the Katana®3752 board. The flowchart (see Fig. 12-3) illustrates the power-up and reset sequence (italicized text indicates environment variables).
Power-Up/Reset SequenceAt power-up or board reset, the monitor performs hardware initialization, diagnostic rou-tines, autoboot procedures, free memory initialization, and if necessary, invokes the com-mand line. If you press the h key during the autoboot sequence, the process aborts.
After a successful power-up/reset sequence, the red power/fault LED on the front panel blinks continuously. If a fault occurs, the LED stops blinking and remains on. The fpledoff monitor command (see page 12-20) and blinkled NVRAM parameter (see Table 12-3) allow you to customize this LED’s behavior.
Prior to the console port being available, the monitor will display a four-bit hexadecimal value on LED1 through LED4 to indicate the power-up status. In the event of a specific ini-tialization error, the board initialization will halt. The LEDs map to the processors as shown in Table 12-2. See Fig. 2-3 for the debug LED locations. Refer to Fig. 12-3 for the LED patterns at various initialization steps.
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10005594-02 Katana®3752 User’s Manual 12-3
Monitor: Basic Operation
Note: These LEDs may not be populated.
Table 12-1: Debug LEDs per CPU
LED: CPU 1: CPU 2: CPU 3:LED1 CR28 CR16 CR11
LED2 CR29 CR17 CR12
LED3 CR30 CR18 CR13
LED4 CR27 CR15 CR10
Katana®3752 User’s Manual 10005594-0212-4
Monitor: Basic Operation
Figure 12-3: Power-up/Reset Sequence Flowchart
RESET
Initialize HID0Initialize MSR
Relocate the baseof the MV64460internal registers
750GL floatingpoint registerinitialization
750GL BAT andsegment register
initialization
Invalidate the L2cache
LED 0001
Invalidate andenable the L1
cache
Setup initial stackand data region in
cache
Configure theMV64460 devicechip selects forflash and CPLD
Initialize theMV64460 CPU
interface settings
Enable icacheLED 0010
Initialize thePPCBoot
environment
Init. serial port perbaudrate
environment var.LED 0011
Display versionstring
Display CPU,board, and bus
speedLED 0100
InitializeI2C
Init. SDRAM. Clearper clearmem andconfigure per eccenvironment vars.
Initializefinal stack
Re-locatePPCBoot to RAM
LED 0110
Initializeflash
Initialize mallocarea
InitializePCI
Isprocessor 1 a
Monarch?
Enumerate PCIper enumerate
environmentvariable
Yes
Display boardserial number
No
Enable MV64460interrupts
Configure dcacheper cachemode
and dcacheenvironment vars.
Configure icacheper icache
environmentvariable
Configure L2cache per l2cache
and l2modeenvironment vars.
Display LED 0111
Initialize Ethernetports
Turn off debugLEDs and blinkfront panel red
LED per blinkledenvironment var.
Main Loop
Perform boarddiagnostics perpowerondiags
environment var.
Check IPMIcontroller peripmipresent
environment var.(processor 1 only)
10005594-02 Katana®3752 User’s Manual 12-5
Monitor: Basic Operation
Monitor Memory UsageThe Katana®3752 monitor preserves the top 32 megabytes of SDRAM for use by operating system and/or application error detection and recovery purposes. The monitor will initialize this area at boot for ECC, as required by the setting of the ecc environment parameter, but the contents will not be cleared, regardless of the clearmem environment parameter set-ting.
The PPCBoot stack, uninitialized data, and code are placed in the next 1 to 2 megabytes directly below the Error Detection and Recovery area. The monitor also reserves the base 16 kilobytes of SDRAM for the exception vector table and monitor use.
Caution: Any writes to these areas can cause unpredictable operation of the monitor.
The Katana®3752 monitor also uses the EEPROM at hex address 0xA6 on the I2C bus to store configuration parameters, diagnostic results, and user-defined data. (Refer to Table 12-3 for details.)
POST Diagnostic ResultsThe Katana®3752 stores power-on self-test (POST) diagnostic results in nonvolatile ran-dom-access memory (NVRAM). This memory is located in the EEPROM at hex address 0xA6 on the I2C bus. The POST results are stored as four 8-bit bytes in the EEPROM, defined as fol-lows.
Table 12-2: POST Diagnostic Bytes
The bits at hex offset 0x1DD8 contain the following POST results.
Register 12-1: Monitor POST Results
ER: No EREADY Test (processor #1 only)pass value=0, fail value=1
PCI: Local PCI Testpass value=0, fail value=1
Hex Offset: Description:1DDB Test result bits
1DDA Reserved for Emerson use
1DD9 Reserved for Emerson use
1DD8 Reserved for customer use
7 6 5 4 3 2 1 0Reserved ER PCI SW IIC FL MEM
!
Katana®3752 User’s Manual 10005594-0212-6
Monitor: Monitor Recovery and Updates
SW: Switch Testpass value=0, fail value=1
IIC: I2C Testpass value=0, fail value=1
FL: Flash Testpass value=0, fail value=1
MEM: SDRAM Testpass value=0, fail value=1
MONITOR RECOVERY AND UPDATES
This section describes how to recover and/or update the monitor, given one or more of the following conditions:
• If there is no console output from any of the three processors, the monitor may be corrupted and need recovering.
• If the monitor still functions, but is not operating properly, then you may need to reset the environment variables.
Recovering the MonitorFirst, make sure that a monitor ROM device is installed in the PLCC socket. Then, place a jumper on JP1, across pins 2 and 3 (see Fig. 2-4).
1 Issue the following command to recover processor #1, where serial# is the four digit serial number, 682A-xxxx:
[Proc 1] => moninit serial#
2 Perform the following tasks:
Reset the monitor:
[Proc 1] => reset
Reset the environment parameters:
[Proc 1] => envinit serial#
3 Power down the board and remove the jumper from JP1, pins 1 and 2.
4 If necessary, program the monitor for processors #2 and #3:
[Proc 1] => moninit p2 serial# fff00000[Proc 1] => moninit p3 serial# fff00000
5 Cycle power to the board.
6 Reset the environment parameters for processors #2 and #3, as follows:
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Monitor: Monitor Recovery and Updates
[Proc 1] => envinit p2 serial#[Proc 1] => envinit p3 serial#
Updating the MonitorTo update the monitor, ensure that an appropriate VLAN is set up in the Ethernet switch and execute the following commands, inserting the appropriate data in the italicized fields:
1 If necessary, edit your network settings:
[Proc 1] => setenv ipaddr 192.168.1.100 [Proc 1] => setenv gatewayip 192.168.1.1 [Proc 1] => setenv netmask 255.255.255.0 [Proc 1] => setenv serverip 10.64.16.168 [Proc 1] => setenv ethport all[Proc 1] => setenv frnt_one auto[Proc 1] => setenv vlan-a proc1_a,proc2_a,cpsb_one,frnt_one[Proc 1] => saveenv [Proc 1] => reset
2 TFTP the new monitor (binary) image to memory location 0x100000:
[Proc 1] =>tftpboot 100000 path/on/tftp/server/to/monitor.bin
3 Update the monitor for each processor:
[Proc 1] => moninit serial# 100000 [Proc 1] => moninit p2 serial# 100000 [Proc 1] => moninit p3 serial# 100000
4 Cycle power to the board.
5 Reset the environment parameters:
[Proc 1] => envinit serial#[Proc 1] => envinit p2 serial#[Proc 1] => envinit p3 serial#
If moninit( ) fails, burn the new monitor to a ROM and follow the recovery steps in “Recov-ering the Monitor” on page 12-7.
Resetting Environment VariablesIssue the following command at the monitor prompt, where serial# is the four-digit serial number, 682A-xxxx:
[Proc 1] => envinit serial#[Proc 1] => envinit p2 serial#[Proc 1] => envinit p3 serial#
Katana®3752 User’s Manual 10005594-0212-8
Monitor: Monitor Command Reference
MONITOR COMMAND REFERENCE
This section describes the syntax and typographic conventions for the Katana®3752 moni-tor commands. Subsequent sections in this chapter describe individual commands, which fall into the following categories: boot, file load, memory, Flash, EEPROM/I2C, environ-ment, test, and other commands.
Command SyntaxThe monitor uses the following basic command syntax:
<Command> <argument 1> <argument 2> <argument 3>
• The command line accepts three different argument formats: string, numeric, and symbolic. You must separate all command arguments by spaces, except for the argument flags (see below).
• Monitor commands that expect numeric arguments assume a hexadecimal base.
• All monitor commands are case sensitive.
• Some commands accept flag arguments. A flag argument is a single character that begins with a period. There is no white space between an argument flag and a command. For example, md.b 80000 is a valid monitor command, while md .b 80000 is not.
• You may abbreviate some commands by typing only the first few characters of the command. For example, you can type ver instead of version. However, the abbreviated commands do not work for accessing online help. You must type help and the full command name.
Typographic ConventionsText formatted in Courier indicates a command example or a direct value that you enter. Square brackets [ ] enclose optional arguments, and angled brackets < > enclose required arguments. Italic type indicates a variable or field that requires input.
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Monitor: Boot Commands
BOOT COMMANDS
The boot commands provide facilities for booting application programs and operating sys-tems from various devices.
bootdExecute the default command stored in the bootcmd environment variable.
Definition: bootd
bootelfThe bootelf command boots from an ELF image in memory, where address is the load address of the ELF image.
Definition: bootelf [address]
bootmThe bootm command boots an application image stored in memory, passing any entered arguments to the called application. When booting a Linux kernel, arg can be the address of an initrd image. If you do not specify addr, the environment variable loadaddr is the default.
Definition: bootm [addr [arg …]]
bootpThe bootp command boots an image via a network connection using the BootP/TFTP pro-tocol. If you do not specify loadaddress or bootfilename, the environment variables loadaddr and bootfile are the default.
Definition: bootp [loadAddress] [bootfilename]
bootvThe bootv command checks the checksum on the primary image (in flash) and boots it, if valid. If it is not valid, it checks the checksum on the secondary image (in flash) and boots it, if valid. If neither checksum is valid, the command returns back to the monitor prompt.
Definition: Verify bootup.
bootv
Write image to flash and update NVRAM.
bootv <primary|secondary> write <source> <dest> <size>
Update NVRAM based on image already in flash.
bootv <primary|secondary> update <source> <size>
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Monitor: Memory Commands
Check validity of images in flash.
bootv <primary|secondary> check
bootvxThe bootvx command boots vxWorks from an ELF image, where address is the load address of the VxWorks ELF image.
Definition: bootvx [address]
rarpbootThe rarpboot command boots an image via a network connection using the RARP/TFTP protocol. If you do not specify loadaddress or bootfilename, the environment variables loadaddr and bootfile are the default.
Definition: rarpboot [loadAddress] [bootfilename]
tftpbootThe tftpboot command boots an image via a network connection using the TFTP protocol. The environment variables ipaddr and serverip are additional parameters for this command. If you do not specify loadaddress or bootfilename, the environment variables loadaddr and bootfile are the default.
Definition: tftpboot [loadAddress] [bootfilename]
MEMORY COMMANDS
The memory commands allow you to manipulate specific regions of memory. For some memory commands, the following flags determine the data size:
.b for data in 8-bit bytes
.w for data in 16-bit words
.l data in 32-bit long words
These flags are optional arguments and describe the objects on which the command oper-ates. If you do not specify a flag, memory commands default to 32-bit long words. Numeric arguments are in hexadecimal.
cmpThe cmp command compares count objects between addr1 and addr2. The console displays any differences.
Definition: cmp [.b, .w, .l] <addr1> <addr2> <count>
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Monitor: Memory Commands
cpThe cp command copies count objects located at the source address to the target address.
Note: If the target address is located in the range of the flash device, it will program the flash with count objects from the source address. The cp command does not erase the flash region prior to copying the data. You must manually erase the flash region using the erase com-mand prior to using the cp command.
Definition: cp [.b, .w, .l] <source> <target> <count>
Example: In this example, the cp command copies 0x1000 32-bit values from address 0x100000 to address 0x80000.
=> cp 100000 80000 1000
findThe find command searches from base_addr to top_addr looking for a pattern. For the find command to work properly, the size of pattern must match the size of the object flag.
Definition: find [.b, .w, .l] <base_addr> <top_addr> <pattern>
Example: In this example, the find command searches for the 32-bit pattern, 0x12345678, in the address range starting at 0x40000 and ending at 0x80000.
=> find.1 40000 80000 12345678
Searching from 0x00040000 to 0x00080000Match found: data = 0x12345678 Adrs = 0x00050a6c
=>
mdThe command md displays the contents of memory starting at address. An optional third argument, # of objects, can define the number of objects displayed. The command displays the memory’s numerical value and ASCII equivalent.
Definition: md [.b, .w, .l] <address> [# of objects]
Example: In this example, the md command displays thirty-two 16-bit words starting at the physical address 0x80000.
=> md.w 80000 20
00080000: ffff ffff ffff ffff ffff ffff ffff ffff ................00080010: ffff ffff ffff ffff ffff ffff ffff ffff ................00080020: ffff ffff ffff ffff ffff ffff ffff ffff ................00080030: ffff ffff ffff ffff ffff ffff ffff ffff ................
Katana®3752 User’s Manual 10005594-0212-12
Monitor: Memory Commands
mmThe mm command modifies memory one object at a time. Once started, the command line prompts for a new value at the starting address. After a new value is entered, pressing ENTER automatically increments the address to the next location. Pressing ENTER without entering a new value does not change the original value for that address. To exit the mm command, enter a non-valid hexadecimal value (such as x), followed by ENTER.
Definition:
Example: In this example, the mm command writes random 8-bit data, starting at the physical address 0x80000.
00080000: ff ? 1200080001: ff ? 2300080002: ff ? 3400080003: ff ? 4500080004: ff ?00080005: ff ? x=> md.b 80000 600080000: 12 23 34 45 ff ff .#4E=>
mwThe command mw writes value to memory starting at address. An optional fourth argu-ment, count, can modify the number of objects.
Definition: mw [.b, .w, .l] <address> <value>
Example: In this example, the mw command writes the value 0xabba three times, starting at the physical address 0x80000.
nmThe nm command modifies a single object repeatedly. Once started, the command line prompts for a new value at the selected address. After a new value is entered, pressing ENTER modifies the value in memory and displays the new value. Then the command line prompts for a new value to be written at the same address. Pressing ENTER without enter-ing a new value does not change the original value. To exit the nm command, enter a non-valid hexadecimal value (such as x), followed by ENTER.
10005594-02 Katana®3752 User’s Manual 12-13
Monitor: Flash Commands
Definition:
FLASH COMMANDS
The flash commands affect the flash devices on the Katana®3752 circuit board, which has up to two flash banks. The following commands access the individual banks as Flash Bank 1 (socketed flash) or Flash Bank 2 (soldered flash). For access to the individual sectors within each bank, sector numbers start at 0 and end at one less than the total number of sectors in the bank. For a flash bank with 128 sectors, the following flash commands access the indi-vidual sectors as 0 through 127.
cpThe cp command can copy data into the flash device. Please refer to “cp” on page 12-12 for details.
eraseThe erase command erases the specified area of flash memory.
Definition: Erase all of the sectors in the address range from start to end.
Erase all of the sectors SF (first sector) to SL (last sector) in Flash Bank # N.
erase N:SF[-SL]
Erase all of the sectors in Flash Bank # N.
erase bank N
Erase all of the sectors in all of the flash banks.
erase all
flinfoThe flinfo command prints out the flash device’s manufacturer, part number, size, number of sectors, and starting address of each sector.
Definition: Print information for all flash memory banks.
flinfo
Print information for the flash memory in bank # N.
flinfo N
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Monitor: EEPROM / I2C Commands
protectThe protect command enables or disables flash sector protection for the specified sector. If the flash device complies with the Common Flash Memory Interface (CFI) specification, the command uses the protection mechanism in the physical device. Otherwise, protection is implemented in software only. (Typically, the soldered flash is CFI-compliant, while the socketed flash is not.)
Definition: Protect all of the flash sectors in the address range from start to end.
protect on start end
Protect all of the sectors SF (first sector) to SL (last sector) in Flash Bank # N.
protect on N:SF[-SL]
Protect all of the sectors in Flash Bank # N.
protect on bank N
Protect all of the sectors in all of the flash banks
protect on all
Remove protection on all of the flash sectors in the address range from start to end.
protect off start end
Remove protection on all of the sectors SF (first sector) to SL (last sector) in Flash Bank # N.
protect off N:SF[-SL]
Remove protection on all of the sectors in Flash Bank # N.
protect off bank N
Remove protection on all of the sectors in all of the flash banks.
protect off all
EEPROM / I2C COMMANDS
This section describes commands that allow you to read and write memory on the serial EEPROMs and I2C devices. Most commands use the following flags determine the length of the address offset, in bytes:
.0 zero bytes (for temperature sensors)
.1 one byte (for the real time clock)
.2 two bytes (for the serial EEPROMs)
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Monitor: EEPROM / I2C Commands
eepromThe eeprom command reads and writes from the EEPROM. For example:
eeprom read 53 100000 1800 100
reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 (right-shifted 7-bit address) and places it in memory at address 0x100000.
Definition: Read/write cnt bytes from devaddr EEPROM at offset off.
eeprom read devaddr addr off cnteeprom write devaddr addr off cnt
icrc32The icrc32 computes a CRC32 checksum.
Definition: icrc32 chip address[.0, .1, .2] count
iloopThe iloop command reads in an infinite loop on the specified address range.
Definition: iloop chip address[.0, .1, .2] [# of objects]
imdThe imd command displays I2C memory. For example:
imd 53 1800.2 100
displays 100 bytes from offset 0x1800 of I2C device 0x53 (right-shifted 7-bit address).
Definition: imd chip address[.0, .1, .2] [# of objects]
immThe imm command modifies I2C memory and automatically increments the address.
Definition: imm chip address[.0, .1, .2]
imwThe imw command writes (fills) memory.
Definition: imw chip address[.0, .1, .2] value [count]
inmThe inm command modifies I2C memory, reads it, and keeps the address.
Definition: inm chip address[.0, .1, .2]
Katana®3752 User’s Manual 10005594-0212-16
Monitor: Environment Commands
ipmifirmloadThe ipmifirmload command reloads the IPMI controller firmware from an image held in the monitor image. The optional boot and run arguments specify to reload the firmware from an image held in memory.
Definition: ipmifirmload [boot <boot_image_addr>] [run <runtime_image_addr>]
iprobeThe iprobe command probes to discover valid I2C chip addresses.
Definition: iprobe
ENVIRONMENT COMMANDS
The monitor uses on-board, non-volatile memory to store environment parameters as ASCII strings with the following format:
<Parameter Name>=<Parameter Value>
The monitor uses some environment variables for board configuration and identification. Refer to “Environment Variables” on page 12-23 for a list of monitor environment variables.
envinitThe envinit command resets the NVRAM and serial number. Optional parameters allow you to:
• specify the processor number
• specify the serial number
• retrieve the serial number from the FRU device
• specify parameters not in the default list
Definition: envinit [p1, p2, p3] [serial#, 'fru', 'old'] [env: ...]
printenvThe printenv command displays all of the environment variables and their current values on the console.
Definition: Print the values of all environment variables.
printenv
Print the values of all environment variable (exact match) ‘name’.
printenv name …
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Monitor: Test Commands
saveenvThe saveenv command writes the environment variables to non-volatile memory.
Definition: saveenv
setenvThe setenv command adds new environment variables, sets the values of existing environ-ment variables, and deletes unwanted environment variables.
Definition: Set the environment variable name to value or adds the new variable name and value to the environment.
setenv name value
Removes the environment variable name from the environment.
setenv name
TEST COMMANDS
The commands described in this section perform diagnostic and memory tests.
diagsThe diags command runs the power-on self test (POST).
Definition: diags
mtestThe mtest command performs a simple SDRAM read/write test.
Definition: mtest [start [end [pattern]]]
umThe um command is a destructive memory test.
Definition: um [.b, .w, .l] base_addr [top_addr]
OTHER COMMANDS
This section describes all the remaining commands supported by the Katana®3752 moni-tor.
autoscrThe autoscr command runs a script, starting at address addr, from memory. A valid autoscr header must be present.
Katana®3752 User’s Manual 10005594-0212-18
Monitor: Other Commands
Definition: autoscr [addr]
base The base command prints or sets the address offset for memory commands.
Definition: Displays the address offset for the memory commands.
base
Sets the address offset for the memory commands to off.
base off
boardresetThe boardreset command causes a hard reset to occur by setting the appropriate field in the programmable logic device. When called from processor 1, the hard reset will affect the whole board. When called from processor 2 or 3, the hard reset will affect only that proces-sor unit.
Definition: boardreset
coninfo The coninfo command displays the information for all available console devices.
Definition: coninfo
crc16 The crc16 command computes a CRC16 checksum on size bytes starting at buff. Optionally, it stores the result at addr.
Definition: crc16 buff size [addr]
crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address.
Definition: crc32 address count
echo The echo command echoes args to console.
Definition: echo [args..]
enumpciThe enumpci command enumerates the PCI bus.
Definition: enumpci
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Monitor: Other Commands
fpledoffThe fpledoff command turns off the red front panel LED.
Definition: fpledoff
frugetThe fruget command retrieves and prints the FRU board and product_info fields.
Definition: fruget
frugetuserThe frugetuser command retrieves count bytes from offset in the FRU user area and copies the bytes to storage.
Definition: frugetuser offset count storage
frusetuserThe frusetuser command retrieves count bytes from storage and writes them to offset in the FRU user area.
Definition: frusetuser offset count storage
gethvrThe gethvr command returns the contents of the Hardware Version Register (see Register Map 6-8).
Definition: gethvr
getmonverThe getmonver command prints the monitor version string of the currently running moni-tor (default). Specifying the optional socket or soldered parameter prints the version string for the corresponding device.
Definition: getmonver [socket, soldered]
getsprThe getspr command returns the contents of the SPR register specified by SPR_ID.
Definition: getspr SPR_ID
go The go command runs an application at address addr, passing the optional arguments arg to the called application. If addr is not specified, the environment variable loadaddr is used as the default.
Katana®3752 User’s Manual 10005594-0212-20
Monitor: Other Commands
Definition: go addr [arg…]
helpThe help (or ?) command displays the online help. Without arguments, all commands are displayed with a short usage message for each. To obtain more detailed information for a specific command, enter the desired command as an argument.
Definition: help [command …]
iminfo The iminfo command displays the header information for an application image that is loaded into memory at address addr. Verification of the image contents (magic number, header, and payload checksums) are also performed.
Definition: iminfo addr [addr …]
isdramThe isdram command displays the SDRAM configuration information (valid chip values range from 50 to 57).
Definition: isdram
loop The loop command executes an infinite loop on address range.
Definition: loop [.b, .w, .l] address number_of_objects
memmap The memmap command displays the board’s memory map layout.
Definition: memmap
moninitThe moninit command resets the NVRAM and serial number, and it writes the monitor to flash. Optional parameters allow you to:
• specify the processor number
• specify the serial number
• retrieve the serial number from the FRU device
• specify the source address of a monitor image to copy from
• specify parameters not in the default list
10005594-02 Katana®3752 User’s Manual 12-21
Monitor: Other Commands
Definition: moninit [p1, p2, p3] [serial#, 'fru', 'old'] [src] [env: ...]
pciThe pci command enumerates the PCI bus if the Katana®3752 is the monarch board. It dis-plays enumeration information about each detected device. The pci command allows you to display values for and access the PCI Configuration Space.
Definition: Display a short or long list of PCI devices on the bus specified by bus.
pci [bus] [long]
Show the header of PCI device bus.device.function.
pci header b.d.f
Display the PCI configuration space (CFG).
pci display[.b, .w, .l] b.d.f [address] [# of objects]
Modify, read, and keep the CFG address.
pci next[.b, .w, .l] b.d.f address
Modify automatically increment the CFG address.
pci modify[.b, .w, .l] b.d.f address
Write to the CFG address.
pci write[.b, .w, .l] b.d.f address value
reset The reset command performs a hard reset of the CPU by triggering the hard reset bit in the device bus PLD.
Definition: reset
run The run command runs the commands in an environment variable var.
Definition: run var […]
setsprThe setspr command sets the contents of the SPR register specified by SPR_ID to SDR_Value.
Definition: setspr SPR_ID SPR_Value
Katana®3752 User’s Manual 10005594-0212-22
Monitor: Environment Variables
scriptThe script command runs a list of monitor commands out of memory. the list as an ASCII string of commands separated by the ; character and terminated with the ;; charac-ter sequence. script_address is the starting location of the script.
Definition: script script_address
showmacThe showmac command displays the Processor MAC addresses.
Definition: showmac
showpciThe showpci command scans the PCI bus and lists the base address of the devices.
Definition: showpci
sleep The sleep command executes a delay of N seconds, where N is a decimal value.
Definition: sleep N
version The version command displays the monitor’s current version number.
Definition: version
ENVIRONMENT VARIABLES
The following table lists the standard environment variables for nonvolatile memory.
Table 12-3: Standard Environment Variables
Variable:Default Value: Description:
baudrate 9600 Console baud rate.Valid rates: 9600, 14400, 19200, 38400, 57600, 115200
blinkled true Specify whether or not front panel LED blinks after init.Valid options: true, false
bootcmd – Command(s) to be executed after boot
bootdelay 1 Countdown to bootcmd execute (-1 to disable autoboot)
bootfile – Path to boot file on server (used with TFTP)
10005594-02 Katana®3752 User’s Manual 12-23
Monitor: Environment Variables
cachemode write Sets the L1 cache mode to write-through or copy-backValid options: write, copy
clearmem on Determines if all of SDRAM is cleared on power-up. This option is ignored if ECC is enabled.Valid options: on, off
cpsb_one auto Speed and duplex settings for cPSB port 1Valid options: disable, auto, 10t_half, 10t_full, 100t_half, 100t_full, 1000t_full
cpsb_two auto Speed and duplex settings for cPSB port 2Valid options: disable, auto, 10t_half, 10t_full, 100t_half, 100t_full, 1000t_full
dcache on Initial data cache stateValid options: on, off
ecc on ECC enable/disable (off = disable, on = enable)
enumerate on PCI enumeration if module is PPMC monarch(on = enumerate if monarch, off = never enumerate)
eready on Should we wait for EREADY as a monarch?(off = no, on = yes)
ethport cpsb Specify Ethernet portValid options: portdbg, porta, portb, cpsb, all
eventset clear CPU1 set, clear, or ignore wait signal to CPU2 and CPU3
eventwait wait CPU2 and CPU3 wait or ignore event signal from CPU1
gatewayIP 0.0.0.0 Gateway IP address
icache on Initial instruction cache stateValid options: on, off
initcoprocs true Specify whether processor 1 performs mon_init function for processors 2 and 3 if they do not boot upValid options: true, false, ignore
ipaddr 0.0.0.0 Board IP address
ipmipresent true Specify whether or not to query CMM for chassis IDIf false, board does not access IPMI controller in boot sequence or with getphysloc commandValid options: true, false
l2cache on Turns the L2 cache on or offValid options: on, off
l2mode write Sets the L2 cache mode to write-through or copy-backValid options: write, copy
linkdelay 3000 Time to wait in milliseconds for cPSB ports to get link (indef=wait indefinitely)
Variable:Default Value: Description: (continued)
Katana®3752 User’s Manual 10005594-0212-24
Monitor: Environment Variables
In addition to the standard environment variables, the Katana®3752 monitor supports other variables that allow you to configure the BCM5691 Ethernet switch’s virtual local area network (VLAN) settings. These non-standard variables are: vlan-a, vlan-b, vlan-c, and vlan-d. By default, they are not defined (that is, configured for no VLAN connection). These vari-ables are set using a comma-separated list of port names.
The name assignments are shown in Table 12-4.
Table 12-4: VLAN Port Name Assignments
loadaddr 8000000 Address to which a boot image is loaded
model Katana3750 Board model number
monversion x.x Monitor version number
netmask 0.0.0.0 Board subnet mask
powerondiags on Set post diagnostics on or off
rebootdelay 120 Specify how long in seconds bootcrc command waits to reboot if cached and downloaded images are invalid (must be set manually)
serial# xxxx Board serial number
serverip 0.0.0.0 Boot server IP address
slotid – Specify the board’s slot ID on powerup/reset (set by init code)
stderr serial stderr interface
stdin serial stdin interface
stdout serial stdout interface
tftpblksize – Specify the size, in bytes, for TFTP block transfers; minimum=8 bytes, maximum=1468 bytes(Undefined by default. If not set, the monitor uses 512 bytes. If set, TFTP will use the new value, unless it is overridden by the server.)
tftpport – Specify TFTP server portValid options: 00—65535
Port Name: Description:
BCM5691 Port #: Default VLAN:
proc1_b processor #1, port 1 (port b) 11 VLAN B
proc1_a processor #1, port 0 (port a) 12 VLAN A
proc2_a processor #2, port 0 (port a) 10 VLAN A
proc3_a processor #3, port 0 (port a) 2 VLAN A
cpsb_one cPSB backplane, port 1 5 VLAN A
cpsb_two cPSB backplane, port 2 8 VLAN B
frnt_one front panel RJ45 1 none
Variable:Default Value: Description: (continued)
10005594-02 Katana®3752 User’s Manual 12-25
Monitor: Troubleshooting
To configure a VLAN connection, use the appropriate variable (vlan-a, vlan-b, vlan-c, or vlan-d), followed by a list of port names, separated by commas with no spaces.
For example, to connect the front panel RJ45 to VLAN A, type the following at the monitor command prompt:
[Proc 1]=> setenv vlan-a proc1_a,proc2_a,proc3_a,cpsb_one,frnt_one[Proc 1]=> saveenv[Proc 1]=> reset
To place all ports on VLAN A:
[Proc 1]=> setenv vlan-a proc1_a,proc1_b,proc2_a,proc3_a,cpsb_one,cpsb_two,frnt_one
[Proc 1]=> setenv vlan-b disable[Proc 1]=> saveenv[Proc 1]=> reset
To connect the front panel RJ45 to VLAN B:
[Proc 1]=> setenv vlan-a proc1_a,proc2_a,proc3_a,cpsb_one,frnt_one[Proc 1]=> setenv vlan-b proc1_b,cpsb_two,frnt_one[Proc 1]=> saveenv[Proc 1]=> reset
Note that setting vlan-a does not override the default value for vlan-b, and vice versa. Set-ting a VLAN variable to disable causes the associated VLAN to be disabled. A port may only belong to a single port-based VLAN. The monitor connects the port to the last VLAN that was set, and VLANs are set in alphabetical order.
TROUBLESHOOTING
To bypass the full board initialization sequence, attach a terminal to the console located on the front of the module. Configure the terminal parameters to be:
9600 bps, no parity, 8 data bits, 1 stop bit
Reset the module while holding down the s key. Pressing the s key forces a default console configuration.
DOWNLOAD FORMATS
The Katana®3752 monitor supports binary and Motorola S-Record download formats, as described in the following sections.
BinaryThe binary download format consists of two parts:
• Magic number (which is 0x12345670) + number of sections
Katana®3752 User’s Manual 10005594-0212-26
Monitor: Download Formats
• Information for each section including: the load address (unsigned long), the section size (unsigned long), and a checksum (unsigned long) that is the long-word sum of the memory bytes of the data section
Motorola S-RecordS-Record download uses the standard Motorola S-Record format. This includes load address, section size, and checksum all embedded in an ASCII file.
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Katana®3752 User’s Manual 10005594-0212-28
(blank page)
10005594-02 Katana®3752
Section 13
Acronyms
ASCII American Standard Code for Information Interchange
BMC Baseboard Management Controller
Cmd Command code
COP Common On Chip
cPSB CompactPCI Packet-Switched Backplane
CPU Central Processing Unit
CRT Cathode Ray Tube
CSA Canadian Standards Association
DAC Dual Access Cycles
DDR Double Data Rate
DMA Direct Memory Access
DMC Development Mezzanine Card
EC European Community
ECC Error Checking and Correction
EEPROM Electrically Erasable Programmable Read Only Memory
EIA Electronics Industries Association
EMC Electromagnetic Compatibility
ESD Electrostatic Discharge
ETSI European Telecommunications Standards Institute
FCC Federal Communications Commission
FRU Field Replaceable Unit
GbE Gigabit Ethernet
GNU GNU’s Not Unix
GPIO General Purpose Input/Output
GPL General Public License
HSL Hot Swap Logic
HSR Hot Swap Register
I/O Input/Output
I2C Inter-Integrated Circuit
User’s Manual 13-1
Acronyms:
IDMA Internal Direct Memory Access
IEC International Electrotechnical Commission
IEEE Institute of Electrical and Electronics Engineers
IP Internet Protocol
IPMB Intelligent Platform Management Bus
IPMI Intelligent Platform Management Interface
ISP In-System Programmable
ITP In-Target Probe
JTAG Joint Test Action Group
LED Light-Emitting Diode
LUN Logical Unit Number
MAC Medium/Media Access Control/Controller
MMC Module Management Controller
MPSC Multi-Protocol Serial Controllers
NEBS Network Equipment-Building System
netFn Network Function Code
NVRAM Non-Volatile Random Access Memory
OEM Original Equipment Manufacturer
PCI Peripheral Component Interconnect
PHY Physical Interface
PLD Programmable Logic Device
PLL Phase Locked Loop
PMC PCI Mezzanine Card
POST Power-On Self Test
RMA Return Merchandise Authorization
RTC Real-Time Clock
SDMA Serial Direct Memory Access
SDR Sensor Data Record
SDRAM Synchronous Dynamic Random Access Memory
SEL System Event Log
Katana®3752 User’s Manual 10005594-0213-2
Acronyms:
SERDES Serializer/Deserializer
SGMII Serial Gigabit Media Independent Interface
SMS System Management Software
SO-DIMM Small-Outline Dual In-line Memory
SROM Serial Read Only Memory
TAP Test Access Port
TFTP Trivial File Transfer Protocol
UART Universal Asynchronous Receiver/transmitter
UL Underwriters Laboratories
VLAN Virtual Local Area Network
10005594-02 Katana®3752 User’s Manual 13-3
Katana®3752 User’s Manual 10005594-0213-4
(blank page)
Index
A floating-point exception mode 4-10 L
acronyms . . . . . . . . . . . . . . . . . . .13-1BBCM5691 . . . . . . . . . . . . . . . . . . . . 8-1binary download format . . . . . . .12-26block diagram
750FX . . . . . . . . . . . . . . . . . . . . . 4-2750FX reset. . . . . . . . . . . . . . . . . 3-4Ethernet ports. . . . . . . . . . . . . . . 8-2general system . . . . . . . . . . . . . . 1-3IIC interface . . . . . . . . . . . . . . . . 5-8IPMB . . . . . . . . . . . . . . . . . . . . . . 9-3monitor startup . . . . . . . . . . . .12-5real-time clock . . . . . . . . . . . . . . 7-1system controller . . . . . . . . . . . . 5-2system reset . . . . . . . . . . . . . . . . 3-2
board configuration registers . . . . . 6-5boot commands, monitor . . . . .12-10
Ccache, CPU memory . . . . . . . . . . . . 4-9caution statements
writes to monitor area . . . . . . .12-6circuit board dimensions . . . . . . . . 2-1compliance . . . . . . . . . . . . . . . . . . . 1-4component map
bottom . . . . . . . . . . . . . . . . . . . . 2-4top . . . . . . . . . . . . . . . . . . . . . . . 2-3
configuration registers, PLD . . . . . . 6-5connectors
backplane . . . . . . . . . . . . . . . . .11-1console port . . . . . . . . . . . . . . .4-16front panel . . . . . . . . . . . . . . . . . 2-2front panel Ethernet . . . . . . . . . . 8-4J1 pinout . . . . . . . . . . . . . . . . . .11-1J2 pinout . . . . . . . . . . . . . . . . . .11-2J3 pinout . . . . . . . . . . . . . . . . . .11-3J8 pinout . . . . . . . . . . . . . . . . . . . 8-4JTAG/COP pinouts. . . . . . . . . . .4-13overview . . . . . . . . . . . . . . . . . . . 2-6P1, P5, P6 pinouts . . . . . . . . . . .4-13P2-P4 pinouts . . . . . . . . . . . . . .4-16
contents, table of . . . . . . . . . . . . . . ii-iiiCPU
block diagram. . . . . . . . . . . . . . . 4-2cache memory . . . . . . . . .4-9, 4-11exceptions . . . . . . . . . . . . . . . . . 4-8features. . . . . . . . . . . . . . . . . . . . 4-1
initialization . . . . . . . . . . . . . . . . 4-4customer support
technical support . . . . . . . . . . . . 2-8
Ddebug port, Ethernet . . . . . . . . . . . 8-4Device Bus PLD registers. . . . . . . . . 6-1
Eenumeration. . . . . . . . . . . . . . . . . . 6-4environment commands, monitor . . . . 12-17equipment for setup. . . . . . . . . . . . 2-7ESD prevention . . . . . . . . . . . . . . . . 2-1Ethernet address. . . . . . . . . . . . . . . 8-3Ethernet switch. . . . . . . . . . . . . . . . 8-1
Ffeatures
components . . . . . . . . . . . . . . . . 1-1general . . . . . . . . . . . . . . . . . . . . 1-1
figures, list of . . . . . . . . . . . . . . . . iii-viiflash commands, monitor . . . . .12-14front panel . . . . . . . . . . . . . . . . . . . 2-2
reset switch . . . . . . . . . . . . . . . . 2-2serial port . . . . . . . . . . . . . . . . . . 2-2USB port . . . . . . . . . . . . . . . . . . . 2-2
GGPIO signals . . . . . . . . . . . . . 5-9, 5-10grounding. . . . . . . . . . . . . . . . . . . . 2-1
HHID registers. . . . . . . . . . 4-5, 4-6, 4-7hot swap . . . . . . . . . . . . . . . . . . . . 10-1
Iinstallation of the board . . . . . . . . . 2-7intelligent platform management bus . 9-1interrupts, PLD . . . . . . . . . . . . . . . . 6-3
JJTAG/COP header . . . . . . . . . . . . . 4-13jumper locations. . . . . . . . . . . . . . . 2-5
L2 cache . . . . . . . . . . . . . . . . . . . . 4-11LEDs
front panel . . . . . . . . . . . . . . . . . 2-2
Mmachine state register (MSR) . . . . . 4-9mean time between failures (MTBF)1-4memory
commands, monitor . . . . . . . 12-11EEPROM . . . . . . . . . . . . . . . . . . . 5-7SDRAM . . . . . . . . . . . . . . . . . . . . 5-7user flash . . . . . . . . . . . . . . . . . . 5-6
monitorauto-booting . . . . . . . . . . . . . . 12-1auto-repeat . . . . . . . . . . . . . . . 12-1binary download format . . . . 12-26command syntax . . . . . . . . . . . 12-9environment parameters . . . . 12-17environment variables . . . . . . 12-23flash commands. . . . . . . . . . . 12-14flash programming . . . . . . . . . 12-1memory commands. . . . . . . . 12-11Motorola S-record . . . . . . . . . 12-27other commands . . . . . . . . . . 12-18power-up/reset sequence flowchart 12-5PPCBOOT . . . . . . . . . . . . . . . . . 12-1recovery . . . . . . . . . . . . . . . . . . 12-7start-up display . . . . . . . 12-2, 12-3test commands . . . . . . . . . . . 12-18TFTP booting . . . . . . . . . . . . . . 12-1troubleshooting . . . . . . . . . . . 12-26updates . . . . . . . . . . . . . . . . . . 12-8version number . . . . . . . 2-6, 12-23
monitor commandsautoscr . . . . . . . . . . . . . . . . . . 12-18base . . . . . . . . . . . . . . . . . . . . 12-19boardreset . . . . . . . . . . . . . . . 12-19bootd . . . . . . . . . . . . . . . . . . . 12-10bootelf . . . . . . . . . . . . . . . . . . 12-10bootm . . . . . . . . . . . . . . . . . . 12-10bootp . . . . . . . . . . . . . . . . . . . 12-10bootv . . . . . . . . . . . . . . . . . . . 12-10bootvx . . . . . . . . . . . . . . . . . . 12-11cmp . . . . . . . . . . . . . . . . . . . . 12-11coninfo . . . . . . . . . . . . . . . . . . 12-19cp . . . . . . . . . . . . . . . 12-12, 12-14crc16 . . . . . . . . . . . . . . . . . . . 12-19crc32 . . . . . . . . . . . . . . . . . . . 12-19
10005594-02 Katana®3752 User’s Manual i-1
Index (continued)
diags . . . . . . . . . . . . . . . . . . . .12-18echo . . . . . . . . . . . . . . . . . . . .12-19eeprom . . . . . . . . . . . . . . . . . .12-16enumpci . . . . . . . . . . . . . . . . .12-19envinit. . . . . . . . . . . . . . . . . . .12-17erase . . . . . . . . . . . . . . . . . . . .12-14find . . . . . . . . . . . . . . . . . . . . .12-12flinfo . . . . . . . . . . . . . . . . . . . .12-14fpledoff . . . . . . . . . . . . . . . . . .12-20fruget . . . . . . . . . . . . . . . . . . .12-20frugetuser. . . . . . . . . . . . . . . .12-20frusetuser . . . . . . . . . . . . . . . .12-20gethvr . . . . . . . . . . . . . . . . . . .12-20getmonver . . . . . . . . . . . . . . .12-20getspr . . . . . . . . . . . . . . . . . . .12-20go . . . . . . . . . . . . . . . . . . . . . .12-20help. . . . . . . . . . . . . . . 12-9, 12-21icrc32 . . . . . . . . . . . . . . . . . . .12-16iloop . . . . . . . . . . . . . . . . . . . .12-16imd . . . . . . . . . . . . . . . . . . . . .12-16iminfo . . . . . . . . . . . . . . . . . . .12-21imm . . . . . . . . . . . . . . . . . . . .12-16imw. . . . . . . . . . . . . . . . . . . . .12-16inm . . . . . . . . . . . . . . . . . . . . .12-16ipmifirmload. . . . . . . . . . . . . .12-17iprobe . . . . . . . . . . . . . . . . . . .12-17isdram. . . . . . . . . . . . . . . . . . .12-21loop. . . . . . . . . . . . . . . . . . . . .12-21md . . . . . . . . . . . . . . . . . . . . .12-12memmap . . . . . . . . . . . . . . . .12-21mm . . . . . . . . . . . . . . . . . . . . .12-13moninit . . . . . . . . . . . . . . . . . .12-21mtest . . . . . . . . . . . . . . . . . . .12-18mw . . . . . . . . . . . . . . . . . . . . .12-13nm . . . . . . . . . . . . . . . . . . . . .12-13pci . . . . . . . . . . . . . . . . . . . . . .12-22printenv . . . . . . . . . . . . . . . . .12-17protect . . . . . . . . . . . . . . . . . .12-15rarpboot . . . . . . . . . . . . . . . . .12-11reset . . . . . . . . . . . . . . . . . . . .12-22run . . . . . . . . . . . . . . . . . . . . .12-22saveenv. . . . . . . . . . . . . . . . . .12-18script. . . . . . . . . . . . . . . . . . . .12-23setenv . . . . . . . . . . . . . . . . . . .12-18setspr . . . . . . . . . . . . . . . . . . .12-22showmac . . . . . . . . . . . . . . . .12-23showpci . . . . . . . . . . . . . . . . .12-23sleep . . . . . . . . . . . . . . . . . . . .12-23
tftpboot . . . . . . . . . . . . . . . . .12-11um . . . . . . . . . . . . . . . . . . . . .12-18version . . . . . . . . . . . . . . . . . .12-23
monitor recovery . . . . . . . . . . . . . 12-7monitor updates. . . . . . . . . . . . . . 12-8MV64360 . . . . . . . . . . . . . . . . . . . . 5-1
Nnotation conventions . . . . . . . . . . . 1-5
PPCI
configuration space . . . . . . . . . . 5-4device and vendor ID . . . . . . . . . 5-4interface . . . . . . . . . . . . . . . . . . . 5-4
power requirements. . . . . . . . . . . . 2-7product ID register . . . . . . . . . . . . . 6-4product repair. . . . . . . . . . . . . . . . . 2-9
Rreal-time clock . . . . . . . . . . . . . . . . 7-1
block diagram . . . . . . . . . . . . . . 7-1operation . . . . . . . . . . . . . . . . . . 7-1
references, manuals, and data books . . 1-6regulatory certifications . . . . . . . . . 1-4reset
logic . . . . . . . . . . . . . . . . . . . . . . 3-1registers, PLD . . . . . . . . . . . . . . . 6-1system controller . . . . . . . . . . . . 5-6
reset switch . . . . . . . . . . . . . . . . . . 2-5returning boards. . . . . . . . . . . . . . . 2-9revision registers, PLD . . . . . . . . . . 6-5RoHS . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Sserial number
location . . . . . . . . . . . . . . . . . . . 2-6user ROM . . . . . . . . . . . . . . . . . . 2-6
serial ports, console . . . . . . . . . . . 4-16setup requirements . . . . . . . . . . . . 2-7specifications
environmental . . . . . . . . . . . . . . 2-7mechanical . . . . . . . . . . . . . . . . . 2-1power . . . . . . . . . . . . . . . . . . . . . 2-7
static control . . . . . . . . . . . . . . . . . 2-1system controller . . . . . . . . . . . . . . 5-1
CPU interface . . . . . . . . . . . . . . . 5-2device controller . . . . . . . . . . . . 5-3doorbell registers . . . . . . . . . . . . 5-5features . . . . . . . . . . . . . . . . . . . 5-1IDMA controller . . . . . . . . . . . . . 5-3PCI configuration space . . . . . . . 5-4PCI device and vendor ID . . . . . . 5-4PCI interface registers . . . . . . . . 5-5PCI interfaces . . . . . . . . . . . . . . . 5-4SDRAM controller. . . . . . . . . . . . 5-2timer/counters. . . . . . . . . . . . . . 5-3
system management bus. . . . . . . . 9-1
Ttable of contents . . . . . . . . . . . . . . ii-iiitables, list of . . . . . . . . . . . . . . . . . .iv-ixtechnical references . . . . . . . . . . . . 1-6technical support . . . . . . . . . . . . . . 2-8
contacting . . . . . . . . . . . . . . . . . 1-8terminology . . . . . . . . . . . . . . . . . . 1-5
typographic conventions, monitor . 12-9
test commands, monitor . . . . . . 12-18timer/counters . . . . . . . . . . . . . . . . 5-3troubleshooting
general . . . . . . . . . . . . . . . . . . . . 2-7monitor . . . . . . . . . . . . . . . . . 12-26
UUL certifications . . . . . . . . . . . . . . . 1-5
VVLAN
configuration in monitor . . . . 12-25port diagram . . . . . . . . . . . . . . . 8-2
Wwatchdog timer . . . . . . . . . . . . . . . 5-6
ZZircon PM . . . . . . . . . . . . . . . . . . . . 9-1
Katana®3752 User’s Manual 10005594-02i-2
10005594-02 Katana®3752 User’s Manual
Notes
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