Kamalapurkar ShounakRajarshi SalilJoshi Rohan

Bhavsar SagarPai Sandesh

Low Latency Publisher-Subscriber Network for Stock Market Application

Team WhiteWalkers

Team WhiteWalkers 2

Network

Trader 1(Subscriber)

Trader 3(Subscriber)

Stock Exchange (Publisher)

Intel

Trader 2(Subscriber)

Microsoft

GoogleGoogle- <stock price>

Companies SubscriberIntel Subscriber 1

Microsoft Subscriber 3Google Subscriber 2

Microsoft - <stock price>

Publisher- Subscriber Network

SUBSCRIBER PACKET SUBSCRIBER

PACKET

PUBLISHER PACKET

PhysicalData LinkNetwork

TransportSession

Presentation

Application

Publisher

Trader # 1

Software based Deep Packet Inspection- DPI solution

High Latency

Not suitable for real-time applications

Unhappy Stock Brokers

• Software based DPI• Update Destination Address

Trader # 3

Trader # 2

Router

Problems?

Publisher

PhysicalData LinkNetwork

Hardware based DPI solution

• DPI with Hardware Accelerators

• Update Destination Address

Trader # 1

Trader # 3

Trader # 2

Router

Performance Evaluation

• *Performance Improvement in Hardware: > 10 X

*Reference: Lockwood, “A low latency library in FPGA for High Frequency Trading”

• Our Method To Test:

Open Source DPI software Tool vs Our Processor

Perf

orm

ance

HW SW

10X

vs

6

Input Arbiter Output Lookup

Input queues Output queue

Processor

High System Overview

Core 1

InputArbiter

OutputArbiter

Header- Checksum

Core 2

Comparator

Header-ChecksumComparator

I am IDLE

I am IDLE

Which core is IDLE

OK! Send to CORE1 BUSYSend to CORE 2

BUSY

DONE!

DONE!

Processor Design

Source IP Destination IP

Payload

CAM

KEYWORDS

PROCESSOR

New Destination

Payload

New Checksum

Send Payload To Comparator

Inspect the Data

Send New IP Address To Checksum Gen

Calculate New Checksum

Send The Packet

Hardware Accelerator Checksum

Comparator

NewChecksum

RegisterFile

Data Mem

PC 0

PC 1

Control

InsMem

ThreadSelect

Example Instruction

R1

R2

R1+R2

R3

ALUADD R3,R2,R1

HardwareAccelerator

Match Found!Update packet

Special Load WordAdd Instruction

10

Description Completion Date

Phase 1 Single Core Multi-Threaded 04/07

Phase 2 Multi-core Multi-Threaded 04/14

Phase 3 Integration with Hardware Accelerators

05/05

Phase 4 Testing and Debugging 05/12

Project Schedule

11

Thank You!