jtag port sdram 32m to 64m byte buffer sdram ac97 inteface...

2. PXA 255 CPU : Xscale

Target Block DiagramJTAG Po rt

JF la s h / M u lt i IC ESD RAM

3 2 M to 6 4 M B yte

SRAM1 M B yte

FLASH1 6 M to 3 2 M B yte

PS2 Ke yB o ard # 1PS2 M o u s e # 1

B U FFER

M M C / SD So c ke t # 1 SPI

IrD A M o d u le # 1 IrD A

Fu ll U ART So c ke t# 1 F u ll U ART

B U FF ER

AD S7 8 4 6

SD RAM1 0 0 M h z

PXA2 5 5 -4 0 0 M h z

XSc a le C o re

B U F FER

AC ’ 9 7 C o d e cC S4 2 0 2

AC 9 7 In te f a c e

M M C / SD So c ke t # 1

C h a ra c to r LC DD is p lay # 1

B U F FER

PC M C IASo c ke t # 1

LED D is p lay * 8

C o m p a c t F la s hSo c ke t # 1

7 Se g m e n tH EX D is p la y

PU SH B u t to nSw itc h * 8

B U F FER

B U F FER

B U F FER

B U F FER

B U F FER

TF T C o lo r LC D6 4 0 * 4 8 0 ( 6 . 4 ")

B U FFER

B

UFFE

R

Exp a n s io n Po rtS lo t # 1

Se c o n d ary E th e rn e tLAN 9 1 C 1 1 1

Prim a ry Eth e rn e tLAN 9 1 C 1 1 1

Fu ll U ART So c ke t# 1

B lu e to o th U ART # 1

F u ll U ART

B lu e to o th

U SB S la ve # 1 U D C

To u c hSc re e n

6 . 4 "

AD S7 8 4 6

Re a l T im e C lo c kRTC 4 5 1 3

I2 C EEPRO MN M 2 4 C 1 6

G PIO

I2 C

I2 C B U SC o n n e c to r # 1

I2 C

Platform Specification (1)items specification

CPU Intel XScale PXA255 400Mhz

Memory SDRAM Samsung 64Mbyte

Flash Intel strata Flash 32Mbyte

LCD LG TFT LCD 6.4” (640××××480)

주변장치주변장치주변장치주변장치

Touch Screen ADS7846, 4 wire Touch Interface

Serial FF_UART, BT_UART

USB USB 1.1 Slave

Ethernet LAN91C111 (10/100Base-T)

JTAG 74LCX245

IrDA ST_UART, HDSL3600

Audio AC97 Stereo Codec, CS4202

Platform Specification (2)items specification

주변장치주변장치주변장치주변장치

PCMCIA 1 slot

CF 1 slot

RTC Real Time Clock Module, RTC4513

TEXT LCD 20××××2 TEXT LCD Module

Button Push Button ××××8(Bus Control)Button Push Button ××××8(Bus Control)

LED Discrete LED×××× 8, 7Segment LED ××××4

Interface

Extend connector 120 pin

LCD Connector 30 pin

Inverter connector 5 pin

Touch connector 4 pin

JTAG connector 20 pin

Power connector 4 pin

PXA 255 Processor CPU Overview• High Performance 32-bit Microprocessor, max 400MHz• Technology

• 0.35um, 3 layer metal CMOS, 2.6 Million transistors• 256 PBGA package (17x17mm)

• XScale core, ARMv5TE 기반• Modified-Harvard Architecture 가 적용된 ARM 프로세서• Modified-Harvard Architecture 가 적용된 ARM 프로세서

• Separate instruction/data cache : 32Kbytes• 2Kbyte mini data/instruction cache

• Instruction & data Memory Management Units (MMU)• Debug capability via JTAG port

System Integration Feature• Memory control• Clock an power control• USB client interface• DMA controller• LCD controller• AC97(audio codec 97)• I2S (Inter-IC Sound Controller)• Multimedia Card Controller• FIR (Fast Infrared) communication port• Multimedia Card Controller• FIR (Fast Infrared) communication port• Synchronous Serial Protocol Port• I2C(Inter-Integrated Circuit) Bus Interface Unit• General Purpose I/O pins (GPIO)• UARTs (Universal Asynchronous Receiver/Transmitter)

• Full/Bluetooth/standard/hardware• Real-Time clocks• OS timers• PWM (Pulse Width Modulation)• Interrupt Control• Network Synchronous Serial Port : other ASIC interface

Palm Size Device : System Example

Intel®XScale

PX255

Portable

Communications

UARTCommunications

Tablet/ SerialKeyboard

AC97

TFT ColorLCD

Display

Speaker

Microphone

3.686MHz Communications

Microprocessor InfraredCommunications

USB Synchronization Port

SDRAM/DRAM

SMROM/ROM

Flash ROM

Glue Logic

SRAM

Variable Latency I/O

PCMCIA Interface(Flash, Modem)

3.686MHz

32.768KHz

PXA 255 CPU Functional BlockColor or GrayscaleLCD Controller

RTC

OS Timer

PWM(2)

InterruptController

Clock &Power Man.

I2S

MemoryController

General Purpose I / O

Peripheral Bus

System Bus

DynamicMemoryControl

SDRAM/SMROM4 banks

DMA Controller and Bridge

0x4400_0000PCMCIA& CFControl

XCVR

Socket 0, 1

ASIC

I2C

AC97

FF_UART

BT_UART

Slow lrDA

Fast lrDA

SSP

VariableLatencyI/O

Control

StaticMemoryControl

General Purpose I / O

Peripheral Bus

3.6864 MHzOsc

32.768 KHzOsc

ROM/FlashSRAM4 banks

MemoryControl 4 banks

DMA Controller and Bridge

CS #0,1,2

CS #3,4,5XScaleCore

IMMU

DMMU

Icache(32 Kbytes)

Dcache(32 Kbytes)

Minicache

Instructions

PC

Addr

WriteBuffer

ReadBuffer

Load/Store Data

MegacellCore

NSSP

USBClient

MMC

Xscale Core Architecture ARM Core General Register & PC

PXA 255 CPU Registers• Xscale Core(ARMv5TE ) Registers

• ARM state general registers: 6 groups, 90 registers

• ARM state program status registers : 6 groups, 11 registersgroups, 11 registers

• System Control Register for Memory Mapped registers Interface• 20 fields about 380 registers

System Control Register• Example DMA controller

PXA 255 Micro-ArchitectureBranch Target Buffer

TraceBuffer

InstructionCache

CP 15 Config

Registers

CP 14 PerformanceMonitoring

IRQ FIQ

Interrupt

Request

Instruction Core Memory BusCache

32KBytes

Data Cache32 KBytes

Mini D-Cache2 KBytes

MMU

MMUWriteBuffer

SystemManagement

DebugJTAG

CP0 Multiplier /

Accumulator

Coprocessor Interface

Execution

Core

Data

Address

Data

Bus

Mini I-Cache2 KBytes

XScale Core Architecture Features

InstructionCache32 Kbytes 32 Ways Lockable by line

Micro-Processor7 Stagepipeline

Data CacheMax 32 Kbytes32 waysWR-Back or WR-ThroughHit under miss

Data RAMMax 28 KbytesRe-map of data cache

Branch TargetBuffer

IMMU32 entry TLB

DMMU32 entry TLB

Fill Buffer4~8 entries

Mini-DataCache2 Kbytes2 ways

DebugHardware BreakpointsBranch History Table

MACSingle cycle Throughput (16*32)16-bit SIMD40-bit accumulator

PowerMgntControl

Write Buffer8 entriesFull coalescing

JTAG

Buffer128 entries

32 entry TLBFully associativeLockable by entry

32 entry TLBFully associativeLockable by entry

4~8 entries

PerformanceMonitoring

Arm Instruction Set Format PXA 255 Instruction Operation• XScale Core

• 32Bit RISC• 32Bit registers• 32Bit instructions: Longword aligned• 32Bit data paths• 7~8 stage pipeline

Register FileOperandShifter

InstructionFetch1 PC

PC - 12

InstructionFetch2 PC - 4

InstructionDecode PC - 8

F1

RF

F2

ID

• 7~8 stage pipelineALU

Execute

Shifter

WriteBack

StateExecute

PC - 12

PC - 16

Data CacheAccess

Data CacheAccess

Data CacheWriteback

MultiplierStage1

MultiplierStage X

MultiplierStage2

RF

X1M1

M2

Mx

X2

XWB

DWB

D2

D1

MAC pipeline

Main executionpipeline

Memory pipeline

Memory Map

Memory Mapped registers Interface

Dynamic Memory Interface 256 Mbytes

SDRAM Bank 3 (64 Mbytes)




Memory Mapped registers (LCD)

0hA000 0000

0h4800 0000

0h4C00 0000

0hA800 0000

0hA400 0000

0hAC00 0000

0hB000 0000

Reserved (1280 Mbytes)

Memory Mapped registers (Memory Control)

Reserved (1344 Mbytes)

0hFFFF FFFF

Static Memory Interface (ROM, Flash,SRAM) 384 Mbytes

PCMCIA Interface 512 Mbytes

Memory Mapped registers Interface192 Mbytes

Memory Mapped registers (LCD)

PCMCIA/CF - Slot 1(256 Mbytes)

PCMCIA/CF - Slot 0(256 Mbytes)

Static Chip Select 3 (64 Mbytes)



Static Chip Select 0 (64 Mbytes)0h0000 0000

0h1000 0000

0h2000 0000

0h3000 0000

0h4000 0000

0h4400 0000

0h0400 0000

0h0800 0000

0h0C00 0000

0h1800 0000Reserved (128 Mbytes)


Static Chip Select 4 (64 Mbytes)0h1400 0000

Memory Mapped registers (Peripherals)

PXA 255 Internal Register• DMA controller• UART: Full function, Bluetooth• I2C• I2S• AC97• UDC• UART: standard

• SSP• MMC Controller• Clocks Manager• Network SSP• Hardware UART• LCD Controller• Memory Controller• UART: standard

• ICP• RTC• OS timer• PWM0, PWM1• Interrupt Control• GPIO• Power Management & Reset Control

• Memory Controller

• Total : 21 fields• about 380 registers

PXA 255 Functional diagram

Serial Channel 4(CODEC)

Serial Channel 0 (USB)

Serial Channel 1

Serial Channel 2 (IrDA)

Serial Channel 3 (UART)

UDC-

UDC+

RXD_1

TXD_1

RXD_2

TXD_2

RXD_3

TXD_3

TXD_C

RXD_C

SCLK_C

SFRM_C

BATT_FAULT

L_DD(15:0)

L_FCLK

L_LCLK

L_PCLK

L_BIAS

GP(27:0)GPIO PortsnCAS/ DQM(3:0)

nSDRAS

RDY

nCS(5:0)

nWE

nOE

nRAS/ nSDCS(3:0)

LCD Control

Memory Control

Intelⓡⓡⓡⓡ

Power Management

Clocks, Reset and Test

JTAG

BATT_FAULT

VDD_FAULT

PWR_EN

TCK_BYP

TESTCLK

PEXTAL

PXTAL

TEXTAL

TXTAL

nRESET

nRESET_OUT

SMROM_EN

ROM_SEL

TCKTDITDOTMS

nTRST

SDCLK<2:0>

SDCKE<1:0>nSDCAS

nSDRAS

RD/nWR Transceiver Control

nPOE

nPCE<2:1> nPIOW nPIOR nPWE

VDD

nIOIS16 nPWAIT nPREG PSKTSEL

VSS/VSSX VDDX

PCMCIA Bus Signals

Supply

A<25:0>

D<31:0> Data Bus

Address Bus

IntelⓡⓡⓡⓡXScale*PXA 250[256-pins]

PXA 255: Memory Model

CoreOn-chipCaches

MMU

Buffers

Memory

Virtual AddressesPhysical Addresses

Buffers

MemoryController

Refer: http://www.intel.com/design/pca/prodbref/252780docs.htm

PXA 255 BUS Read Operation• Cache line fills read 8 words• Read allocate• Round robin replacement

SystemMemory

PXA255

32KB PC

Instruction

Core ClockHalf Core Clock

D[0:31]

hit

XScaleCore

32KBI- Cache

MemoryController

32KBD-Cache

PC

Addr

32 bytes

Data

System BusExternal Bus

I-MMU

D-MMU

ReadBuffer

A[0:31]A[0:25]

D[0:31] D[0:31]

D[0:31]

A[0:31]

A[0:31]

VA[0:31]

VA[0:31]

Instructions&

DataMemory

hit

miss

miss

PXA 255 BUS Writes• No write to I-Cache• Write Back D-Cache• Software coherency needed between caches• Not write allocate

PXA255Core ClockHalf Core Clock

A[0:31]System

XScale

CoreMemoryController

32KBD-Cache Addr

32 bytes

Data

System BusExternal Bus

D-MMU

WriteBuffer

(8 entries)

A[0:31]A[0:25]

D[0:31] D[0:31]

D[0:31]

A[0:31] VA[0:31]

Data

Dirty Bits

SystemMemory

PXA 255: Instruction Cache• 32Kbytes Instruction Cache

• 1,024 lines of 32 bytes(8 words)• Uses the virtual address• 32-way 32-set associative• Round-Robin replacement• Mapped via MMU page C-bits Data

PC

Address

Instructions

IMMU

DMMU

32 KbyteI-cache

Main D-cache

Mini-D-cache

XScaleCore

• MMU - enable 경우: memory management table의 C-bit에 의해서제어• MMU - disable 경우: 모든 address에 대하여 C=1• C=1 or MMU - disable 경우: miss

• 8word의 line fetch가 수행이 되어 round-robin replacement에 의해서 cache bank가 대치• MMU - enable, C=0 경우: virtual address에 해당하는 외부 메모리에서 single word를 읽어오고, cache에 쓰여지지 않음.

PXA 255 Data Cache• 2 Data Caches: Main Data Cache, Mini Data Cache• Both: write back, read allocate, virtual• Mapped via MMU page B, C-bits

• Main Data Cache: 32KB PC

Instructions

IMMU32 KbyteI-cache

Main D-cache

XScaleCore• Main Data Cache: 32KB

• 32-way 32-set associative• Round-Robin replacement• B=1 & C=1

• Mini Data Cache: 2KB• 2-way set associative • Least Recently Used (LRU) replacement• B=0 & C=1

Data

AddressDMMU

Main D-cache

Mini-D-cache

Core

PXA 255 Read Buffer• PXA 255 Read Buffer

• Data prefetcher

– saves processor waiting

– load & calculate in parallel

– for Read-Only data

– supplements the data cache

PC

Instructions

I-cache

D-cache&

XScaleCore

– supplements the data cache

• Under software control

– Coprocessor 15, register #9

– 4 entries, 32 bytes each

– Loads of 1, 4, 8 words

– Replace or invalidate data

Data

Address

D-cache&

mini-D-cache

Write Buffer

128 byteReadBuffer

System Bus

PXA 255 Memory Management

Virtual Addresses SpacePhysical Addresses Space

SystemMemory

I-Cache

PXA255MMU

VAPAAC32

ITLB

D-Cache

XScaleCore

Instructions

Data

Descriptors

I-CacheVAPAAC

VAPAACB

DTLB

TLB Miss

Translation TableBase Register

PXA 255 Coprocessor15• CP15 Register transfer instructions

cond 1 1 1 0 CRm

31 28 27 2423 21 20 19 1615 12 11 8 7 5 4 3 0

0 0 0 CRn Rd 1 1 1 1 Cop2 1L

load from coprocessor/store to coprocessor

MCR P15, 0, Rd, CRn, CRm, Cop2

PXA 255 CP15 Register structure

• CP15 Register structureRegister Purpose0 ID Register1 Control2 Translation Table Base3 Domain Access Control5 Fault Status5 Fault Status6 Fault Address7 Cache Operations8 TLB Operations9 Read Buffer Operations10 TLB lockdown13 Process ID Mapping14 Debug Support15 Test & Clock Control4,11~12 UNUSED

PXA 255 CP15 registerimplementer revision

31 24 23 16 15 4 3 0

part number (BCD)0 0 0 0 0 0 0 AC0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M

31 15 1413 12 1110 9 8 7 6 5 4 3 2 1 0

I Z F R S B L D P W C AVRRC1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 14 13 0

translation table base addressC2

D0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D3 D2 D1D4D7 D6 D5D8D11 D10 D9D12D15 D14 D13C3

C5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 status

31 9 8 7 4 3 0

domain0

fault address

31 0

C6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 2524 0

process IDC13

Grouping of PXA 255 System Register• System Control: clock manager, reset/power manager (CP14)• System Integration: GPIO, interrupt, RTC, OS timer, PWM• DMA Controller• Memory Controller• LCD Controller• SSPC• I2C bus unit• I2C bus unit• UARTs• Fast Infrared communication port• USB device controller• AC’97• I2S• Multimedia controller• NSSP• Hardware UART

System Control Module of PXA 255• Power management controller

• Supporting normal, idle and sleep modes• General purpose I/O ports: 80 ports

• Generate FIQ, IRQ, “wakeup” interrupts• Interrupt controller

• Routes all system (GPIOs, LCD, Serial Channel) interrupts to either IRQ or FIQ• Multi-channel DMA controller• Multi-channel DMA controller

• Software programmable to any serial port and LCD• Supporting External DMA

• Real time clock and timer• 32 bit counter/comparator• 32.7 kHz crystal: accuracy +/- 5 sec/month

• OS timer with alarm register• 32 bit counter/comparator• 3.68 MHz crystal: fine grain timing interrupts

Running mode of PXA 255Hardware Reset

RUN

Power on, nRESET asserted

nRESET asserted

nRESET assertednRESETnegated nRESET

asserted

SLEEP

IDLE

RUN

Wait for interruptinstruction Force sleep bit set, or VDD

or battery fault pins asserted

System orperipheral unitinterrupt

GPIO or RTCalarm interrupt

VDD or battery fault pins asserted

CPU clock held low, all otherresources active, wait for interrupt Wait for wake-up event

Power and Battery Faults (1)• Battery fault

• Battery removed or dangerously low• Power fault

• VDD is lost or out of regulation• Caused by shorted PCMCIA card

• Intel® PXA255 sleep mode• Intel® PXA255 sleep mode• During wakeup sequence if Batt_Fault or VDD_Fault asserts

• Wakeup events ignore• if Batt_Fault asserted when Sleep results from a ‘fault’ state

• All wakeup sources are ignored besides GPIO[0,1]

Power and Battery Faults (2)• Idle: Low Power Modes

• CPU halted but MEMC and peripherals running• Idle mode wakeup ~150uS • Interrupt or timer expiring exit device from Idle• If battery fault/power fault occur during Idle, Intel® PXA255 transitions to Sleep• No processor state lost : Program flow resumes where Idle mode was enteredentered

• Sleep: Low Power Modes• Power_EN pin negated by Intel® PXA255 to alert system to drive VDD to 0V• Sleep entered when Batt_fault, Power_fault or Sleep bit asserted• CPU, MEMC, peripherals receive no clocks

• MEMC puts DRAM in self refresh state before fully entering sleep• Power consumed in Sleep < 50uA

• Must disable 3.68MHz oscillator. Wakeup time ~150mS• GPIO, timer expiring, peripheral causing interrupt can start wakeup sequence

Power and Battery Faults (3)• Sleep : Low Power Modes

Power Manager Control Register (PMCR)

• IDEA<0> (Imprecise Data Abort Enable) • 0 = nVDD_FAULT 또는 nBATT_FAULT가 나타났을 때 Sleep mode에

즉시 들어가는 것을 허용• 1 = nVDD_FAULT 또는 nBATT_FAULT가 나타났을 때 sleep mode에

들어가는 것을소프트웨어적으로 CPU에 부정확한 data 정지 시그널을강제적으로 인가

• PMCR register• PMCR register

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

IDAE

Power Manager General Configuration Register

• PCFR (Power Manager General Configuration Register)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FPFSReserved

• OPDE [0] 3.6864MHz oscillator power-down enable• FP [1] Float PCMCIA controls during Sleep Mode• FS [2] Float Static Chip Selects during Sleep Mode

OPDE

Clock32.768K

RTC

32.768K

PWR_MGR

3.6864

PWM

3.6864

SSP

3.6864

GPIO

3.6864

OST

CPU

CORE

MEM

32.768

KHz

/1 /112

100-400

MHz

PLL*

/NL

1 0 1

0

OSCC, OON

CCLKCFGcp14 c6.1 : turbo

MEM

Controller

LCD

Controller

USB

47.923

FICP

47.923

12C

31.949

MMC

19.169

UARTs

14.746

AC97

12.288

12S

5.672

KHz

OSC

3.6864

MHz

OSC

PLL*

147.46

MHz

PLL

95.846

MHz

PLL

DMA /

Bridge

/M/2/4

RETAINS POWER IN SLEEP PXbus

CCCR

Core PLL Output Frequencies

50298.6

@1.1 v

199.1

@1.0 V

ㅡㅡㅡㅡ99.5

@1.0 V127

3.002.001.501.00

(Run)

SDRAM

max Freq

MEM, LCD

Frequency

(MHz)

PXbus

Frequency

Turbo Mode Frequency (MHz) for Values “N” and Core Clock Configuration Register (CCCR[15:0])

Programming for Values of “N”:ML

99.5 99.5

196ㅡㅡㅡㅡ

398.1

@1.3 V

298.6

@1.1 v

398.1

@1.3 V

427

165.9ㅡㅡㅡㅡㅡㅡㅡㅡ331.8

@1.3 V245

132.7ㅡㅡㅡㅡㅡㅡㅡㅡ265.4

@1.1 V236

66ㅡㅡㅡㅡ

199.1

@1.0 V227

@1.1 [email protected] [email protected] V

36 1 132.7

@1.0 V

ㅡㅡㅡㅡ

ㅡㅡㅡㅡ

ㅡㅡㅡㅡ

ㅡㅡㅡㅡ

ㅡㅡㅡㅡ

ㅡㅡㅡㅡ

99.5

99.5

165.9

132.7

132.7

99.5

99.5

83

66

66

99.5

Core Clock Configuration Register(1)

• CCCR(Core Clock Configuration Register)

• N[9:7] Run Mode Frequency 에서 Turbo Mode Frequency 로 변환하기 위해서

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LMNReserved

• N[9:7] Run Mode Frequency 에서 Turbo Mode Frequency 로 변환하기 위해서곱하는 수, Turbo Mode Freq. = Run Mode Frequency * N

000 , 001 , 101 , 111 – Reserved001(Multiplier) = 1011(Multiplier) = 1.5100 (Multiplier) = 2110 (Multiplier) = 3

• Hardware Reset , Watchdog Reset 이 되면 010 값이 default가 된다.• Turbo Mode Freq(398.1MHz) = Run Mode Freq(199.1MHz) * N(2)


• M [6:5]: Memory Frequency에서 Run Mode Frequency로 변환하기 위해서곱하는 수Memory Freq = Crystal Frequency * L

00 , 11 – Reserved01(Multiplier) = 1(Multiplier가 1이면 Run Mode Freq와 Memory

Frequency가 같다.)10(Multiplier) = 2(Multiplier가 2이면 Run Mode Freq가 Memory

Frequency의 2배가 된다.)Frequency의 2배가 된다.)

• Hardware Reset , Watchdog Reset 이 되면 10 값이 default가 된다.• Memory Freq(99.5MHz) = Crystal Frequency(3.6864MHz) * L(27)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LMNReserved


• L<4:0>: Crystal Frequency에서 Memory Frequency로 변환하기위해서 곱하는 수 (3.6864MHz Crystal을 사용)00000 , 00110 to 11111 – Reserved00001(Multiplier) = 27 (Memory Freq는 99.53MHz가된다.)00010(Multiplier) = 32 (Memory Freq는 117.96MHz가된다.)00011(Multiplier) = 36 (Memory Freq는 132.71MHz가된다.)00011(Multiplier) = 36 (Memory Freq는 132.71MHz가된다.)00100(Multiplier) = 40 (Memory Freq는 147.46MHz가된다.)00101(Multiplier) = 45 (Memory Freq는 165.89MHz가된다.)

• Hardware Reset , Watchdog Reset 이 되면 00001 값이 default가 된다.

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LMNReserved

Clock Enable Register: CKEN• CKEN0 [PWM0]• CKEN1 [PWM1]• CKEN2 [AC97]• CKEN3 [SSP]• CKEN4 [HWUART]• CKEN5 [STUART]• CKEN6 [FFUART]• CKEN7 [BTUART]• CKEN8 [I2S]• CKEN9 [NSSP]• CKEN11 [USB]

* All Unit Clock Enable Bit;

0 – Clock disable1 – Clock enable

• CKEN11 [USB]• CKEN12 [MMC]• CKEN13 [FICP]• CKEN14 [I2C]• CKEN15 [LCD]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1

Reserved

C

K

E

N

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C

K

E

N

1

C

K

E

N

2

C

K

E

N

3

r

e

s

e

r

v

e

d

C

K

E

N

5

C

K

E

N

6

C

K

E

N

7

C

K

E

N

8

C

K

E

N

11

C

K

E

N

12

C

K

E

N

13

C

K

E

N

14

C

K

E

N

16

r

e

s

e

r

v

e

d

r

e

s

e

r

v

e

d

r

e

s

e

r

v

e

d

Oscillator Configuration Register: OSCC

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

OOK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OON

• OSCC는는는는 32.768MHz Oscillator의의의의Configuration을을을을Control하는하는하는하는Register이다이다이다이다.• Oscillator가가가가동작되었을때동작되었을때동작되었을때동작되었을때안정화가안정화가안정화가안정화가되는데는되는데는되는데는되는데는 10초가초가초가초가걸린다걸린다걸린다걸린다. Oscillator가가가가안정화안정화안정화안정화되면되면되면되면OOK bit가가가가 1로로로로

set된다된다된다된다.set된다된다된다된다.OON [1] Write-once only bit

0 = 32.768MHz Oscillator 사용불가능사용불가능사용불가능사용불가능

이때이때이때이때RTC 와와와와 Power Manager 의의의의 Clock은은은은3.6863MHz Oscillator의의의의값이값이값이값이공급된다공급된다공급된다공급된다.(112로로로로나누어진나누어진나누어진나누어진값값값값) ☞☞☞☞ Page 3-3 의의의의 Figure 3-1 Clocks Manager Block Diagram 참고참고참고참고1 = 32.768KHz Oscillator 사용가능사용가능사용가능사용가능

이이이이비트는비트는비트는비트는Hardware Reset으로만으로만으로만으로만Clear가가가가된다된다된다된다.

OOK [0] Read-only bit0 = OON bit가가가가 0 이거나이거나이거나이거나Oscillator가가가가안정화안정화안정화안정화되지되지되지되지않았을않았을않았을않았을경우경우경우경우

1 = OON bit가가가가 1 로로로로 set 되고되고되고되고Oscillator가가가가안정화안정화안정화안정화되었을되었을되었을되었을경우경우경우경우

RTC 와와와와 Power Manager의의의의Clock은은은은 32.768KHz Oscillator의의의의Clock을을을을사용사용사용사용이이이이비트는비트는비트는비트는Hardware Reset으로만으로만으로만으로만Clear가가가가된다된다된다된다.

General Purpose I/O• GPIO[58:73] = dual panel color or 16 bit parallel input on LCD

• GPIO[23:27] = SPI if both synchronous serial protocols are required in a single system

• Modem control signals for UART (CTS, RTS, CD, etc) implemented via GPIO signalsimplemented via GPIO signals

• 4-5 GPIOs required for full PCMCIA support• 3 GPIOs required for Intel® SA-1111 Interface

General Purpose I/O Block Diagram

Pin DirectionRegister(GPDR)

Alternate FunctionRegister(GAFR)

Pin Set Registers(GPSR)0

1

Alternate Function(Output)

Pin Clear Registers(GPCR)2

3

2

0x40E0_000C/10/14

GPDR

1 : 출력

0 : 입력

0x40E0_0054/58/5C0x40E0_0060/64/68

0x40E0_0060/64/68

0x40E0_0060/64/68

Edge DetectStatus Register(GEDR)

Rising Edge DetectEnable Register(GRER)

Falling Edge DetectEnable Register(GFER)

EdgeDetect

Pin-LevelRegister(GPLR)

(Output)

Alternate Function(Input)

3

3

210

Power ManagerSleep Wake-up logic

Base Address

0x40E0_0000

0x40E0_0048/4C/50

0x40E0_0030/34/38

0x40E0_003C/40/44

0x40E0_0000/04/08

Interrupt ControllerInterrupt Controller

Level Register(ICLR)

Interrupt Controller

Mask Register (ICMR)

Interrupt Source Bit

All Other Qualified interrupt Bits

FIQ

23 23XScale CORE

CPSR.6(F)

40D0 0004

40D0 0008

CCR[DIM]=0 &IDLE mode=‘1’

0 : IRQ

1 : FIQ


Pending Register (ICPR)


IRQ Pending Register (ICIP)

Interrupt ControllerFIQ Pending Register (ICFP)

IRQ

CPSR.6(F)

CPSR.7(I)40D0 0000

40D0 000C

40D0 0010

40D0 0014 : Interrupt controller control register (ICCR)ICCR.0 : disable idle mask(DIM)

Fault Switches• Sleep Mode Test• External Voltage Regulator Requirements

PWR_EN

PXA255

VDD_FAULT

BATT_FAULT

Target Board: RESET• Processor Reset Circuit MAX811T• Voltage Monitor (3V~3.15 )• Manual Reset Input (Push button – “Low”)• Multi-ICE Reset • Reset Output to Flash

JTAG PORT J20

PXA255

RESET_IN

RESET_OUT

MR

RESET

MAX811T

31 5 7

JTAG_RST

RESET

RESET

Target Board: Flash Memory• 3Volt Intel Strata Flash - 28F128• 32Bit Data Bus• Size : 32MByte -128Mbit (16Mbyte) * 2 EA• MSC0 : Static Chip Select 0 (Bank 0)• Base Address = 0x0000_0000

PXA255Memory

Controller

Interface

ADDR [ 10..23]

DATA [ 0..32]

Flash

16Bit Low

Flash16Bit High

D[ 0..15]

D[ 16..31]

CS0

RESET

OE

Target Board: Static RAM• Samsung K6R4016V1C• 3Volt High-Speed CMOS Static RAM• 32Bit Data Bus / 1Mbyte• MSC1: Static Chip Select 3 (Bank 3)• Base Address = 0x0C00_0000

ADDR [ 10..23]

PXA255Memory

Controller

Interface

ADDR [ 10..23]

DATA [ 0..32]

SRAM

16Bit Low

SRAM16Bit High

D[ 0..15]

D[ 16..31]

DQM[ 0..1]

DQM[ 2..3]

CS3

WE

OE

Target Board: SDRAM• Samsung Synchronous DRAM - K4S561632• 32Bit Data Bus• 256Mbit - 4M x 16Bit x 4 Bank• Size : 64MByte -256Mbit (32Mbyte) * 2 EA• SDRAM Bank 0 - Dynamic Memory• Base Address = 0xA000_0000• Base Address = 0xA000_0000

PXA255Memory

Controller

Interface

ADDR [ 10..24]

DATA [ 0..32]

SDRAM

16Bit Low

SRAM

16Bit High

D[ 0..15]

D[ 16..31]

DQM[ 0..1]

DQM[ 2..3]

nSDCS0

WE

RAS/CAS

SDCLK1/SDCKE1

Target Board Circuit(1)

MMU

PXA250Core

PXA255

D[31:0]A[31:0]

LCD

Dynamic Memory Controller SDCKE[1]

SDCLK[1]SDCS[0]#SDRAS#

WE#SDCAS#

DQM[3:0]

MDCNFGMDCAS00MDREFR

LCD LDD[15:0]

TFT LCD & Touch screen

GP[27:0]

GPIO

GPIO Registers GP[27:0]

Bridge


ICIPICMRICLR

ICCRICFP

FIQ, IRQ

DMA

DMARegisters

LCD Controller

ADS 7843

LCD CON

LDD[15:0]L-FCLKL-LCLKL-PCLK

LCDControlRegisters

DCLKCS#DINBUSY

PENIRQ#DOUT

GP4

GP5GP26

X+X-

Y-Y+

Inverter Power

L-BIAS

E-PORT0[7:0] GP25E-PORT

GP23

E-PORT0 7

Target Board Circuit(2)P X A 2 5 5P X A 2 5 5P X A 2 5 5P X A 2 5 5D [1 5 :0 ] D [1 5 :0 ]

S O C K E T 0

S O C K E T 1

D IR O E #

D IR O E #

D [1 5 :0 ]

G P IO (7 )

G P IO (1 2 )

C D 1 #C D 2 #

C D 1 #C D 2 #

n P IO R

n P O E

PCMCIA / CF

C D 2 #

R D Y /B S Y #

R D Y /B S Y #

G P IO (1 1 )

G P IO (1 0 )

P S K T S E L

A (2 5 :0 )

O E #

W E #

IO R #

IO W #

R E G #

M A (2 5 :0 )

n P O E

n P W E

n P IO R

n P IO W

n P R E G

A (2 5 :0 )

O E #

W E #

IO R #

IO W #

R E G #n P C E (1 :2 ) C E (1 :2 )#

C E (1 :2 )#

n P W A IT

n P IO S 1 6

W A IT # W A IT #

IO IS 1 6 #

IO IS 1 6 #

Target Board: PS2 interface• PS2 Keyboard / Mouse

• Holtek HT6542B• 8Bit Data Bus• 8MHz Operating • Support PS/2 compatible mouse

HT6542B

KBCOKBCI

KBDO

KBDI

MSCO

MSCI

MSDO

MSDIMOUSE

KEYBOARD

DIR OE#

CS#

D(7:0)

PXA255

RD_nWR

nCS1nCS2

nCS3nCS4

DIR OE#

MD(31:0)

HT6542_CS

Address

Decoder

MA(25:0)

nOEnPWE

A0

RD#WR#

DQ RESET#

KB_INT

MS_INT

GPIO(19)

GPIO(9)

Target Board: Audio Codec• Audio Codec

• Cirrus Logic CS4202• AC’97 2.2 Compliant• 20-bit Stereo D/A Converters• 18-bit Stereo A/D Converters• 18-bit Stereo A/D Converters• MIC Input / Headphone Output

PXA255

AC’97

Controller Unit

(ACUNIT)

nACRESET

CS4202

AC’97 Primary CODEC

SDATA_OUT

SYNC(48 kHz)

SDATA_IN_0

BITCLK(12.288MHz

Hardware overview

MMU

PXA255 Core FTUART,BTUART

D[31:0]A[31:0]

PXA255

UTCR0UTCR1UTCR2

DB9

UTCR3

DTDRUTSR0UTSR1Bridge

TX1RX1

TX3RX3

DMA

RS-232

Serial / USB Port

USB

UDCCRUDCARUDCOMP

UDCCS2UDCD0UDCWC

FIQ, IRQ

USBCON

R

R

R

R

RFIQ, IRQ


ICIPICMRICLR

ICCRICFP

FIQ, IRQ

DMA

DMARegisters

MemoryController

MemoryControlRegisters

D+D-

473K

1.5K27.4

UDCIMPUDCCS0UDCCS1

UDCDRUDCSR

Target Board: Ethernet LAN• SMSC 10/100 Ethernet Single Chip LAN91C111• Internal 32bit Wide Data Path• 8Kbytes Internal Memory (Receive and Transmit FIFO Buffers)• External 25MHz-output pin for an external PHY and MAC• MSC0, 1 : Static Chip Select 1,2 (Bank 1,2)• Base Address = 0x04000_0000 (primary) 0x0800_0000(secondary)

PXA255

MD(31:0)

T/F

T/F

Primary Ethernet

Secondary Ethernet

ADDR (15:2)

D(31:0) D(31:0)

DIR OE#

Logic

nCS1nCS2

nCS3nCS4

RD_nWR

nPWE

nOEMA(25:0)

nDQM(3:0)

WE#

OE#

A(15:2)

DQM(3:0)#

WE#

OE#

A(15:2)

DQM(3:0)#

nCS1

nCS2

GPIO(0)

GPIO(1)

INTR0

INTR0

Target Board: Push Switch• 8bit Read [D0~D7] • Base Address = 0x1050_0000

PXA255

+3.3V

MemoryController

MD(7:0)

BU

FFE

R

CS4

Address

Decoder

MA(22:20)

G

Target Board: Discrete LED• 8Bit Write [ D0~D7 ]• Base Address = 0x1060_0000

PXA255

Memory

Controller

MD(7:0)

B

U

FF

E

R

CS4

Address Decoder

MA(22:20)

CK

Target Board: 7 Segment LED• 16Bit Write [ D0~D7 ] • Base Address = 0x1030_0000 [ Low 2 Segment ]

0x1040_0000 [ High 2 Segment ]

PXA255MD(15:0)

LAT

DQ(7:0)

MemoryController

T

CH

CS4

Address Decoder

MA(22:20)

CK

CK

LAT

C

H

DQ(15:8)

DQ(7:0)

DQ(15:8)

Target Board: Text LCD• 8Bit Data Write [ D0~D7 ]• 3Bit Control Write [ D8~D10]• Base Address = 0x1060_0000• 20 Characters x 2 Lines / Backlight Type

PXA255MD(15:0)

LA

Character LCD Module

+5V

VD

D(7:0)DQ(7:0)PXA255

Memory

Controller

A

TCH

CS4

Address

Decoder

MA(22:20)

CK

LA

TC

H

D(7:0)

RS

RW

E

DQ(8)

DQ(9)

DQ(10)

jtag port sdram 32m to 64m byte buffer sdram ac97 inteface...

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