Journal of

Electronic Design Technology

Jan - Apr il 2014

STM JOURNALSScientific Technical Medical

ISSN: 2321-4228(JoEDT)

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Journal of Electronic Design Technology

Journal of Electronic Design Technology

(ISSN: 2321– 4228)

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Industrial Tribology Machine Dynamics & Maintenance

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Chandigarh, India.

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Prof. Sajal K. PaulDepartment of Electronics Engineering,

Indian School of Mines Dhanbad-826004, India.

I take the privilege to present the hard copy compilation for the [Volume 5 Issue (1)] of Journal of

Electronic Design Technology (JoEDT). The intension of JoEDT is to create an atmosphere that

stimulates creativeness, research and growth in the area of Electronic Design Technology.

The development and growth of the mankind is the consequence of brilliant Research done by

eminent Scientists and Engineers in every field. JoEDT provides an outlet for Research findings and

reviews in areas of Electronic Design Technology found to be relevant for National and

International recent developments & research initiative.

The aim and scope of the Journal is to provide an academic medium and an important reference for

the advancement and dissemination of Research results that support high level learning, teaching and

research in the domain of Electronic Design Technology.

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their continued support and invaluable contributions and suggestions in the form of authoring write-

ups/ reviewing and providing constructive comments for the advancement of the journals. With

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Research/Review findings for our customers base.

I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.

Dr. Archana Mehrotra

Director

STM Journals

Director's Desk

STM JOURNALS

1. VLSI Transistor and Interconnect Scaling Overview Pritam Bhattacharjee, Arindam Sadhu 1

2. FDTD-based Time Domain Analysis of CMOS Gate Driven Interconnects M. Kavicharan, N.S.Murthy, N. Bheema Rao 16

3. Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm TechnologyNeha Yadav, Ashish Kumar Singhal 22

4. Automization In Diamond Industry H.S. Makda, Ashish M. Kothari, Mangalia Avani, Trivedi Khyati, Nagda Gunjan 36

5. Three Stage High Step-up Interleaved Boost Converter with Voltage Multiplier Cell Arundathi Ravi 39

ContentsJournal of Electronic Design Technology

JoEDT(2014) © STM Journals 2014. All Rights Reserved

Journal of Electronic Design Technology ISSN: 2321-4228

Volume 5, Issue 1

www.stmjournals.com

VLSI Transistor and Interconnect Scaling Overview

Pritam Bhattacharjee*, Arindam Sadhu Department of Electronics & Communication, Engineering- Microelectronics & VLSI, Heritage

Institute of Technology, Kolkata, India

Abstract In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are

discussed for nano-devices. New technologies adopted at research level are stated here in

brief.

Keywords: Scaling factor ‘s’, technology or process node, short-channel effects, drain-induced barrier lowering, punch through, surface scattering, velocity saturation, impact

ionization, hot electrons, SOI, floating body, FinFET, quantum dot cellular automata

JoEDT (2014)© STM Journals 2014. All Rights Reserved

Journal of Electronic Design Technology ISSN: 2321-4228

Volume 5, Issue 1

www.stmjournals.com

FDTD-based Time Domain Analysis of CMOS Gate

Driven Interconnects

M. Kavicharan*, N.S.Murthy, N. Bheema Rao Department of ECE, National Institute of Technology, Warangal, India

Abstract Accurate time domain analysis of CMOS gate driven interconnects is important for the

design and analysis of high performance VLSI systems. Conventionally, CMOS driver is

approximated as a constant resistance instead of non-linear and time-varying MOS resistance, which causes inaccurate modeling of CMOS driver. This paper presents a

new method for FDTD-based transient analysis of CMOS gate driven interconnect line

using a generalized model. The generalized model of CMOS inverter includes non-linear effects such as carrier’s velocity saturation effect of short channel devices, while

distributed interconnect RLC model is analyzed using conventional FDTD with second order accuracy. The simulation results of the proposed method are in good agreement

with LTspice results and considerable savings in CPU computation time is observed.

Keywords: CMOS driver, FDTD method, time domain analysis, distributed

interconnects

JoEDT(2014)© STM Journals 2014. All Rights Reserved

Journal of Electronic Design Technology ISSN: 2321-4228

Volume 5, Issue 1

www.stmjournals.com

Improvement of Design Issues in FinFET based Design

Techniques for XOR and XNOR Circuits

at 45 nm Technology

Neha Yadav1, Ashish Kumar Singhal

2*

1Research Scholar of ITM University, India

2Department of EE, SR group of Institution,

Jhansi (U.P), India

Abstract The scaling of conventional CMOS circuit inclines to the short channel effect due to

leakage current increase in the circuit. To minimize the short channel effect, FINFET can

be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital

circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This comparison is based on analysis of various design technique for XOR and

XNOR logic circuits. The performances of XOR and XNOR circuits are based on

CADANCE VIRTUOSO tool at voltage supply 0.6 voltages and the temperature is 260C

and all the simulation results have been generated by Cadence SPECTRE simulator at

45 nm technology. The XOR and XNOR circuits with pass transistor, inverter based

design, transmission gate and with feedback transistors designs are desirable for arithmetic circuits. Simulation results reveal low power, delay, power, delay product

(PDP), average dynamic power consumption and energy delay product (EDP).

Keywords: XOR, XNOR, PDP, low power, high speed, pass transistor, transmission

gate, feedback circuit cadence SPECTRE simulator at 45 nm technology

JoEDT(2014)© STM Journals 2014. All Rights Reserved

Journal of Electronic Design Technology ISSN: 2321-4228

Volume 5, Issue 1

www.stmjournals.com

Automization In Diamond Industry

H.S. Makda*, Ashish M. Kothari, Mangalia Avani, Trivedi Khyati, Nagda Gunjan Department of Electronics & Communication Engineering Atmiya Institute of Science &

Technology, Rajkot, Gujarat, India

Abstract The rapidly increase in the technology in diamond industry makes it possible to cut, shape and polish diamond in the beautiful and artistic manner with less time

consumption. But the process is very costly as extensive manpower is required in this

technology. The various processes involved in this technology such as cutting into parts,

polishing are done by the manpower. Above all the small things like to count the diamond

problem is neglected. As the size of the diamond is too small the counting person needs a sharp eye to count with accuracy without any mistake. Thus this process is very much

time consuming, as well it may cause eye problem in future to a counting person. Thus

our goal of this project invention relates to the problem of counting of a diamond of too small size or to large size. Tools are used in this project are image processing for

counting and micro-controller interfaced with displaying the counts of the diamond. The image of diamonds is captured and using matlab in image processing, after the image is

processed and the counting of diamond is possible after that the data stored in matlab

will given to micro-controller through the interfacing of matlab and micro-controller it will able to be display the number of diamonds counting on the LCD.

Keywords: Diamond counting, matlab programming, image processing

JoEDT(2014)© STM Journals 2014. All Rights Reserved

Journal of Electronic Design Technology ISSN: 2321-4228

Volume 5, Issue 1

www.stmjournals.com

Three Stage High Step-up Interleaved Boost Converter

with Voltage Multiplier Cell

Arundathi Ravi* Department of EEE, Sathyabama University, Chennai, India

Abstract In this paper, three stage high step-up interleaved boost converter with three voltage multiplier cells (VMCS) and three state switching cells (3SSC) is proposed. Here an

interleaved boost converter is used, as a result higher efficiency and reduced input ripple

current is obtained. Also, an additional stage of voltage multiplier i.e., three stages is added so that voltage gain will increase. It reduces switching loss and stress through the

devices. Moreover, by employing the three-state switching cell, the size of the inductor is reduced because the operating frequency of the inductor is double of the switching

frequency. The current share between the active switches allows further reduction of the

conduction losses in case of two stage circuit. The new method has been examined under various scenarios such as switching loss, ripples, stress and conduction loss. A detailed

comparative study is done between two stage multiplier cell and three stage multiplier

cell is made regarding power, efficiency, total stress and losses. The simulation of proposed converter with input voltage of 12 V and output of 115 V was done using

MATLAB and the simulation result was validated. Finally, a prototype was built for an input voltage of 12 V, 70 V output voltage and 14 W output power.

Keywords: voltage multiplier cell, interleaved boost converter, high voltage gain,

efficiency