joão paulo carmo, phd senior researcher university of
TRANSCRIPT
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Circuitos sequênciais
Campus de Azurém, 4800-058 Guimarães, PORTUGAL
Phone: +351-253-510190, Fax: +351-253-510189
João Paulo Carmo, PhD
Senior Researcher
University of Minho
R&D ALGORITMI Centre
Micro/Nanotecnology and Biomedical Applications
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Flip-flops
Necessidade de circuitos
Saídas actuais dependerem da história passada
Z[k.T] = f{ A(k.T) , Z[(k-1).T] }
Z[k.T] : saída actual, no instante k.T
A[k.T] : entrada actual, no instante k.T
Z[(k-1).T] : saída passada, instante (k-1).T
Impossibilidade com lógica combinacional
Circuitos com memória
Multivibrador biestável
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Multivibradores
Classes de multivibradores
Biestáveis
2 estados estáveis Capacidade de memorização
Monoestáveis Apenas 1 estado estável
Temporização Linhas de atraso digital
Astáveis Sem estados estáveis
Geradores de sinais de relógio
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Multivibradores
Multivibradores biestáveis
Assíncronos
Síncronos
Activados por nível
Biestáveis síncronos activados por flanco
Flip-flop
Activados por flanco
Todos os outros
Latch (báscula)
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1 0
A B
Circuito com memória mais rudimentar
Com dois estados estáveis
Sem entradas
Com pouco (ou nenhum) interesse
0 1
A B
A = 1 e B = 0 A = 0 e B = 1 Circuito bloqueado num destes estádos
Latched
Multivibradores
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Latch (báscula) SR (set/reset) com NOR
Qb
Qa
S
R
Saídas t=kT Qb S Qa R
0 0
0 1
1 0
1 1
Multivibradores
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Latch (báscula) SR (set/reset) com NOR
Saídas t=kT
Qb
Qa
S
R
Qb S Qa R
0 Qa(t-T) 0
0 1
1 0
1 1
Qb(t-T) Memoriza Qa
Qb
Multivibradores
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Flip-flops
Latch (báscula) SR (set/reset) com NOR
Saídas t=kT
Qb
Qa
S
R
Qb S Qa R
0 Qa(t-T) 0
0 0 1
1 0
1 1
Qb(t-T)
1 Desactiva Qa
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Latch (báscula) SR (set/reset) com NOR
Saídas t=kT
Qb
Qa
S
R
Qb S Qa R
0 Qa(t-T) 0
0 0 1
1 1 0
1 1
Qb(t-T)
1
0 Activa Qa
Multivibradores
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Latch (báscula) SR (set/reset) com NOR
Saídas t=kT
Qb
Qa
S
R
Qb S Qa R
0 Qa(t-T) 0
0 0 1
1 1 0
1 0 1
Qb(t-T)
1
0
0 A evitar
Multivibradores
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Q
Q
S
R
Latch (báscula) SR (set/reset) com NOR
Saídas t=kT Qb S Qa R
0 Qa(t-T) 0
0 0 1
1 1 0
1 0 1
Qb(t-T)
1
0
0
Q = Qa
Q = Qb
S
R Q
Q
Multivibradores
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Qb
Qa
S
R
Latch (báscula) SR (set/reset) com NAND
Saídas t=kT Qb S Qa R
1 Qa(t-T) 1
0 1
1 0
1 1
Qb(t-T) Memoriza Qa
Qb
Multivibradores
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Qb
Qa
S
R
Latch (báscula) SR (set/reset) com NAND
Saídas t=kT Qb S Qa R
1 Qa(t-T) 1
0 1
1 0
0 0
Qb(t-T)
1 0 Activa Qa
Multivibradores
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Qb
Qa
S
R
Latch (báscula) SR (set/reset) com NAND
Saídas t=kT Qb S Qa R
1 Qa(t-T) 1
0 1
1 0
0 0
Qb(t-T)
1 0
0 1 Desactiva Qa
Multivibradores
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Qb
Qa
S
R
Latch (báscula) SR (set/reset) com NAND
Saídas t=kT Qb S Qa R
1 Qa(t-T) 1
0 1
1 0
0 0
Qb(t-T)
1 0
0 1
A evitar 1 1
Multivibradores
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S
R Q
QS
R
Q
Q
S
R
Latch (báscula) SR (set/reset) com NAND
Saídas t=kT Qb S Qa R
1 Qa(t-T) 1
0 1
1 0
0 0
Qb(t-T)
1 0
0 1
1 1
Q = Qa
Q = Qb
Multivibradores
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S
R Q
QS
R
Q
Q
S
R
Latch (báscula) SR (set/reset) com NAND
Saídas t=kT Qb S Qa R
1 Qa(t-T) 1
0 1
1 0
0 0
Qb(t-T)
1 0
0 1
1 1
Entradas activas ao nível baixo
Multivibradores
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Latch (báscula) SR (set/reset) com NAND
Entradas activas ao nível alto
S
R Q
Q
Q
Q
S
R
S
R
S Q(t) R
0 Q(t-T) 0
0 1
1 0
1 1
0
1
1
Multivibradores
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Latch SR (set/reset) com enable
S Q(t) R
0 Q(t-T) 0
0 0 1 1 1 0 1 X 1
enable
1
1 1 1
0 X X
enable
S
R
Q
Q
S
R
S
R Q
Q
enable EN
Saídas t=kT
Q(t-T)
Multivibradores
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Latch tipo D (data)
clock
S
RQ
Q
S
R
D
(data)
(enable)
D
CLK Q
Q
clock
Saídas t=(k+1).T
CLK Q(t) D
0 Q(t-T) X
1 0
1 1
Retêm o valor
Q(t-T) anterior
Multivibradores
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Latch tipo D (data)
clock
S
RQ
Q
S
R
D
(data)
(enable)
D
CLK Q
Q
clock
Saídas t=(k+1).T
CLK Q(t) D
0 X
1 0
1 1
Memoriza 0 0
Q(t-T)
Multivibradores
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Latch tipo D (data)
clock
S
RQ
Q
S
R
D
(data)
(enable)
D
CLK Q
Q
clock
Saídas t=(k+1).T
CLK Q(t) D
0 X
1 0
1 1 Memoriza 1
0
Q(t-T)
1
Multivibradores
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Latch tipo D (data)
Diagrama temporal
t0
t1
t2
t3
t4
D
clock
Q
CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data)
Enquanto clock=0, Q(t) não varia (valor anterior)
CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data)
Enquanto clock=1, Q(t)=D (Q segue o valor de D)
CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data)
Quando clock transita de 1 para 0, Q(t)=Q(t-T)
CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
retêm Q(t-T)
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data) CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
Enquanto clock=0, Q(t) não varia (valor anterior)
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data) CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
Enquanto clock=1, Q(t)=D (Q segue o valor de D)
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data) CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
Quando clock transita de 1 para 0, Q(t)=Q(t-T)
retêm Q(t-T)
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data) CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
Enquanto clock=0, Q(t) não varia
Multivibradores
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t0
t1
t2
t3
t4
D
clock
Q
Latch tipo D (data) CLK Q(t) D
0 X
1 0
1 1
0
Q(t-T)
1 Diagrama temporal
As ideias anteriores repetem-se……
Multivibradores
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Latch tipo D (data)
Claramente trata-se de um biestável síncrono
t0
t1
t2
t3
t4
D
clock
Q
clock
S
RQ
Q
S
R
D
(data)
(enable)
Infelizmente, activado por nível Problemas não contemplados
Atraso de propagação no inversor Sinais de frequência muito elevada
Multivibradores
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D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
Flip-flop mestre-escravo (com 2 latch tipo D)
por 2 latch D anteriores
CLK
S
RQ
Q
S
R
D
CLK
S
RQ
Q
S
R
Dinput
clock
Qm
Qs
clock
master slave
por 1 inversor adicional
Constituído
Multivibradores
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D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
clock
input
Qm
Qs
clock
0 T 2T 3T
Flip-flop mestre-escravo (com 2 latch tipo D)
Análise temporal
Multivibradores
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clock
input
Qm
Qs
clock
0 T 2T 3T
D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
Flip-flop mestre-escravo (com 2 latch tipo D)
Análise temporal
Mestre
Sem novidade
Depende de
input (D)
clock (CLK)
Multivibradores
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clock
input
Qm
Qs
clock
0 T 2T 3T
D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
Flip-flop mestre-escravo (com 2 latch tipo D)
Análise temporal
Escravo
Análise fácil
Depende de
Qm (D)
clock (CLK)
Multivibradores
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clock
input
Qm
Qs
clock
0 T 2T 3T
clock
input
Qm
Qs
clock
0 T 2T 3T
D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
Flip-flop mestre-escravo (com 2 latch tipo D)
Sensibilidade
clock:
Multivibradores
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clock
input
Qm
Qs
clock
0 T 2T 3T
D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
Flip-flop mestre-escravo (com 2 latch tipo D)
Sensibilidade
clock:
flanco
descendente
Multivibradores
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D
Q
Q
clock
input
Qm
Qs
clock
0 T 2T 3T
D
CLK Q
Q D
CLK Q
Q
clock
inputQ
m
master slaveQ
s
clock
Qm
Flip-flop mestre-escravo (com 2 latch tipo D)
Sensibilidade
clock:
flanco
descendente
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock Q(t) D
X
Saídas t=(k+1).T
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock Q(t) D
X X Q(t-T)
Saídas t=(k+1).T
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock Q(t) D
X X
0 0
Q(t-T)
Saídas t=(k+1).T
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock Q(t) D
X X
0
1
0
Q(t-T)
1
Saídas t=(k+1).T
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock Q(t) D
X X
0
1
0
Q(t-T)
1
Saídas t=(k+1).T
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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Flip-flop D com sensibilidade ao flanco ascendente
clock Qn+1 D
X X
0
1
0
Qn
1
No estado n+1
clock
D
Q
1a
1b
2a
2b
3a
3b Q
S
R
D
Q
Q
Multivibradores
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clock
Qa
Qb
Qc
input
D Q
Q
D Q
Q
D Q
QCLK
input
clock
Qa
Qb
Qc
Comparação latch D e flip-flop D
Multivibradores
![Page 48: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/48.jpg)
clock
Qa
Qb
Qc
input
D Q
Q
D Q
Q
D Q
QCLK
input
clock
Qa
Qb
Qc
Comparação latch D e flip-flop D
Multivibradores
![Page 49: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/49.jpg)
clock
Qa
Qb
Qc
input
D Q
Q
D Q
Q
D Q
QCLK
input
clock
Qa
Qb
Qc
Comparação latch D e flip-flop D
Multivibradores
![Page 50: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/50.jpg)
clock
Qa
Qb
Qc
input
D Q
Q
D Q
Q
D Q
QCLK
input
clock
Qa
Qb
Qc
Comparação latch D e flip-flop D
Multivibradores
![Page 51: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/51.jpg)
clockQ
Q
2apreset
clear
D
Flip-flop D com sensibilidade ao flanco ascendente
Com sinais de
preset clear
Assíncronos
Multivibradores
![Page 52: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/52.jpg)
clockQ
Q
2apreset
clear
D
Flip-flop D com sensibilidade ao flanco ascendente
Com sinais de
D Q
Q
preset
clear
preset
clear
Assíncronos
Multivibradores
![Page 53: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/53.jpg)
Flip-flop D com sensibilidade ao flanco ascendente
Com clear
Síncrono
D
Q
Q
clear
D
clock
Só limpa o conteúdo no próximo flanco Introduz atraso
Até um período de clock
Multivibradores
![Page 54: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/54.jpg)
J Q
QK
clock
Flip-flop JK
Permite implementar o flip-flop D
Multivibradores
![Page 55: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/55.jpg)
J Q
QK
clock
Flip-flop JK
Permite implementar o flip-flop D
Mas mais flexível
Multivibradores
![Page 56: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/56.jpg)
J Q
QK
clock
Flip-flop JK
Permite implementar o flip-flop D
Permite activar/desactivar a saída
Mas mais flexível
Multivibradores
![Page 57: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/57.jpg)
J Q
QK
clock
Flip-flop JK
Permite implementar o flip-flop D
Permite activar/desactivar a saída
Mas mais flexível
clock Qn+1 K
0 Qn
Comportamento J
0 FF D
Multivibradores
![Page 58: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/58.jpg)
J Q
QK
clock
Flip-flop JK
Permite implementar o flip-flop D
Permite activar/desactivar a saída
Mas mais flexível
clock Qn+1 K
0
1 0
Qn
Comportamento J
0
0
Multivibradores
![Page 59: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/59.jpg)
J Q
QK
clock
Flip-flop JK
Permite implementar o flip-flop D
Permite activar/desactivar a saída
Mas mais flexível
clock Qn+1 K
0
1
0
0
Qn
1
Comportamento J
0
0
1
Multivibradores
![Page 60: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/60.jpg)
J Q
QK
clock
Qn
Flip-flop JK
Permite implementar o flip-flop D
Permite activar/desactivar a saída
Mas mais flexível
clock Qn+1 K
0
1
0
0
Qn
1
Comportamento
1
J
0
0
1
1 FF D
Pode dar jeito
Multivibradores
![Page 61: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/61.jpg)
J Q
QK
clock
Qn
Flip-flop JK
Permite implementar o flip-flop D
Permite activar/desactivar a saída
Mas mais flexível
clock Qn+1 K
0
1
0
0
Qn
1
Comportamento
1
J
0
0
1
1
X X X Qn
Multivibradores
![Page 62: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/62.jpg)
J Q
QK
clock
Flip-flop JK
Implementação
clock
D
K
J
Q
Q
Q
Q
Multivibradores
![Page 63: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/63.jpg)
Flip-flop T (toogle)
Permite trocar (ou não) a saída no estado anterior
Controlo: entrada T
T Q
Q
Multivibradores
![Page 64: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/64.jpg)
Flip-flop T (toogle)
Permite trocar (ou não) a saída no estado anterior
Controlo: entrada T
T Q
Q
Equivalente a
J Q
QK
T
clock
Multivibradores
![Page 65: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/65.jpg)
Flip-flop T (toogle)
Permite trocar (ou não) a saída no estado anterior
Controlo: entrada T
clock Qn+1 T
0 Qn
Comportamento
T Q
Q
Retém valor
Multivibradores
![Page 66: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/66.jpg)
Qn
Flip-flop T (toogle)
Permite trocar (ou não) a saída no estado anterior
Controlo: entrada T
clock Qn+1 T
0
1
Qn
Comportamento
T Q
Q
Troca valor
Multivibradores
![Page 67: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/67.jpg)
Qn
Flip-flop T (toogle)
Permite trocar (ou não) a saída no estado anterior
Controlo: entrada T
clock Qn+1 T
0
1
Qn
Comportamento
X X Qn
T Q
Q
Sem alteração
Multivibradores
![Page 68: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/68.jpg)
clock
T
Q
Flip-flop T (toogle)
Exemplo T Q
Qclock
Multivibradores
![Page 69: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/69.jpg)
clock
T
Q
Flip-flop T (toogle)
Exemplo T Q
Qclock
Instantes para troca de valor Q
Multivibradores
![Page 70: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/70.jpg)
Monostáveis
Multivibradores
Biestáveis
2 estados estáveis
![Page 71: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/71.jpg)
acção de
impulso externo
Monostáveis
Biestáveis
Multivibradores
2 estados estáveis
Dispara para estado instável Monostável
Regressa ao único estado estável
τ
![Page 72: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/72.jpg)
Monostáveis
Implementação
Multivibradores
τ = ln(2)RC
RRESET
DIS
THR
TRIG
GND CTRL
Vdd
OUT
C
C2
trigger
Sinais
trigger
OUT
DISdescarga
Vdd
τ
![Page 73: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/73.jpg)
Aplicações
Contadores digitais
Registos de deslocamento
Contadores digitais
Registos de dados
Comunicações digitais
Implementação de barramentos (bus)
Baralhadores (scramblers)
Geradores/detectores de CRC
Multivibradores
![Page 74: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/74.jpg)
Registos de deslocamento
Aplicações
Contadores digitais
Registos de dados
Comunicações digitais
Implementação de barramentos (bus)
Baralhadores (scramblers)
Geradores/detectores de CRC
Multivibradores
![Page 75: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/75.jpg)
Contadores digitais
Contadores
Assíncronos
clock é o sinal de sincronismo do 1º flip-flop
clock
Q Q Q
Q1
Q2
Q3
FF1
FF2
FF3
Síncronos
Contadores assíncronos
clock dos outros flip-flops é a saída do a montante
Circuito mínimo Requer cuidado com descodificação
Transições não simultâneas
![Page 76: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/76.jpg)
clock
Q1
Q2
Q3
Contadores digitais
Contadores assíncronos
8 estados (28) clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
FFs sem atraso
![Page 77: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/77.jpg)
Q1
clock
Q1
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso
clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Saída Q1
frequência (clock) = 2 frequência (Q1)
![Page 78: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/78.jpg)
Q2
clock2
= Q1
Q2
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso
clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Saída Q2
frequência (Q1) = 2 frequência (Q2)
![Page 79: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/79.jpg)
Q3
clock3
= Q2
Q3
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso
clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Saída Q3
frequência (Q2) = 2 frequência (Q3)
![Page 80: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/80.jpg)
clock
Q1
Q2
Q3
1 0 1 0 1 0 1 0
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Contagens
![Page 81: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/81.jpg)
1 1 0 0 1 1 0 0
clock
Q1
Q2
Q3
1 0 1 0 1 0 1 0
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Contagens
![Page 82: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/82.jpg)
1 1 0 0 1 1 0 0
clock
Q1
Q2
Q3
1 0 1 0 1 0 1 0
1 1 1 1 0 0 0 0
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Contagens
![Page 83: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/83.jpg)
1 1 0 0 1 1 0 0
clock
Q1
Q2
Q3
1 0 1 0 1 0 1 0
1 1 1 1 0 0 0 0
111 011 101 001 110 010 100 000 111
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Contagens
![Page 84: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/84.jpg)
1 1 0 0 1 1 0 0
clock
Q1
Q2
Q3
1 0 1 0 1 0 1 0
1 1 1 1 0 0 0 0
7 3 5 1 6 2 4 0 7
Contadores digitais
Contadores assíncronos
8 estados (28)
FFs sem atraso clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
Contagens
![Page 85: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/85.jpg)
clock
Q1
Q2
Q3
Contadores digitais
Contadores assíncronos
8 estados (28) clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
FFs com atraso
Transições não
coincidentes
ANTES
![Page 86: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/86.jpg)
clock
Q1
Q2
Q3
Contadores digitais
Contadores assíncronos
8 estados (28) clock
D Q
Q
D Q
Q
D Q
Q
Q1
Q2
Q3
FFs com atraso
Transições não
coincidentes
DEPOIS
![Page 87: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/87.jpg)
Contadores digitais
Contadores Síncronos
clock é o sinal de sincronismo de todos os flip-flops
Transições sincronizadas (razoavel/ simultâneas)
clock
Q Q QQ
1Q
2Q
3
FF1
FF2
FF3
Exige lógica não tão trivial
![Page 88: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/88.jpg)
Contadores digitais
Contador síncrono de 0 a 7 (contador de módulo 8)
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
![Page 89: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/89.jpg)
Contadores digitais
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
Q1 muda todos
os períodos
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 90: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/90.jpg)
Contadores digitais
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
Q1 muda todos
os períodos
Flip-flop T sempre
activado
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 91: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/91.jpg)
Contadores digitais
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
Mudanças em Q2
a cada 2 períodos
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 92: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/92.jpg)
Contadores digitais
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
Mudanças em Q2
a cada 2 períodos
Flip-flop T
activado por Q1
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 93: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/93.jpg)
Contadores digitais
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
Mudanças em Q3
a cada 4 períodos
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 94: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/94.jpg)
Contadores digitais
Saídas
Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 1
3 0 1
4 1 0
5 1 0
6 1 1
7 1 1
0
1
0
1
0
1
0
1
8 0 0 0
Mudanças em Q3
a cada 4 períodos
Flip-flop T
activado por Q2Q1
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 95: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/95.jpg)
Contadores digitais
Implementação
clock
QT
Q
Q1
1QT
Q
Q2
QT
Q
Q3
Q1.Q
2
Contador síncrono de 0 a 7 (contador de módulo 8)
![Page 96: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/96.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
![Page 97: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/97.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
Inicializar Q3Q2Q1Q0=1000
1 0 0 0
![Page 98: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/98.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
No flanco ascendente do clock (óbvia/ INIT=1)
![Page 99: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/99.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
No flanco ascendente do clock (Q2=Q3, Q1=Q2….)
0
1 0 0
![Page 100: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/100.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
Ideias repetem-se nos flanco ascendente do clock
0 0
1 0
![Page 101: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/101.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
Ideias repetem-se nos flanco ascendente do clock
0 0
0
1
![Page 102: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/102.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
O valor inicial 1000 volta a estar em Q3Q2Q1Q0
1 0 0 0
![Page 103: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/103.jpg)
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
As contagens repetem-se ao fim de 4 pulsos de clk
1 0 0 0
0 0
0
1
0 0
1 0
0
1 0 0
0 1
1 0
0
1 0 0
8 1 2 4 2 4
1 0 0 0
8
![Page 104: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/104.jpg)
1 0 0 0
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
Pode-se reiniciar Q3Q2Q1Q0=1000 em qq instante
![Page 105: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/105.jpg)
1 0 0 0
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
Pode-se reiniciar Q3Q2Q1Q0=1000 em qq instante
1 0 0 0
0 0
0
1
0 0
1 0
0
1 0 0
0 1
1 0
0
1 0 0
8 1 2 4 2 4
1 0 0 0
8 8 4
![Page 106: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/106.jpg)
0
1 0 0
Contadores digitais
Contador em anel (ring counter)
Supondo que se ativa (ativo a 0) no início o INIT
clock
INIT
Q0
Q3
Q2
Q1
D Q
Q0
clock
D Q
Q3
D Q
Q2
D Q
Q1
PRESET RESET RESET RESET
INIT
Depois recomeça tudo de novo
8 4
![Page 107: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/107.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
![Page 108: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/108.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q0 muda a cada
ciclo de clock
![Page 109: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/109.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q0 muda a cada
ciclo de clock
clock
T Q
Q
Q0
Flip-flop T com
sempre ativado
![Page 110: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/110.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q1 antes de mudar
precede Q0=1
![Page 111: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/111.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q1 antes de mudar
precede Q0=1
Flip-flop T
ativado por Q0
T Q
Q
Q1
clock
T Q
Q
Q0
![Page 112: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/112.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q2 antes de mudar
precede Q0=1
e Q1=1
![Page 113: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/113.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q2 antes de mudar
precede Q0=1
e Q1=1
Flip-flop T
ativado por Q0.Q1
T Q
Q
Q2
T Q
Q
Q1
clock
T Q
Q
Q0
![Page 114: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/114.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q3 antes de mudar
precede Q0=1
e Q1=1 e Q2=1
![Page 115: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/115.jpg)
Contadores digitais
Contador síncrono de módulo 2N = 16 (de 0 a 15) Q1 Ciclo # Q3 Q2
0 0 0
1 0 0
2 0 0 3 0 0
4 0 1 5 0 1
6 0 1 7 0 1
0
0
1 1
0 0
1 1
8 1 0 0
9 1 0 10 1 0
11 1 0 12 1 1
13 1 1 14 1 1
0 1
1 0
0 1
15 1 1 1
Q0
0
1
0 1
0 1
0 1
0
1 0
1 0
1 0
1
Q3 antes de mudar
precede Q0=1
e Q1=1 e Q2=1
Flip-flop T ativado
por Q0.Q1.Q2
T Q
Q
Q2
T Q
Q
Q1
clock
T Q
Q
Q0
T Q
Q
Q3
![Page 116: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/116.jpg)
Registros de dados
Armazena N bits ao flanco ascendente Requer N flip-flops como elementos de memória
Em comum têm: Sinal de control clock
clock
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Ex: registro de 4 bits
![Page 117: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/117.jpg)
Registros de dados
Desvantagem Armazena o dado a cada flanco ascendente
D Q
Q
Q1
dado
clock
![Page 118: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/118.jpg)
D Q
Q
Q1
dado
clock
Registros de dados
Desvantagem Armazena o dado a cada flanco ascendente
![Page 119: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/119.jpg)
Registros de dados
Como obviar o problema anterior
Controlar o armazenamento
Utilizando um sinal adicional, load
D Q
Q
Q
clock
dado
load
0
1
Conjuntamente com um multiplexer 2:1
D Q
Q
dado
clock
load
![Page 120: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/120.jpg)
Registros de deslocamento
Úteis numa panóplia alargada de aplicações
Tipos
Entrada paralelo – Saída paralelo (PIPO)
Barramentos (bus)
Entrada paralelo – Saída série (PISO)
Transmissor de linha série (p.ex., RS232)
Entrada série – Saída paralelo (SIPO)
Receptor de linha série (p.ex., RS232)
Entrada série – Saída série (SISO) Leitura/escrita sequencial de dados
![Page 121: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/121.jpg)
Registros de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
Q1 Q3 Q2
t0
t1
t2
t3
t4
t5
t6
t7
t8
in
1
0
1
1
1
0
X
X
(=out)
X
Deslocamento de 101110
![Page 122: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/122.jpg)
Deslocamento de 101110
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1
t2
t3
t4
t5
t6
t7
0
t8
in
1
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Instante t0:
P.ex.: limpou conteúdo dos FFs
out(t0) = X
1 0 0 0
X X X
![Page 123: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/123.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2
t3
t4
t5
t6
t7
0
0
t8
in
1
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t1:
Q3(t1) = in(t0)
out(t1) = X
0 1 0
1
0
X X
![Page 124: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/124.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3
t4
t5
t6
t7
0
0
0
t8
in
1
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110 Deslocamento de 101110
Instante t2:
Q3(t2) = in(t1)
out(t2) = X
1 0 1 0
X
![Page 125: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/125.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3 1 0
t4
t5
t6
t7
0
0
0
1
t8
in
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t3:
Q3(t3) = in(t2)
1
out(t3) = in(t0)
1 1 0 1
![Page 126: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/126.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3 1 0
t4
t5
t6
t7
0
0
0
1
t8
in
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t4:
Q3(t4) = in(t3)
out(t4) = in(t1)
1
1 1 0
1 1 1 0
![Page 127: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/127.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3 1 0
t4
t5
t6
t7
0
0
0
1
t8
in
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t5:
Q3(t5) = in(t4)
out(t5) = in(t2)
1
1 1 0
1 1 1
0 1 1 1
![Page 128: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/128.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3 1 0
t4
t5
t6
t7
0
0
0
1
t8
in
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t6:
Q3(t6) = in(t5)
out(t6) = in(t3)
1
1 1 0
1 1 1
0 1 1
X 0 1 1
![Page 129: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/129.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3 1 0
t4
t5
t6
t7
0
0
0
1
t8
in
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t7:
Q3(t7) = X
out(t7) = in(t4)
1
1 1 0
1 1 1
0 1 1
X 0 1
X X 0 1
![Page 130: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/130.jpg)
Registos de deslocamento
Entrada série – Saída série (SISO)
Desloca os dados horizontalmente
Q1 Q3 Q2
t0 0 0
t1 1 0
t2 0 1
t3 1 0
t4
t5
t6
t7
0
0
0
1
t8
in
0
1
1
1
0
X
Entrada
de dados
(in)
clock
D Q
Q
Q3
D Q
Q
Q2
D Q
Q
Q1
Saída
de dados
(out)
(=out)
X
X
Deslocamento de 101110
Instante t8:
Q3(t8) = X
out(t8) = in(t5)
1
1 1 0
1 1 1
0 1 1
X 0 1
X X 0
X X X 0
![Page 131: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/131.jpg)
Registros de deslocamento
Entrada série – Saída paralelo (SIPO)
store
D Q D Q D Q
parallel out
P3
P2
P1
serial in
clock
D Q
Q3
D Q
Q2
D Q
Q1
Andar de
colocação
dos dados
Andar de
memorização
dos dados
Requer 2 andares: Colocação dos dados
Memorização dos dados
![Page 132: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/132.jpg)
Registros de deslocamento
SIPO
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
serial in
clock
D Q
Q3
D Q
Q2
D Q
Q1
Andar de
colocação
dos dados1º andar: SISO
t1 t2 t3
![Page 133: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/133.jpg)
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
Registos de deslocamento
SIPO serial in
clock
D Q
Q3
D Q
Q2
D Q
Q1
Andar de
colocação
dos dados1º andar: SISO
serial in: 101 t1 t2 t3
![Page 134: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/134.jpg)
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
1 10
X
X X
1 10X
01X
1X
Registos de deslocamento
SIPO serial in
clock
D Q
Q3
D Q
Q2
D Q
Q1
Andar de
colocação
dos dados1º andar: SISO
serial in: 101 t1 t2 t3
![Page 135: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/135.jpg)
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
1 10
X
X X
1 10X
01X
1X
Registos de deslocamento
SIPO serial in
clock
D Q
Q3
D Q
Q2
D Q
Q1
Andar de
colocação
dos dados1º andar: SISO
serial in: 101 t1 t2 t3
2º andar: próxima etapa
Ordenar a memorização dos dados Q3Q2Q1
![Page 136: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/136.jpg)
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
1
0
1
Registos de deslocamento
SIPO
2º andar
Armazenar 101 t1 t2 t3
store
D Q D Q D Q
parallel out
P3
P2
P1
Andar de
memorização
dos dados
Q3
Q2
Q1
![Page 137: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/137.jpg)
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
1
0
1
1
0
1
Registos de deslocamento
SIPO
2º andar
Armazenar 101 t1 t2 t3
store
D Q D Q D Q
parallel out
P3
P2
P1
Andar de
memorização
dos dados
Q3
Q2
Q1
![Page 138: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/138.jpg)
clock
serial in
Q3
Q2
Q1
store
P3
P2
P1
1
0
1
1
0
1
Registos de deslocamento
SIPO
2º andar
Armazenar 101 t1 t2 t3
store
D Q D Q D Q
parallel out
P3
P2
P1
Andar de
memorização
dos dados
Q3
Q2
Q1
![Page 139: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/139.jpg)
Registros de deslocamento
Entrada paralelo – Saída série (PISO)
store/shift
serial out
clock
D Q D Q D Q
Q3
Q2
Q1
P3
S
R
S
R
S
R
P2
0
1
P1
0
1
Requer 2 etapas: Armazenamento dos dados
Deslocamento dos dados (SISO)
![Page 140: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/140.jpg)
Registros de deslocamento
Entrada paralelo – Saída série (PISO)
store/shift
serial out
clock
D Q D Q D Q
Q3
Q2
Q1
P3
S
R
S
R
S
R
P2
0
1
P1
0
1
Requer 2 etapas: Armazenamento dos dados Deslocamento dos dados (SISO)
Requer N-1 multiplexers:
select
0
1
A
B
Z
select
A
B
Z
![Page 141: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/141.jpg)
store/shift
serial out
clock
D Q D Q D Q
Q3
Q2
Q1
P3
S
R
S
R
S
R
P2
0
1
P1
0
1= 0
Registros de deslocamento
Entrada paralelo – Saída série (PISO)
Etapa 1: armazenamento dos dados
store = 1 (store/shift = 0)
![Page 142: João Paulo Carmo, PhD Senior Researcher University of](https://reader035.vdocuments.site/reader035/viewer/2022081601/62bcd0976416e7258f1d04f4/html5/thumbnails/142.jpg)
store/shift
serial out
clock
D Q D Q D Q
Q3
Q2
Q1
P3
S
R
S
R
S
R
P2
0
1
P1
0
1= 1
Registos de deslocamento
Entrada paralelo – Saída série (PISO)
Etapa 2: deslocamento dos dados
shift = 1 (store/shift = 1)