, Printed Pages: ,I--~,----------------------------(following Paper ID and .coll \0. to be filled in your answer book)(i) J .ist the set of for bidden latencies and the Collision Vector.

t ii: Urnvv a state t.ransition d azramCo •

():'.(ct) Draw a diagram sbowi ig the structure of a four dimensionalhypercube network. List all the paths available fr0111 node 7 to1111d~, l) that use the minir UI11 number of intermediate nodes.

0J (i) Draw'([ 8 input Omeg: network using 2x2 switches as buildinghiocks. . a

(ii) Determine how many rerrnutations can be implemented ill onepass through this omega network. What is the percentage of onepass lcrmlltations.

"liii) . \Yh,lt is the maximum number or passes neede to implementany permutations through the network?

(,-)",Writc: short notes on the [allowing:v ci.i Snoopy Bus protocols 2.

(ii) Directory based protocols ~.(iii) Muhipori memory.

------.----------------------------------~M.Tech

FIRST SEMESTER EXAMINATION, 2008-2009COMPUTER ORGANIZATION AND ARCHITECTURE

Tillie: Lhrs. Max. Marks: 1(JO

Note: Attempt ({II questions. AU questions carry equal marks ..

Q 1. Attempt any Four parts or the following:

v\ . (~)/ The output of [our registers, RO, R 1, R2 and R3 are connected, through 4 to I line multiplexers to the inputs of fifth register RS.

Each register is eight bi ts long. The required transfers an dictated byfour timing variables to through T,3 as follows:

TO: RS ~ ROTl : RS ~ RlT2: RS ~ R2T3: R5 ~R3

The timing variables are mutually exclusive, which means that onlyone variables is equal to I at any given time, while the other three anequal to O. Draw a block diagram showing the hardwarei111plernentation of the register transfers. Incl ude the connectionsnecessary from the four timing variables to the selection inputs ofhe multiplexers and to load input of register R5.

~ What are the advantages and disadvantages of hardwired and micra~ )')!'\ -grarnmed control? :.!~:I. 1 ~i the ,!ddr~~s stored ill the progr~m counter be designated hy thecy ~\mr-ol x I. I he instrucuon store-i in X I has an address par: x~. TI]£v .

')l'('r,! nd needed to ex ecute the instruction is stored in the rnernorj

..nd with address :-.:3. An index register contains the value xqwhat is the relationship between these various quantities if the..addrcssi ng mode of the instruction is (i) direct (i i) Indirect;(:;:! l'C "cia ive (iv) Indexed?

. ",'n~t.' _./-

17'"r" n"",

(e)

CO

Design a variable length opcode to allow all of the following to beencoded in a 36 - bit instruction:

(i) Instruction with two IS bit addresses and one 3 bitregister number.

(ii) Instruction with OIIC IS bit ;Iddrcss ;11](1 o Ill: , hi: I·l-,~.i~;t('\'number.

(i ii) 1nstructions with no addresses or registers.All is bit computer has a register R. Determine the values 01' st;ILusbit c.s.z and v after each of the following instructions. The initiulvalue of register R. in each case is hexadecimal 72. The numbersbelow are also in hexadecimal. -

L(i) Add immediate operand C6 to R(ii) Subtract immediate operand 9A from R(iii) AND immediate operand 8 D to R(iv) Exclusive - OR R with R

\

I)df'l'mine the lour pages resident ill the memory alter each i", -

reference change for each of the following replacement policie- •(i) riro (ii) LRU

(b,)(i) A block set associated cache c insists 1,)1 a t(lLI! "i ()·I hi"U:,] divided into 4 block sets the main memo!')' cOI1(,~il1:; ,tl% bl.«:

l·"e11 l'(lll.'iistillg ()r 12X words.t I) How many bits are there in a main memory address?(2) How many bits are there in each of the TACT. SFT ',lel \Vt Ii; I'

fields?..\( i i ) Discuss the lJMA data transfer with llic help or block diagr(II~1

(c) (i ) Give a block diagram for a 8M x 32 memory using 512 K .\ ::memory chips. 2S

/1;(ii) What is meant by the BUS arbitration. How call nt is arbitr.ui»:, be implemented in Daisy Chaining Scheme?

Q2. :\ttelllpt any Two parts of the follcwing : [lOx~]

(!4.(I) l.xplain the applicability ,JIlL!the involved ill usiu]; :\llllblll\ 1:11'.

Gustafson's law and sun and 1 Ii s law to estimate the spcl'dllj'performance of an n - processor system compared with tlta: l" ;l

single processor system. Ignore all communication over heads.01 Design a binary integer multiply pipeline with five stages. Till'

first stage is for partial product generation. The last stage is ;1 .iilbit carry look a head adder. The middle three stages are IWilL· ,.,16 carry save adders (CSAs) of appropriate lengths .. -:

(i) Prepare a schematic design of the live stage multiply pipcliu.All line widths and inter staue connections must hl' :'1\('\\:1.

(ii) Determine the maximal clock rate of the pipeline if me :-,~.:_delays are 11 = 12 = 1] = 14 90 I1S15 45 ms, and the latch del.i, i··.20 111S.

(iii) What is maximal through put of this pipeline ill terms of th.:number of 36 - bit results generated per second.

(c) Consider the following reservation table: 1-J'

~(i) Using combinational circuit design techniques, derive the\0 Boolean functions for the BCD 9's cornplementor. Draw the

logic diagram.V~ii) Show the hardware to be used lor the addition and subtraction

of two decimal numbers in signed-magnitude representation.Indicate how an overflow is detected. 3

(b) 'K) Derive an algorithm in flowchart for decimal division.\'O(ii) Show the content of registers A. 8,8, and sc during. the decimal

multiplication of 470 x 199.. (s.{:~i) Design an array multiplier that multiplies two 4 bit numbers.'-'" \GUse A1':D gates and binary address. L

(ii) Represent following decimal numbers in IEEE 754 i1o(lling.point format: -7- 1.75, - .012 4-'

Q3.~ A virtual m.emory system has 16.k word logi~al ad~rt:ss space, ,:K\ ~ word physical address space WIth a pag: SIze of 2k v;,ords. I he

page address trace of a program has been found to be :7532104167420135")

Tl T2SI IA :8S2 , iAS3 \B !,

T3 T4 .T5A IB,13! :--~~--~i'-A-B-+-~

rS/IT-I2 -2- C\/fl'-12 -3-

,---~~------------------. - --. --(Following Paper ID and Roll No. to be fille-' your answer book)

ROIINo~ -'----'--'-----'---'---j

M.TechFIRST SEMESTER EXAMINATION,2009-2010

COMPUTER ORGANIZATION & ARCHITECTURE

Time: Lhrs. Max. Marks:lOO

Note: Attempt all questions. All questions carry equal marks.

Que.l. Attempt any TWO parts 1.10*2 =20]

a) Write a program to evaluate the arithmetic statementX = A-B+C*(D*E-F)

C+Il*F!. using a general register computer with three add rest:

instructions.2. Using a general register computer with two address

instructions.b) Explain instruction cycle along with the micro operations 0

each of the phasesc) i) What is the difference between microprocessor, a micro

program, a microinstruction, micro operation andmicrocode?ii) Discuss the procedure to map the instruction code tomicro instruction address

Que.Z. Attempt any TWO parts r 10*2 =20 ]

a) Explain the Booth's algorithm for multiplication of signed-2's complement numbers along with flow chart and (suitable example.

CSI!T-j~ -1- (Turn over]

What do you mean by high speed adders? Discuss design ofhigh speed adders.

c) i) Represent -(0.625) decimal in IEEE 754 floating formats: Single precision format and double precision fonnat.ii) Show the contents of registers E, A, Q, and SC duringthe process of division of 111000000 by 10001.

Que.3. Attempt any TWO parts [10*2 =20]

a) Give the block diagram of DMA controller? Why are theread and write control lines in a DMA controllerbidirectional? Under what condition and for what purposearc they used as inputs? Under what condition and for whatpurpose are they used as 0 utputs?

b) i) Write short note on Virtual memory.ii) A ROM chip of 1024x8 bit has four select input andoperates from a 5 volt power supply. How many pins are

, needed for the IC package? Draw a block diagram and labelall inputs and output terminals in the ROM.

c) A digital computer has a memory unit of 64Kx.16 and acache memory of the words. The cache uses direct mappingwith a block size of four words.i) How many bits-arc there in the tag, index, block. andword fields of the address format? .ii) How many blocks can the cache accommodate?

Que.4. Attempt any TWO parts [10*2 =20]

a) Discuss the superscalar and superpipelined processing.Also estimate the performance of superlined superscalarprocessor of degree (m,n).

b) Prove the relation S n * >=S n' >=S n foe solving the sameproblem on the same machine under different assumption.Also derive that Amdahl's law and Guftafson's law as aspecial case of the S 11 * expression.

CSIIT-12 -2-

I.

II.

Ill.

r lV.

c) Consider the 5-stage pipelined processor srI cified by thefollowing reservation table:

. -1 2 3 4 5

S1 XS2 X X -.S' X-,

~-

S4 X--I

S5 X ,JI

List the set of forbidden latencies and the (, .llision vector.Draw a state diagram showing all possible initial sequenceswithout collision in the pipeline.Identify the simple cycles: greedy cyc'cs and minimumaverage latency (MAL)What is the maximum throughput of this pipeline?

Que.5 Attempt any TWO parts [10*2 =20]

CSIIT-12

a) What is cache coherence problem? How does this occurs.Discuss snoopy bus protocol and directory based protocol.

b) Discuss following for Message passing mechanismsi) Message routing schemesii) Virtual channels and deadlocks

c) i) How many legitimate states are there in a 4x4 switchmodule including both broadcast and permutations? Justifyyour answer with reason?ii) Construct a 64-input Omega network using 4x4 switchmodules in multiple stages. How many permutations can beimplemented directly in a single pass through the network\\ithout blocking?

-3-

I Printed pages: 2 ~' CS/IT-12, II ~ Cs rl-L~roll No. to be filled your answer beak) ~

•. • - • • - Roll No. ~:O::3J~ 0 I 0 19"13 II

M.Tech.FIRST SEM. EXAMINATION, 2010-11

Time: 3hrs. Max. Marks: 100

Subject: Computer Organization and Architecture

Note: (1) Attempt all questions.(2) All questions are equal marks.(3) Notations used have usual meaning.(4) Make suitable assumptions where ever necessary.

Q.1. Attempt any two parts of the following:

(a) What are the advantages and disadvantages of

hardwired and microprogrammed control. Why is

microprogrammed control is increasingly becoming

popular.

,(b) Discuss the applications of Autoincrement and

Index addressing modes with the help of suitable

examples. Also explain the role of program counter

in implementing the various basic addressing modes.

(c) A given cornputer has 16-bit instructions.

Operand addresses are specified using G-b;t fields.

There are k two operand instructions (ior example

compare) and I zero-operand in tructions (for

example, Halt). What is the maximum number oj'

one operand instructions that can be provided in tlus

comput-er?

Q2 Attempt any two parts of the following:

(a) Explain with the of timing diagrams the hand

shake control of data transfer during an input and

output operation in standard I/O interrace.

(b) Multiply the signed 6-bit nu.ub..r: :\ :. ()1 0 I : 1

(multiplicand) and B = 110110 (rnutuplier) 'J~'n~'

Booth's aigoritbm. Each and evorv Sicn :)f I.

(c) Write a note on vectored interrupts.

Q3 Attempt any two parts of the following:

(a) Given that magnetic disks are used a' the

secondary storage for programs and dam files i(; .'

virtual-memcry system,

parameter should influence the choice o!:page size.

(b) Disc ..iss the superscaler :lJld supcrpi pI:' iined

processinu. Also estimate the performance pi

uperpipelined superscaler proce SOl of c':Jc,: (n.,

n).

(c) Do a comparative analysis of distributed and

shared memory MIMD architecture.

Q4 Attempt any two parts of the following :

to A23) from least to most significant. Which

address bits are unaffected by translation?

(a) What are pipeline hazards. Discuss the branch

prediction strategies in detail to address the branch

problems.

(c) In a three level volatile memory organisation the

access time from primary and secondary cache are

5ms and 20ms respectively. The hit rate of primary

cache is 70 percent whereas the hit rate 'of secondary

cache is 50 percent. If the hit rate of. primary

memory is 40 percent and the average access time is.80ms then calculate the average access time of data

,from the memory.

(b) What are major advantages of Vector Processor.

i\ four ported (three read, one write) would support a

vector processor with what maximum speedup over

uniprocessor. Explain?

\ c) ! >i:,1,;\!SS three basic issues and their impact in the

dcsii:!,il of sharer, memory multiprocessor

architectures.

Q5 Attempt any two of the following:

(a) In a cache memory organization, how memory is

updated on a write. Discuss the advantages and

disadvantages of write-through and copyback

policies.

(b) I~ 128KB cache has 64B lines,,8B physical

words, 4K. byte pages, and is four-way set

associative. It uses copy-back and LRU

replacements. The processor creates 30 bit (byte

addressed) virtual addresses ihat are translated to 24

hit (hv1P. addressed) real byte addu.sses (labelled AO