ispmach 4a data sheet (vl)
TRANSCRIPT
Publication#
ISPM4A
Rev:
M
Amendment/
0
Issue Date:
September 2006
Lead-Free
PackageOptions
ispMACH™ 4A CPLD FamilyHigh Performance E2CMOS® In-System Programmable Logic
Available!FEATURES◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families◆ Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and refit feature— SpeedLockingTM performance for guaranteed fixed timing— Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed— 5.0ns tPD Commercial and 7.5ns tPD Industrial— 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages◆ Flexible architecture for a wide range of design styles
— D/T registers and latches— Synchronous or asynchronous mode— Dedicated input registers— Programmable polarity— Reset/ preset swapping
◆ Advanced capabilities for easy system integration— 3.3-V & 5-V JEDEC-compliant operations— JTAG (IEEE 1149.1) compliant for boundary scan testing— 3.3-V & 5-V JTAG in-system programming— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)— Safe for mixed supply voltage system designs— Programmable pull-up or Bus-FriendlyTM inputs and I/Os— Hot-socketing — Programmable security bit— Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions◆ Lead-free package options
Table 1. ispMACH 4A Device Features
3.3 V Devices
Feature M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512
Macrocells 32 64 96 128 192 256 384 512
User I/O options 32 32/64 48 64 96 128/160/192 160/192 160/192/256
tPD (ns) 5.0 5.5 5.5 5.5 6.0 5.5 6.5 7.5
fCNT (MHz) 182 167 167 167 160 167 154 125
tCOS (ns) 4.0 4.0 4.0 4.0 4.5 4.0 4.5 5.5
tSS (ns) 3.0 3.5 3.5 3.5 3.5 3.5 3.5 5.0
Static Power (mA) 20 25/52 40 55 85 110/150 149/155 179
JTAG Compliant Yes Yes Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes Yes Yes
5 V Devices
Feature M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256
Macrocells 32 64 96 128 192 256
User I/O options 32 32 48 64 96 128
tPD (ns) 5.0 5.5 5.5 5.5 6.0 6.5
fCNT (MHz) 182 167 167 167 160 154
tCOS (ns) 4.0 4.0 4.0 4.0 4.5 5.0
tSS (ns) 3.0 3.5 3.5 3.5 3.5 3.5
Static Power (mA) 20 25 40 55 74 110
JTAG Compliant Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes
2 ispMACH 4A Family
GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Table 2).
Note:
1. C = Commercial, I = Industrial
Table 2. ispMACH 4A Speed Grades
Device
Speed Grade
-5 -55 -6 -65 -7 -10 -12 -14
M4A3-32
M4A5-32C C, I C, I I
M4A3-64/32
M4A5-64/32C C, I C, I I
M4A3-64/64 C C, I C, I I
M4A3-96
M4A5-96C C, I C, I I
M4A3-128
M4A5-128C C, I C, I I
M4A3-192
M4A5-192C C, I C, I I
M4A3-256/128 C C C, I C, I I
M4A5-256/128 C C C, I I
M4A3-256/192
M4A3-256/160C C, I I
M4A3-384 C C, I C, I I
M4A3-512 C C, I C, I I
ispMACH 4A Family 3
The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable power-down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition.
Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512
44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 64+6 48+8 64+6
100-pin PQFP 64+6
100-ball caBGA 64+6
144-pin TQFP 96+16
144-ball fpBGA 96+16
208-pin PQFP 128+14, 160 160 160
256-ball fpBGA 128+14, 192 192 192
256-ball BGA 128+14 192
388-ball fpBGA 256
5 V Devices
Package M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256
44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 48+8 64+6
100-pin PQFP 64+6
144-pin TQFP 96+16
208-pin PQFP 128+14
4 ispMACH 4A Family
FUNCTIONAL DESCRIPTION
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL® blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes. In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently.
Notes:1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix.
I/OPins
Clock/InputPins
Cen
tral
Sw
itch
Mat
rix
I/OPins
I/OPins
DedicatedInput Pins
PAL Block
PAL Block
LogicAllocatorwith XOR
Output/Buried
Macrocells
33/34/36 1616
ClockGenerator
LogicArray
Out
put S
witc
h M
atrix
InputSwitchMatrix
I/O C
ells
16
16
8
Note 1
Note 2
Note 3
4
PAL Block
17466G-001
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
ispMACH 4A Family 5
Table 4. Architectural Summary of ispMACH 4A devices
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate with each other with consistent, predictable delays.
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device.
Each PAL block consists of:
◆ Product-term array◆ Logic allocator◆ Macrocells◆ Output switch matrix◆ I/O cells◆ Input switch matrix◆ Clock generatorNotes:1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
ispMACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-512
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-256/160
M4A3-256/192
Macrocell-I/O Cell Ratio 2:1 1:1
Input Switch Matrix Yes Yes1
Input Registers Yes No
Central Switch Matrix Yes Yes
Output Switch Matrix Yes Yes
6 ispMACH 4A Family
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided in both true and complement forms for efficient logic implementation.
Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number of unused—or wasted—product terms left over. The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7.
Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration of the associated macrocell. When the macrocell is used in synchronous mode(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing.
In addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18 product terms.
When the extra product term is used to extend the cluster, the value of the second XOR input can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are shown in Figures 3 and 4.
Table 5. PAL Block Inputs
Device Number of Inputs to PAL Block
M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-64/64
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64
33
33
33
33
33
M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128
34
34
M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512
36
36
36
ispMACH 4A Family 7
Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)
Output Macrocell Available Clusters Output Macrocell Available Clusters
M0 C0, C1, C2 M8 C7, C8, C9, C10
M1 C0, C1, C2, C3 M9 C8, C9, C10, C11
M2 C1, C2, C3, C4 M10 C9, C10, C11, C12
M3 C2, C3, C4, C5 M11 C10, C11, C12, C13
M4 C3, C4, C5, C6 M12 C11, C12, C13, C14
M5 C4, C5, C6, C7 M13 C12, C13, C14, C15
M6 C5, C6, C7, C8 M14 C13, C14, C15
M7 C6, C7, C8, C9 M15 C14, C15
Table 7. Logic Allocator for M4A(3,5)-32/32
Output Macrocell Available Clusters Output Macrocell Available Clusters
M0 C0, C1, C2 M8 C8, C9, C10
M1 C0, C1, C2, C3 M9 C8, C9, C10, C11
M2 C1, C2, C3, C4 M10 C9, C10, C11, C12
M3 C2, C3, C4, C5 M11 C10, C11, C12, C13
M4 C3, C4, C5, C6 M12 C11, C12, C13, C14
M5 C4, C5, C6, C7 M13 C12, C13, C14, C15
M6 C5, C6, C7 M14 C13, C14, C15
M7 C6, C7 M15 C14, C15
0 Default
0 Default
Prog. Polarity
To
n-1
To
n-2
Fro
m n
-1
To
n+
1
Fro
m n
+1
Fro
m n
+2
Basic Product Term Cluster
ExtraProduct
Term
Logic Allocator
n n
To
Ma
cro
cell
n
0 Default
0 Default
Prog. Polarity
To n
-1T
o n
-2
Fro
m n
-1
To n
+1
Fro
m n
+1
Fro
m n
+2
Basic Product Term Cluster
ExtraProduct
Term
Logic Allocator
n n
To M
acro
cell
n
17466G-006
Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”
17466G-005
a. Synchronous Mode
b. Asynchronous Mode
8 ispMACH 4A Family
Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All configurations have the same delay. This means that designers do not have to decide between optimizing resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available.
0
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low
d. Basic cluster routed away;single-product-term, active high
e. Extended cluster routed away
0
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
b. Extended cluster, active high c. Extended cluster, active low
e. Extended cluster routed awayd. Basic cluster routed away;single-product-term, active high
a. Basic cluster with XOR
ispMACH 4A Family 9
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator.
SWAP
D/T/L QAP AR
Power-UpReset
PAL-BlockInitialization
Product Terms
From Logic Allocator
Block CLK0
Block CLK1
Block CLK2
Block CLK3
To Output and InputSwitch Matrices
Common PAL-block resource
Individual macrocell resources
From PAL-ClockGenerator
D/T/L QAP AR
Power-UpReset
IndividualInitialization
Product Term
From LogicAllocator
Block CLK0
Block CLK1
To Output and InputSwitch Matrices
Individual ClockProduct Term
From PAL-BlockClock Generator
SWAP
17466G-010
Figure 5. Macrocell
17466G-009
a. Synchronous mode
b. Asynchronous mode
10 ispMACH 4A Family
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH.
D QAP AR
D QAP AR
L QAP AR
L QAP AR
GG
T QAP AR
17466G-011
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
a. D-type with XOR b. D-type with programmable D polarity
c. Latch with XOR d. Latch with programmable D polarity
e. T-type with programmable T polarity
f. Combinatorial with XOR
ispMACH 4A Family 11
Note:1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be programmed.
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire PAL block.
Table 8. Register/Latch Operation
Configuration Input(s) CLK/LE 1 Q+
D-type Register
D=X
D=0
D=1
0,1, ↓ (↑)
↑ (↓)
↑ (↓)
Q
0
1
T-type Register
T=X
T=0
T=1
0, 1, ↓ (↑)
↑ (↓)
↑ (↓)
Q
Q
Q
D-type Latch
D=X
D=0
D=1
1(0)
0(1)
0(1)
Q
0
1
Power-UpReset
APD/T/L
ARQ
PAL-BlockInitialization
Product Terms
a. Power-up reset
Power-UpPreset
APD/L
PAL-BlockInitialization
Product Terms
ARQ
17466G-012 17466G-013
Figure 7. Synchronous Mode Initialization Configurations
b. Power-up preset
12 ispMACH 4A Family
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired. The input switch matrix can send the signal back to the central switch matrix as feedback.
Note:1. Transparent latch is unaffected by AR, AP
Table 9. Asynchronous Reset/Preset Operation
AR AP CLK/LE1 Q+
0 0 X See Table 8
0 1 X 1
1 0 X 0
1 1 X 0
Power-UpReset
APD/L/T
ARQ
IndividualReset
Product Term
a. Reset
Power-UpPreset
APD/L/T
ARQ
IndividualPreset
Product Term
b. Preset
17466G-014 17466G-015
Figure 8. Asynchronous Mode Initialization Configurations
ispMACH 4A Family 13
Output Switch Matrix
The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout.
In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells; each macrocell has a choice of four I/O cells. The ispMACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells (Figure 9).
Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio
Macrocell Routable to I/O Cells
M0, M1 I/O0, I/O5, I/O6, I/O7
M2, M3 I/O0, I/O1, I/O6, I/O7
M4, M5 I/O0, I/O1, I/O2, I/O7
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4
M10, M11 I/O2, I/O3, I/O4, I/O5
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Each macrocell can driveone of 4 I/O cells in
ispMACH 4A devices with2:1 macrocell-I/O cell ratio.
Each I/O cell canchoose one of 8
macrocells inall ispMACH 4A
devices.
mac
roce
lls
MU
X
I/O c
ell
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Each macrocell can driveone of 8 I/O cells in
ispMACH 4A devices with 1:1macrocell-I/O cell ratio except
M4A(3, 5)-32/32 devices.
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Each macrocell can driveone of 8 I/O cells in
M4A(3, 5)-32/32 devices.
Figure 9. ispMACH 4A Output Switch Matrix
14 ispMACH 4A Family
M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7
I/O Cell Available Macrocells
I/O0 M0, M1, M2, M3, M4, M5, M6, M7
I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M0, M1, M10, M11, M12, M13, M14, M15
I/O6 M0, M1, M2, M3, M12, M13, M14, M15
I/O7 M0, M1, M2, M3, M4, M5, M14, M15
Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192
Macrocell Routable to I/O Cells
M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
I/O Cell Available Macrocells
I/O0 M0 M1 M2 M3 M4 M5 M6 M7
I/O1 M0 M1 M2 M3 M4 M5 M6 M7
I/O2 M0 M1 M2 M3 M4 M5 M6 M7
I/O3 M0 M1 M2 M3 M4 M5 M6 M7
I/O4 M0 M1 M2 M3 M4 M5 M6 M7
I/O5 M0 M1 M2 M3 M4 M5 M6 M7
I/O6 M0 M1 M2 M3 M4 M5 M6 M7
I/O7 M0 M1 M2 M3 M4 M5 M6 M7
Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio
Macrocell Routable to I/O Cells
ispMACH 4A Family 15
Table 13. Output Switch Matrix Combinations for M4A3-64/64
I/O8 M8 M9 M10 M11 M12 M13 M14 M15
I/O9 M8 M9 M10 M11 M12 M13 M14 M15
I/O10 M8 M9 M10 M11 M12 M13 M14 M15
I/O11 M8 M9 M10 M11 M12 M13 M14 M15
I/O12 M8 M9 M10 M11 M12 M13 M14 M15
I/O13 M8 M9 M10 M11 M12 M13 M14 M15
I/O14 M8 M9 M10 M11 M12 M13 M14 M15
I/O15 M8 M9 M10 M11 M12 M13 M14 M15
Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32
Macrocell Routable to I/O Cells
M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
I/O Cell Available Macrocells
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15
Macrocell Routable to I/O Cells
MO, M1 I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
M2, M3 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15
M4, M5 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15
M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
M8, M9 I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9
M10, M11 I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11
M12, M13 I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13
M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
I/O Cell Available Macrocells
I/O0, I/O1 M0, M1, M2, M3, M4, M5, M6, M7
I/O2, I/O3 M2, M3, M4, M5, M6, M7, M8, M9
I/O4, I/O5 M4, M5, M6, M7, M8, M9, M10, M11
I/O6, I/O7 M6, M7, M8, M9, M10, M11, M12, M13
I/O8, I/O9 M8, M9, M10, M11, M12, M13, M14, M15
I/O10, I/O11 M0, M1, M10, M11, M12, M13, M14, M15
I/O12, I/O13 M0, M1, M2, M3, M12, M13, M14, M15
I/O14, I/O15 M0, M1, M2, M3, M4, M5, M14, M15
Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192
Macrocell Routable to I/O Cells
16 ispMACH 4A Family
I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable product term is provided for each I/O cell. The feedback signal drives the input switch matrix.
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the second data value is put on the I/O pin and compared with the previous stored value.
Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells. It powers up to a logic low.
Zero-Hold-Time Input Register
The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges.
D/L Q
Block CLK3Block CLK2Block CLK1Block CLK0
To InputSwitchMatrix
IndividualOutput EnableProduct Term
From OutputSwitch Matrix
17466G-017 17466G-018
Figure 10. I/O Cell for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio
Figure 11. I/O Cell for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio
To InputSwitchMatrix
IndividualOutput EnableProduct Term
From OutputSwitch Matrix
Power-up reset
ispMACH 4A Family 17
Input Switch Matrix
The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix.
To
Cen
tral
Sw
itch
Mat
rix
Fro
m M
acro
cell
2
From Input Cell
Dire
ct
Fro
m M
acro
cell
1
Reg
iste
red/
Latc
hed
17466G-002 17466G-003
Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix
Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell Ratio - Input Switch Matrix
To
Cen
tral
Sw
itch
Mat
rix Fro
m M
acro
cell
Fro
m I/
O P
in
18 ispMACH 4A Family
PAL Block Clock Generation
Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. Table 14 lists the possible combinations.
1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1.
Note:1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.
This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration.
Table 14. PAL Block Clock Combinations1
Block CLK0 Block CLK1 Block CLK2 Block CLK3
GCLK0
GCLK1
GCLK0
GCLK1
X
X
X
X
GCLK1
GCLK1
GCLK0
GCLK0
X
X
X
X
X
X
X
X
GCLK2 (GCLK0)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK3 (GCLK1)
X
X
X
X
GCLK3 (GCLK1)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK2 (GCLK0)
GCLK0
GCLK1
GCLK2
GCLK3
Block CLK0(GCLK0 or GCLK1)
Block CLK1(GCLK1 or GCLK0)
Block CLK2(GCLK2 or GCLK3)
Block CLK3(GCLK3 or GCLK2)
17466G-004
Figure 14. PAL Block Clock Generator 1
ispMACH 4A Family 19
ispMACH 4A TIMING MODEL
The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH 4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized ispMACH 4A timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed discussion about the timing parameters.
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs easy access to the performance required in today’s designs.
(External Feedback)
(Internal Feedback)
INPUT REG/INPUT LATCH
tSIRS tHIRStSILtHILtSIRZtHIRZtSILZtHILZ
tPDILi tICOSi tIGOSi tPDILZi
Q
tSS(T)tSA(T)tH(S/A)tS(S/A)LtH(S/A)LtSRR
tPDi tPDLi tCO(S/A)itGO(S/A)itSRi
COMB/DFF/TFF/LATCH/SR*/JK*
S/R
IN
BLK CLK
OUT
tPL
tBUF
tEAtER
tSLW
Q
CentralSwitchMatrix
*emulated
17466G-025
Figure 15. ispMACH 4A Timing Model
20 ispMACH 4A Family
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY
All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing.
IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 4A devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface.
ispMACH 4A devices can be programmed across the commercial temperature and voltage range. The PC-based ispVM™ software facilitates in-system programming of ispMACH 4A devices. ispVM takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. ispVM software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, ispVM software can output files in formats understood by common automated test equipment. This equpment can then be used to program ispMACH 4A devices during the testing of a circuit board.
PCI COMPLIANT
ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
Both the 3.3-V and 5-V VCC ispMACH 4A devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixed-voltage design capability.
PULL UP OR BUS-FRIENDLY INPUTS AND I/Os
All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are
ispMACH 4A Family 21
weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each ispMACH 4A device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the ispMACH 4A devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
HOT SOCKETING
ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH devices be minimal on active signals.
22 ispMACH 4A Family
MACROCELLM0C0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
B
89
M0
M4A(3, 5)-64/32M4A3-64/64M4A(3, 5)-96/48M4A(3, 5)-128/64
AB
1617
1717
M4(3, 5)-192/96M4(3, 5)-256/128
M4A3-384M4A3-512
1818
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
O0
O1
O2
O3
O4
O5
O6
O7M15
CLK
0C
LK1
CLK
2C
LK3
I/OCELL
I/O0
CLOCKGENERATOR
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
CEN
TRAL
SW
ITC
H M
ATR
IX
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
24
A
04
16
16
C1
C2
I/OCELL
I/O1
C3
C4
I/OCELL
I/O2
C5
C6
I/OCELL
I/O3
C7
C8
I/OCELL
I/O4
C9
C10
I/OCELL
I/O5
C11
C12I/O
CELL
I/O6
C13
C14
I/OCELL
INPUT SWITCHMATRIX
I/O7
C15
LOG
IC A
LLO
CAT
OR
OU
TPU
T SW
ITC
H M
ATR
IX
Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio
ispMACH 4A Family 23
Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)
MACROCELLM0C0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
B
97
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
O0
O2
O4
O6
O8
O10
O12
O14
M15
I/OCELL
I/O0
CLOCKGENERATOR
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
CE
NT
RA
L S
WIT
CH
MAT
RIX
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
O1I/O
CELL
I/O1
32
A
04
16
16
C1
C2 I/OCELL
I/O2
O3I/O
CELL
I/O3
O5I/O
CELL
I/O5
O7I/O
CELL
I/O7
C3
C4I/O
CELL
I/O4
C5
C6I/O
CELL
I/O6
C7
C8I/O
CELL
I/O8
O9I/O
CELL
I/O9
O11I/O
CELL
I/O11
C9
C10 I/OCELL
I/O10
C11
C12I/O
CELL
I/O12
O13I/O
CELL
I/O13
O15I/O
CELL
I/O15
C13
C14 I/OCELL
INPUTSWITCHMATRIX
I/O14
C15
LOG
IC A
LLO
CAT
OR
OU
TP
UT
SW
ITC
H M
ATR
IX
CLK
0C
LK1
CLK
2C
LK3
M4A3-64/64
AB
1617
1818
M4A3-256/160M4A3-256/192
17466H-41
24 ispMACH 4A Family
17466H-042
MACROCELLM0C0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
17
97
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
O0
O2
O4
O6
O8
O10
O12
O14
M15
I/OCELL
I/O0
CLOCKGENERATOR
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
CE
NT
RA
L S
WIT
CH
MAT
RIX
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
O1I/O
CELL
I/O1
32
16
02
16
16
C1
C2 I/OCELL
I/O2
O3I/O
CELL
I/O3
O5I/O
CELL
I/O5
O7I/O
CELL
I/O7
C3
C4I/O
CELL
I/O4
C5
C6I/O
CELL
I/O6
C7
C8I/O
CELL
I/O8
O9I/O
CELL
I/O9
O11I/O
CELL
I/O11
C9
C10 I/OCELL
I/O10
C11
C12I/O
CELL
I/O12
O13I/O
CELL
I/O13
O15I/O
CELL
I/O15
C13
C14 I/OCELL
INPUTSWITCHMATRIX
I/O14
C15
LOG
IC A
LLO
CAT
OR
OU
TP
UT
SW
ITC
H M
ATR
IXO
UT
PU
T S
WIT
CH
MAT
RIX
CLK0/I0 CLK0/I1
Figure 18. PAL Block for M4A (3,5)-32/32
ispMACH 4A Family 25
BLOCK DIAGRAM – M4A(3,5)-32/32
17466H-019
Central Switch Matrix22
CLK
0/I0
, CLK
1/I1
I/O8–I/O15 I/O0–I/O7
I/O16–I/O23 I/O24–I/O31
I/O Cells
Output SwitchMatrix
Macrocells
8
8
16
8
8
8
33
4
4 4
4
8
8
I/O Cells
Output SwitchMatrix
Macrocells
66 X 98AND Logic Array
and Logic AllocatorC
lock
Gen
erat
or
Inpu
t Sw
itch
Mat
rix
8
8
16
8
8
8
2
8
8
I/O Cells
Output SwitchMatrix
Macrocells
8
8
16
8
8
8
8
8
I/O Cells
Output SwitchMatrix
Macrocells
66 X 98AND Logic Array
and Logic Allocator
8
8
16
8
8
8
2
8
8
Inpu
t Sw
itch
Mat
rixIn
put S
witc
hM
atrix
Inpu
t Sw
itch
Mat
rix
Clo
ck G
ener
ator
OE
OE
OEOE
Block A
Block B
33
26 ispMACH 4A Family
BLOCK DIAGRAM – M4A(3,5)-64/32
17466H-020
Central Switch Matrix22
CLK
0/I0
, CLK
1/I1
I/O0–I/O7 I/O24–I/O31
I/O16–I/O23I/O8–I/O15
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
16
16
24
16
16
8
33
4
4
2
8
8
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
16
16
24
16
16
8
33
4
4
2
8
8
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
16
16
24
16
16
8
33
4
4
2
8
8
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
16
16
24
16
16
8
33
4
4
2
8
8
Inpu
t Sw
itch
Mat
rixIn
put S
witc
hM
atrix
Inpu
t Sw
itch
Mat
rix
Clo
ck G
ener
ator
Clo
ck G
ener
ator
OE
OE
OE
OE
Block A
Block B
Block D
Block C
ispMACH 4A Family 27
BLOCK DIAGRAM – M4A3-64/64
Central Switch Matrix44
CLK
0/I0
, CLK
1/I1
CLK
2/I3
, CLK
3/I4
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
16
16
16
16
16
33
4
4
16
16
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
16
16
16
16
16
33
4
4
16
16
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
16
16
16
16
16
33
4
4
16
16
I/O Cells
Output SwitchMatrix
Macrocells
66 X 90AND Logic Array
and Logic Allocator
16
16
16
16
16
33
4
4
16
16
Clo
ck G
ener
ator
Clo
ck G
ener
ator
OE
OE
OE
OE
Block A
Block B
Block D
Block C
2
17466H-020A
28 ispMACH 4A Family
BLOCK DIAGRAM – M4A(3,5)-96/48
44
4
CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5
I2, I3, I6, I7
I/O16
–I/O
23I/O
8–I/O
15I/O
0–I/O
7
I/O40
–I/O
47I/O
32–I
/O39
I/O24
–I/O
31
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
Clock Generator
16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
Clock Generator
Input SwitchMatrix16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
Clock Generator
Input SwitchMatrix16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
161624
16 16
8
33
44
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
161624
16 16
8
33
44
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
161624
16 16
8
33
44
4
8
8OE
Input SwitchMatrix
Input SwitchMatrix
Input SwitchMatrix
Clock Generator
Clock Generator
Clock Generator
Input SwitchMatrix
OE
OE
OE
OE
OE
Blo
ck C
Blo
ck B
Blo
ck A
Blo
ck D
Blo
ck E
Blo
ck F
Cen
tral
Sw
itch
Mat
rix
17466G-021
ispMACH 4A Family 29
BLOCK DIAGRAM – M4A(3,5)-128/64
Cen
tral
Sw
itch
Mat
rix
44
2
CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4
I2, I5
I/O0–
I/O7
I/O8–
I/O15
I/O16
–I/O
23I/O
24–I
/031
I/O32
–I/O
39I/O
40–I
/O47
I/O48
–I/O
55I/O
56–I
/O63
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
Clock Generator
16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
Clock Generator
Input SwitchMatrix16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
Clock Generator
Input SwitchMatrix16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
rClock Generator
Input SwitchMatrix16 16 24
1616
8
33
4 4
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
161624
16 16
8
33
44
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
161624
16 16
8
33
44
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
r
161624
16 16
8
33
44
4
8
8
I/O C
ells
Out
put S
witc
hM
atrix
Mac
roce
lls
66 X
90
AN
D L
ogic
Arr
ayan
d Lo
gic
Allo
cato
rOE
161624
16 16
8
33
44
4
8
8
Input SwitchMatrix
Input SwitchMatrix
Input SwitchMatrix
Clock Generator
Clock Generator
Clock Generator
Input SwitchMatrix
Input SwitchMatrix
Clock Generator
OE
OE
OE
OE
OE
OE
OE
Blo
ck A
Blo
ck B
Blo
ck C
Blo
ck D
Blo
ck H
Blo
ck G
Blo
ck F
Blo
ck E
17466H-022
ispMACH 4A Family 30
BLOCK DIAGRAM – M4A(3,5)-192/96
Cen
tral
Sw
itch
Mat
rix
Block BI/O88—I/O95 CLK0—CLK3
I/O16—I/O23Block E
I/O40—I/O47Block H
I/O32—I/O39Block G
I0—I15I/O24—I/O31Block F
Block AI/O80—I/O87
Block KI/O64—I/O71
Block LI/O72—I/O79
Block C I/O8—I/O15Block D I/O0—I/O7
I/O56—I/O63 Block JI/O48—I/O55 Block I
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic AllocatorC
lock
Gen
erat
or
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
16
4 4
OE
8
16
8
4
16
24
8
16
16
34
4
4
8
24 34
4
8
8
16
16
4
4
16
16
OE
8
24 34
4
8
8
16
16
4
4
16
16
OE
8
16
8
4
16
24
8
16
16
34
34 34 34 34
34 34 34 34
4
4
OE
OE
8
16
8
4
16
24
8
16
16
4
4
8
24
4
8
8
16
16
4
4
16
16
OE
8
24
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
24
16
16
8
16 8
4
16
OE
4
4
24
16
16
8
16
16
4
8
8
OE
4
4
24
16
16
8
16
16
4
8
8
4
4
8
24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
4
4
OE
17466G-067
ispMACH 4A Family 31
BLOCK DIAGRAM – M4A(3,5)-256/128
Cen
tral
Sw
itch
Mat
rix
Block BI/O8–I/O15 CLK0–CLK3
I/O48–I/O55Block G
I/O72–I/O79Block J
I/O64–I/O71Block I
I0–I13I/O56–I/O63Block H
Block AI/O0–I/O7
Block OI/O112–I/O119
Block PI/O120–I/O127
Block C I/O16–I/O23Block D I/O24–I/O31Block E I/O32–I/O39Block F I/O40–I/O47
I/O104–I/O111 Block NI/O96–I/O103 Block MI/O88–I/O95 Block LI/O80–I/O87 Block K
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
68 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
14
4 4
OE
8
16
8
4
16
24
8
16
16
34
4
4
8
24 34
4
8
8
16
16
4
4
16
16
OE
8
24 34
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
34 24
16
16
8
16 8
4
16
OE
4
4
34 24
16
16
8
16
16
4
8
8
OE
4
4
34 24
16
16
8
16
16
4
8
8
4
4
8
34 24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
34
4
4
OE
OE
8
16
8
4
16
24
8
16
16
34
4
4
8
24 34
4
8
8
16
16
4
4
16
16
OE
8
24 34
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
34 24
16
16
8
16 8
4
16
OE
4
4
34 24
16
16
8
16
16
4
8
8
OE
4
4
34 24
16
16
8
16
16
4
8
8
4
4
8
34 24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
34
4
4
OE
17466G-024
32 ispMACH 4A Family
BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192
Cen
tral
Sw
itch
Mat
rix
Block B CLK0–CLK3
Block G Block JBlock IBlock H
Block A Block OBlock P
Block CBlock DBlock EBlock F
Block NBlock MBlock LBlock K
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 98AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
4 4
OE
16
16
16
4
16
32
16
16
16
36
4
4
16
32 36
4
16
16
16
16
4
4
16
16
OE
16
32 36
4
16
16
16
16
4
4
16
16O
E
OE
4
4
16
36 32
16
16
16
16 16
4
16
OE
4
4
36 32
16
16
16
16
16
4
16
16
OE
4
4
36 32
16
16
16
16
16
4
16
16
4
4
16
36 32
16
16
16
16 16
4
16
OE
16
16
16
4
16
32
16
16
16
36
4
4
OE
OE
16
16
16
4
16
32
16
16
16
36
4
4
16
32 36
4
16
16
16
16
4
4
16
16
OE
16
32 36
4
16
16
16
16
4
4
16
16
OE
OE
4
4
16
36 32
16
16
16
16 16
4
16
OE
4
4
36 32
16
16
16
16
16
4
16
16
OE
4
4
36 32
16
16
16
16
16
4
16
16
4
4
16
36 32
16
16
16
16 16
4
16
OE
16
16
16
4
16
32
16
16
16
36
4
4
OE
17466G-050
ispMACH 4A Family 33
BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192
Cen
tral
Sw
itch
Mat
rix
Block BCLK0–CLK3
Block A Block GXBlock HX
Block CBlock F
Block DBlock E
Block FXBlock CX
Block EXBlock DX
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
4 4
4
OE
8
16
8
4
16
24
8
16
16
36
4
4
8
24 36
4
8
8
16
16
4
4
16
16
OE
8
24 36
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
36 24
16
16
8
16 8
4
16
OE
4
4
36 24
16
16
8
16
16
4
8
8
OE
4
4
36 24
16
16
8
16
16
4
8
8
4
4
8
36 24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
36
4
4
OE
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rixOutput Switch
Matrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
OE
8
16
8
4
16
24
8
16
16
36
4
4
8
24 36
4
8
8
16
16
4
4
16
16
OE
8
24 36
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
36 24
16
16
8
16 8
4
16
OE
4
4
36 24
16
16
8
16
16
4
8
8
OE
4
4
36 24
16
16
8
16
16
4
8
8
4
4
8
36 24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
36
4
4
OE
Block GBlock J
Block HBlock I
Block BXBlock O
Block AXBlock P
Detail A
Repeat Detail A
Block LBlock K Block M Block N
17466G-067
34 ispMACH 4A Family
BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256
Cen
tral
Sw
itch
Mat
rix
Block B
CLK0–CLK3
Block A Block OXBlock PX
Block C Block F
Block DBlock E
Block NXBlock KX
Block MXBlock LX
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
OE
8
16
8
4
16
24
8
16
16
36
4
4
8
24 36
4
8
8
16
16
4
4
16
16
OE
8
24 36
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
36 24
16
16
8
16 8
4
16
OE
4
4
36 24
16
16
8
16
16
4
8
8
OE
4
4
36 24
16
16
8
16
16
4
8
8
4
4
8
36 24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
36
4
4
OE
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
I/O Cells
Macrocells
72 X 90AND Logic Array
and Logic Allocator
Clo
ck G
ener
ator
Inpu
t Sw
itch
Mat
rix
Output SwitchMatrix
OE
8
16
8
4
16
24
8
16
16
36
4
4
8
24 36
4
8
8
16
16
4
4
16
16
OE
8
24 36
4
8
8
16
16
4
4
16
16
OE
OE
4
4
8
36 24
16
16
8
16 8
4
16
OE
4
4
36 24
16
16
8
16
16
4
8
8
OE
4
4
36 24
16
16
8
16
16
4
8
8
4
4
8
36 24
16
16
8
16 8
4
16
OE
8
16
8
4
16
24
8
16
16
36
4
4
OE
Block GBlock J
Block HBlock I
Block JXBlock GX
Block IXBlock HX
Block KBlock N
Block LBlock M
Block FXBlock CX
Block EXBlock DX
Detail A
Repeat Detail A
Repeat Detail A
Block PBlock O Block AX Block BX
4 4
4
17466G-068
ispMACH 4A Family 35
ABSOLUTE MAXIMUM RATINGS
M4A5Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . . . . . . -55°C to +100°C
Device Junction Temperature. . . . . . . . . . . . . . . . . . . . +130°C
Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Latchup Current (TA = -40°C to +85°C) . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause per-manent device failure. Functionality at or above these limits is not implied. Expo-sure to Absolute Maximum Ratings for extended periods may affect devicereliability.
OPERATING RANGES
Commercial (C) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . +4.75 V to +5.25 V
Industrial (I) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +4.50 V to +5.5 V
Operating ranges define those limits between which the functionality of the device isguaranteed.
Notes:1. Total IOL for one PAL block should not exceed 64 mA.
2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
5-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH VoltageIOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V
IOH = -100 µA, VCC = Max, VIN = VIH or VIL 3.3 3.6 V
VOL Output LOW Voltage IOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) 0.5 V
VIH Input HIGH VoltageGuaranteed Input Logical HIGH Voltage for all Inputs (Note 2)
2.0 V
VIL Input LOW VoltageGuaranteed Input Logical LOW Voltage for all Inputs (Note 2)
0.8 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 μA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –10 μA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) 10 μA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) –10 μA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –30 –160 mA
36 ispMACH 4A Family
ABSOLUTE MAXIMUM RATINGS
M4A3Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . . . . . . -55°C to +100°C
Device Junction Temperature. . . . . . . . . . . . . . . . . . . . +130°C
Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . .-0.5 V to +4.5 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Latchup Current (TA = -40°C to +85°C) . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause per-manent device failure. Functionality at or above these limits is not implied. Expo-sure to Absolute Maximum Ratings for extended periods may affect devicereliability.
OPERATING RANGES
Commercial (C) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . . +3.0 V to +3.6 V
Industrial (I) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the device isguaranteed.
Notes:1. Total IOL for one PAL block should not exceed 64 mA.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
Notes:1. See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site.
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
3.3-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH VoltageVCC = Min VIN = VIH or VIL
IOH = –100 μA VCC – 0.2 V
IOH = –3.2 mA 2.4 V
VOL Output LOW VoltageVCC = Min VIN = VIH or VIL (Note 1)
IOL = 100 μA 0.2 V
IOL = 24 mA 0.5 V
VIH Input HIGH VoltageGuaranteed Input Logical HIGH Voltage for all Inputs
2.0 5.5 V
VIL Input LOW VoltageGuaranteed Input Logical LOW Voltage for all Inputs
–0.3 0.8 V
IIH Input HIGH Leakage Current VIN = 3.6 V, VCC = Max (Note 2) 5 μA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –5 μA
IOZH Off-State Output Leakage Current HIGHVOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2)
5 μA
IOZL Off-State Output Leakage Current LOWVOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2)
–5 μA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –15 –160 mA
ispMACH 4A Family 37
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 -55 -6 -65 -7 -10 -12 -14
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Combinatorial Delay:
tPDiInternal combinatorial propagation delay
3.5 4.0 4.3 4.5 5.0 7.0 9.0 11.0 ns
tPD Combinatorial propagation delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns
Registered Delays:
tSSSynchronous clock setup time, D-type register
3.0 3.5 3.5 3.5 5.0 5.5 7.0 10.0 ns
tSSTSynchronous clock setup time, T-type register
4.0 4.0 4.0 4.0 6.0 6.5 8.0 11.0 ns
tSAAsynchronous clock setup time, D-type register
2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns
tSATAsynchronous clock setup time, T-type register
3.0 3.0 3.0 3.5 4.5 5.0 6.0 9.0 ns
tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns
tHA Asynchronous clock hold time 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns
tCOSi Synchronous clock to internal output 2.5 2.5 2.8 3.0 3.0 3.0 3.5 3.5 ns
tCOS Synchronous clock to output 4.0 4.0 4.5 5.0 5.5 6.0 6.5 6.5 ns
tCOAi Asynchronous clock to internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns
tCOA Asynchronous clock to output 6.5 6.5 6.8 7.0 8.5 11.0 13.0 15.0 ns
Latched Delays:
tSSL Synchronous latch setup time 4.0 4.0 4.0 4.5 6.0 7.0 8.0 10.0 ns
tSAL Asynchronous latch setup time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns
tHSL Synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns
tHAL Asynchronous latch hold time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns
tPDLi Transparent latch to internal output 5.5 5.5 5.8 6.0 7.5 9.0 11.0 12.0 ns
tPDLPropagation delay through transparent latch to output
7.0 7.0 7.5 8.0 10.0 12.0 14.0 15.0 ns
tGOSi Synchronous gate to internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns
tGOS Synchronous gate to output 4.5 4.5 4.8 5.0 6.0 7.5 10.0 11.0 ns
tGOAi Asynchronous gate to internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns
tGOA Asynchronous gate to output 7.5 7.5 7.8 8.0 11.0 13.0 16.0 18.0 ns
Input Register Delays:
tSIRS Input register setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns
tHIRS Input register hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns
tICOSi Input register clock to internal feedback 3.0 3.0 3.0 3.0 3.5 4.5 6.0 6.0 ns
Input Latch Delays:
tSIL Input latch setup time 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 ns
tHIL Input latch hold time 2.5 2.5 2.5 3.0 3.0 3.0 3.0 4.0 ns
tIGOSi Input latch gate to internal feedback 3.5 3.5 3.8 4.0 4.0 4.0 4.0 5.0 ns
tPDILiTransparent input latch to internal feedback
1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns
38 ispMACH 4A Family
Input Register Delays with ZHT Option:
tSIRZ Input register setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns
tHIRZ Input register hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns
Input Latch Delays with ZHT Option:
tSILZ Input latch setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns
tHILZ Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns
tPDIL
Zi
Transparent input latch to internal feedback - ZHT
6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns
Output Delays:
tBUF Output buffer delay 1.5 1.5 1.8 2.0 2.5 3.0 3.0 3.0 ns
tSLW Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
tEA Output enable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns
tER Output disable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns
Power Delay:
tPL Power-down mode delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
Reset and Preset Delays:
tSRiAsynchronous reset or preset to internal register output
7.5 7.7 8.0 8.0 9.5 11.0 13.0 16.0 ns
tSRAsynchronous reset or preset to register output
9.0 9.2 10.0 10.0 12.0 14.0 16.0 19.0 ns
tSRRAsynchronous reset and preset register recovery time
7.0 7.0 7.5 7.5 8.0 8.0 10.0 15.0 ns
tSRW Asynchronous reset or preset width 7.0 7.0 8.0 8.0 10.0 10.0 12.0 15.0 ns
Clock/LE Width:
tWLS Global clock width low 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns
tWHS Global clock width high 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns
tWLA Product term clock width low 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns
tWHA Product term clock width high 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns
tGWS
Global gate width low (for low transparent) or high (for high transparent)
4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns
tGWA
Product term gate width low (for low transparent) or high (for high transparent)
4.0 4.0 4.5 4.5 5.0 5.0 6.0 9.0 ns
tWIRL Input register clock width low 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns
tWIRH Input register clock width high 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns
tWIL Input latch gate width 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 -55 -6 -65 -7 -10 -12 -14
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
ispMACH 4A Family 39
Notes:1. See “Switching Test Circuit” document on the Literature Download page of the Lattice web site.
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
CAPACITANCE 1
Note:1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may be affected.
Frequency:
fMAXS
External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS)
143 133 125 118 95.2 87.0 74.1 60.6 MHz
External feedback, T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOS)
125 125 118 111 87.0 80.0 69.0 57.1 MHz
Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi)
182 167 160 154 125 118 95.0 74.1 MHz
Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi)
154 154 148 143 111 105 87.0 69.0 MHz
No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 1/(tSST + tHS)
250 250 200 200 154 125 100 83.3 MHz
fMAXA
External feedback, D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA)
111 111 108 100 83.3 66.7 55.6 43.5 MHz
External feedback, T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOA)
105 105 102 95.2 76.9 62.5 52.6 41.7 MHz
Internal feedback (fCNTA), D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi)
133 133 125 125 105 83.3 66.7 50.0 MHz
Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi)
125 125 125 118 95.2 76.9 62.5 47.6 MHz
No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA)
167 167 143 143 125 100 62.5 55.6 MHz
fMAXIMaximum input register frequency, Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS)
167 167 143 143 125 100 83.3 83.3 MHz
Parameter Symbol Parameter Description Test Conditions Typ Unit
CIN Input capacitance VIN=2.0 V 3.3 V or 5 V, 25°C, 1 MHz 6 pF
CI/O Output capacitance VOUT=2.0V 3.3 V or 5 V, 25°C, 1 MHz 8 pF
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 -55 -6 -65 -7 -10 -12 -14
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
40 ispMACH 4A Family
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power.
350
300
250
200
150
100
50
0
0 20 40 60 80 100
120
140
160
180
200
VCC = 5 V or 3.3 V, TA = 25º C
I CC
(m
A)
Frequency (MHz)
M4A-32/32
M4A-64/32
M4A-128/64
M4A-256/128
Figure 19. ispMACH 4A ICC Curves at High Speed Mode
M4A-256/160
M4A-64/64
M4A-96/48
400M4A-512/160
M4A-192/96
M4A-384/160
250
200
150
100
50
0
0 20 40 60 80 100
120
140
160
180
200
VCC = 5 V or 3.3 V, TA = 25º C
M4A-32/32
I CC
(m
A)
Frequency (MHz)
M4A-64/32
M4A-128/64
M4A-256/128
Figure 20. ispMACH 4A ICC Curves at Low Power Mode
M4A-256/160
M4A-64/64
M4A-96/48
M4A-512/160
M4A-192/96
M4A-384/160
ispMACH 4A Family 41
44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)
Top View44-Pin PLCC
PIN DESIGNATIONSCLK/I = Clock or Input
GND = Ground
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
1 44 43 425 4 3 26 41 40
7
8
9
10
11
12
13
14
15
16
17
23 24 25 2619 20 21 2218 27 28
39
38
37
36
35
34
33
32
31
30
29
I/O5
I/O6
I/O7
TDI
CLK0/I0
GND
TCK
I/O8
I/O9
I/O10
I/O11
A2
A1
A0
B0
B1
B2
B3
D3
D2
D1
D0
C0
C1
C2
B3
B2
B1
B0
B8
B9
B10
A2
A1
A0
A8
A9
A10
A11
I/O27
I/O26
I/O25
I/O24
TDO
GND
CLK1/I1
TMS
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
VC
C
GN
D
I/O16
I/O17
I/O18
I/O19
I/O20
B4
B5
B6
B7
C7
C6
C5
C4
C3
A12
A13
A14
A15
B15
B14
B13
B12
B11
I/O4
I/O3
I/O2
I/O1
I/O0
GN
D
VC
C
I/O31
I/O30
I/O29
I/O28
A3
A4
A5
A6
A7
D7
D6
D5
D4
A3
A4
A5
A6
A7
B7
B6
B5
B4
M4A(3,5)-32/32M4A(3,5)-32/32
M4A(3,5)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
17466G-026
I/O Cell
PAL Block
C 7
42 ispMACH 4A Family
44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)
Top View 44-Pin TQFP (1.0mm Thickness)
PIN DESIGNATIONSCLK/I = Clock or Input
GND = Ground
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
I/O12
I/O13
I/O14
I/O15
VC
CG
ND
I/O16
I/O17
I/O18
I/O19
I/O20
B4
B5
B6
B7
C7
C6
C5
C4
C3
A12
A13
A14
A15
B15
B14
B13
B12
B11
I/O4
I/O3
I/O2
I/O1
I/O0
GN
DV
CC
I/O31
I/O30
I/O29
I/O28
A3
A4
A5
A6
A7
D7
D6
D5
D4
A3
A4
A5
A6
A7
B7
B6
B5
B4
I/O27I/O26I/O25I/O24TDOGNDCLK1/I1TMSI/O23I/O22I/O21
D3D2D1D0
C0C1C2
B3B2B1B0
B8B9B10
I/O5I/O6I/O7TDI
CLK0/I0GNDTCKI/O8I/O9
I/O10I/O11
A2A1A0
B0B1B2B3
A2A1A0
A8A9
A10A11
1234567891011
3332313029282726252423
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
M4A(3,5)-32/32M4A(3,5)-32/32
M4A(3,5)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
I/O CellPAL Block
C 7
ispMACH 4A Family 43
48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)
Top View48-Pin TQFP (1.4mm Thickness)
PIN DESIGNATIONSCLK/I = Clock or Input
GND = Ground
I/O = Input/Output
VCC = Supply Voltage
NC = No Connect
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
I/O12
I/O13
I/O14
I/O15
VC
CN
CG
ND
I/O16
I/O17
I/O18
I/O19
I/O20
B4
B5
B6
B7
C7
C6
C5
C4
C3
A12
A13
A14
A15
B15
B14
B13
B12
B11
I/O4
I/O3
I/O2
I/O1
I/O0
GN
DN
CV
CC
I/O31
I/O30
I/O29
I/O28
A3
A4
A5
A6
A7
D7
D6
D5
D4
A3
A4
A5
A6
A7
B7
B6
B5
B4
I/O27I/O26I/O25I/O24TDOGNDNCCLK1/I1TMSI/O23I/O22I/O21
D3D2D1D0
C0C1C2
B3B2B1B0
B8B9B10
I/O5I/O6I/O7TDI
CLK0/I0NC
GNDTCKI/O8I/O9
I/O10I/O11
A2A1A0
B0B1B2B3
A2A1A0
A8A9
A10A11
123456789101112
33343536
3231302928272625
4445464748 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
M4A(3,5)-32/32M4A(3,5)-32/32
M4A(3,5)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
I/O CellPAL Block
C 7
17466G-028
44 ispMACH 4A Family
100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48)
Top View100-Pin TQFP
PIN DESIGNATIONSCLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
NC = No Connect
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
12345678910111213141516171819202122232425
NCTDINCNC
I/O6I/O7I/O8I/O9
I/O10I/O11
I0/CLK0VCC
GNDI1/CLK1
I/O12I/O13I/O14I/O15I/O16I/O17
NCNC
TMSTCKNC
A1A0B0B1B2B3
B4B5B6B7C0C1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GN
DN
CN
CI/O
18I/O
19I/O
20I/O
21I/O
22I/O
23 NC I2
NC
NC
GN
DV
CC I3
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29 NC
NC
GN
D
C2
C3
C4
C5
C6
C7
D7
D6
D5
D4
D3
D2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GN
DN
CN
CI/O
5I/O
4I/O
3I/O
2I/O
1I/O
0I7 V
CC
GN
DN
CN
CI6 N
CI/O
47I/O
46I/O
45I/O
44I/O
43I/O
42N
CN
CG
ND
A2
A3
A4
A5
A6
A7
F7
F6
F5
F4
F3
F2
75747372717069686766656463626160595857565554535251
NCTDONCNCNCI/O41I/O40I/O39I/O38I/O37I/O36I5/CLK3GNDVCCI4/CLK2I/O35I/O34I/O33I/O32I/O31I/O30NCNCNCNC
F1F0E0E1E2E3
E4E5E6E7D0D1
17466G-029
I/O Cell
PAL Block
C 7
ispMACH 4A Family 45
100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64)
Top View100-Pin PQFP
PIN DESIGNATIONSI/CLK = Input or Clock
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
TRST = Test Reset
ENABLE = Program
I/O
7A
7A
6A
5A
4A
3A
2A
1A
0
D7
D6
D5
D4
D3
D2
D1
D0
I/O
6I/O
5I/O
4I/O
3I/O
2I/O
1I/O
0V
CC
GN
DG
ND
VC
CI/
O6
3I/
O6
2I/
O6
1I/
O6
0I/
O5
9I/
O5
8I/
O5
7I/
O5
6
H0
H1
H2
H3
H4
H5
H6
H7
GNDGND
TDII5
I/O8I/O9
I/O10I/O11I/O12I/O13I/O14I/O15
IO/CLK0
GNDGND
I1/CLK1I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23
B7B6B5B4B3B2B1B0
C0C1C2C3C4C5C6C7
TMSTCKGNDGND
282930
4 56789101112131415161718192021222324252627
123
99
98
10
03
13
23
33
43
53
63
73
83
94
04
14
24
34
44
54
64
74
84
95
0
97
96
95
94
93
92
91
90
89
88
87
86
85
84
82
81
83
I/O46I/O45I/O44I/O43I/O42I/O41I/O40I2ENABLEGNDGND
GNDTD0TRSTI/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O48
G7G6G5G4G3G2G1G0
I4/CLK3GNDGND
I3/CLK2I/O47
F1F2F3F4F5F6F7
F0
GND
777675747372717069686766656463626160595857565554535251
807978
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
GN
DG
ND
I/O
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
E0
E1
E2
E3
E4
E5
E6
E7
VCCVCC
VCCVCC
�
VC
C
VC
C
I/O Cell PAL Block
C 7
17466G-031
46 ispMACH 4A Family
100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64)
Top View100-Pin TQFP
PIN DESIGNATIONSCLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
TRST = Test Reset
ENABLE = Program
12345678910111213141516171819202122232425
GNDTDI
I/O8I/O9
I/O10I/O11I/O12I/O13I/O14I/O15
I0/CLK0VCCGND
I1/CLK1I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23TMSTCKGND
A1A3A5A7A9
A11A13A15
B15B13B11B9B7B5B3B1
B7B6B5B4B3B2B1B0
C0C1C2C3C4C5C6C7
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GN
DG
ND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31 I2
VC
CG
ND
GN
DV
CC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GN
DG
ND
B14
B12
B10 B8
B6
B4
B2
B0
C0
C2
C4
C6
C8
C10
C12
C14
D7
D6
D5
D4
D3
D2
D1
D0
E0
E1
E2
E3
E4
E5
E6
E7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GN
DG
ND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VC
CG
ND
GN
DV
CC
I5 I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GN
DG
ND
A14
A12
A10
A8
A6
A4
A2
A0
D0
D2
D4
D6
D8
D10
D12
D14
A7
A6
A5
A4
A3
A2
A1
A0
H0
H1
H2
H3
H4
H5
H6
H7
75747372717069686766656463626160595857565554535251
GNDTDOTRSTI/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O48I4/CLK3GNDVCCI3/CLK2I/O47I/O46I/O45I/O44I/O43I/O42I/O41I/O40ENABLEGND
D1D3D5D7D9D11D13D15
C15C13C11C9C7C5C3C1
G7G6G5G4G3G2G1G0
F0F1F2F3F4F5F6F7
M4A3-64/64
M4A3-128/64M4A5-128/64
17466G-032a
I/O Cell
PAL Block
C 7
ispMACH 4A Family 47
100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64)
Bottom View100-Ball caBGA
10 9 8 7 6 5 4 3 2 1
A GND I/O63H7
I/O60H4
I/O57H1
GND GND I/O1A1
I/O4A4
I/O7A7
GND A
B TRST GND I/O61H5
I5 VCC I/O0A0
I/O6A6
GND TDI I/O15B7
B
CI/O53G5
TDOI/O62
H6I/O58
H2I/O56
H0I/O2A2
GNDI/O14
B6I/O13
B5I/O12
B4C
DI/O50G2
I/O55G7
GND I/O59H3
I/O3A3
I/O5A5
I/O11B3
I/O10B2
CLK0/I0
CLK3/I4
I/O9B1
D
EI/O49G1
I/O51G3
I/O54G6
VCC I/O16C0
I/O20C4
I/O8B0
VCC GND E
F GND VCC I/O40F0
I/O52G4
I/O48G0
VCC I/O22C6
I/O19C3
I/O17C1
CLK1/I1 F
GI/O41
F1CLK2/I3 I/O42
F2I/O43
F3I/O37
E5I/O35
E3I/O27
D3GND I/O23
C7I/O18
C2G
HI/O44
F4I/O45
F5I/O46
F6GND I/O34
E2I/O24
D0I/O26
D2I/O30
D6TCK I/O21
C5H
JI/O47
F7ENABLE GND I/O38
E6I/O32
E0VCC I2 I/O29
D5GND TMS J
K GND I/O39E7
I/O36E4
I/O33E1
GND GND I/O25D1
I/O28D4
I/O31D7
GND K
10 9 8 7 6 5 4 3 2 1
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE
============
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgram
C 7
17466G-100cabga
48 ispMACH 4A Family
144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96)
Top View144-Pin TQFP
PIN DESIGNATIONSCLK = Clock
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
17466G-033
123456789101112131415161718192021222324252627282930313233343536
GNDTDI
I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
I2I3
VCCGND
I4I/O8I/O9
I/O10I/O11I/O12I/O13I/O14I/O15GNDVCC
I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23TMSTCKGND
D7D6D5D4D3D2D1D0
C7C6C5C4C3C2C1C0
E7E6E5E4E3E2E1E0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
GN
DI/O
24I/O
25I/O
26I/O
27I/O
28I/O
29I/O
30I/O
31 I5 I6 I7C
LK1
GN
DV
CC
CLK
2 I8 I9I/O
32I/O
33I/O
34I/O
35I/O
36I/O
37I/O
38I/O
39V
CC
GN
DI/O
40I/O
41I/O
42I/O
43I/O
44I/O
45I/O
46I/O
47
F7
F6
F5
F4
F3
F2
F1
F0
G0
G1
G2
G3
G4
G5
G6
G7
H0
H1
H2
H3
H4
H5
H6
H7
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
I/O89
I/O88
GN
DV
CC
I/O87
I/O86
I/O85
I/O84
I/O83
I/O82
I/O81
I/O80
I1 I0 CLK
0G
ND
VC
CC
LK3
I15
I14
I13
I/O79
I/O78
I/O77
I/O76
I/O75
I/O74
I/O73
I/O72
GN
D
B7
B6
B5
B4
B3
B2
B1
B0
A7
A6
A5
A4
A3
A2
A1
A0
L0 L1 L2 L3 L4 L5 L6 L7
108107106105104103102101100999897969594939291908988878685848382818079787776757473
GNDTDONCI/O71I/O70I/O69I/O68I/O67I/O66I/O65I/O64I12VCCGNDI11I10I/O63I/O62I/O61I/O60I/O59I/O58I/O57I/O56GNDVCCI/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O48NCGND
K0K1K2K3K4K5K6K7
J0J1J2J3J4J5J6J7
I0I1I2I3I4I5I6I7
I/O Cell
PAL Block
C 7
ispMACH 4A Family 49
144-BALL FPBGA CONNECTION DIAGRAM (M4A3-192/96)
Bottom View144-Ball fpBGA
12 11 10 9 8 7 6 5 4 3 2 1
A GND I/O72L7
I/O76L3
I13 GBCLK3 I0 I/O82 A2
I/O86 A6
I/O88 B0
I/O93B5
I/O95 B7
GND A
B GND I/O73L6
I/O77L2
I/O79L0
VCC I1 I/O83 A3
I/O87A7
I/O90B2
I/O94 B6
I/O0D7
TDI B
C GND TDO I/O74 L5
I14 GND I/O80A0
I/O84A4
GND I/O92 B4
I/O1 D6
I/O4 D3
I/O3D4
C
D I/O67 K4
I/O69K2
I/O71K0
I/O75L4
GBCLK0 I/O81A1
VCC I/O91 B3
I/O2D5
I2 I/O6D1
I/O7 D0
D
E I12 I/O64 K7
I/O66 K5
I/O70 K1
I/O78 L1
I/O85A5
I/O89 B1
I/O5D2
I/O8 C7
I4 GND VCC E
F I10 I11 GND I/065 K6
I/O68K3
I15 I3 GND I/O12C3
I/O11 C4
I/O10C5
I/O9C6
F
G I/O60 J3
I/O61J2
I/O62J1
I/O63J0
VCC GND I7 I/O20E3
I/O17E6
I/O15C0
I/O14C1
I/O13C2
G
H I/O56J7
I/O57J6
I/O58J5
I/O59J4
I/O53I2
I/O41 H1
I/O37 G5
I/O30F1
I/O22E1
I/O18 E5
I/O16E7
VCC H
J I/O55I0
I/O54 I1
VCC I/O50 I5
I/O43H3
VCC I/O33 G1
GBCLK2 I/O27F4
I/O23E0
I/O21E2
I/O19E4
J
K I/O51 I4
I/O52 I3
I/O49I6
I/O44H4
GND I/O36G4
I/O32G0
VCC I6 I/O26F5
TCK TMS K
L GND I/O48I7
I/O46H6
I/O42H2
I/O39G7
I/O35G3
I9 GND I/O31F0
I/O29F2
I/O25F6
GND L
M GND I/O47H7
I/O45H5
I/O40H0
I/O38G6
I/O34G2
I8 GBCLK1 I5 I/O28F3
I/O24F7
GND M
12 11 10 9 8 7 6 5 4 3 2 1
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
m4a3.192.96_144bga
50 ispMACH 4A Family
208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 ANDM4A3-256/160)
Top View208-Pin PQFP
C7C6C5C4C3C2C1C0
D7D6D5D4D3D2D1D0
E0E1E2E3E4E5E6E7
F0F1F2F3F4F5F6F7
GNDTDI
I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23VCCGNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31
I2I3
GNDVCCVCCGNDGNDVCCVCCGND
I4I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39GNDVCC
I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47TMSTCKGND
GND
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
GND
VCC
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63 I5 I6
CLK
1VC
CGND
GND
VCC
VCC
GND
GND
VCC
CLK
2 I7 I8I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
VCC
GND
I/O72
I/O73
I/O74
I/O75
I/O76
I/O77
I/O78
I/O79
GND
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152
G7
G6
G5
G4
G3
G2
G1
G0
H7
H6
H5
H4
H3
H2
H1
H0
I0 I1 I2 I3 I4 I5 I6 I7 J0 J1 J2 J3 J4 J5 J6 J7
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
101
102
103
104
N7N6N5N4N3N2N1N0
M7M6M5M4M3M2M1M0
L0L1L2L3L4L5L6L7
K0K1K2K3K4K5K6K7
B7 B6 B5 B4 B3 B2 B1 B0 A7
A6
A5
A4
A3
A2
A1
A0 P0 P1 P2 P3 P4 P5 P6 P7 O0
O1
O2
O3
O4
O5
O6
O7
GND
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I1 I0 CLK
0VC
CGND
GND
VCC
VCC
GND
GND
VCC
CLK
3I13
I12
I/O12
7I/O12
6I/O12
5I/O12
4I/O12
3I/O12
2I/O12
1I/O12
0VC
CGND
I/O11
9I/O11
8I/O11
7I/O11
6I/O11
5I/O11
4I/O11
3I/O11
2GND
GNDTDOTRSTI/O111I/O110I/O109I/O108I/O107I/O106I/O105I/O104VCCGNDI/O103I/O102I/O101I/O100I/O99I/O98I/O97I/O96I11GNDVCCVCCGNDGNDVCCVCCGNDI10I9I/O95I/O94I/O93I/O92I/O91I/O90I/O89I/O88GNDVCCI/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O80ENABLEGND
156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
RECOMMEND TO TIE TO VCC
M4A(3, 5)-256/128
RECOMMEND TO TIE TO GND
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE
============
I/O CellPAL Block
ClockGroundInput Input/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgram
C 7
M4A3-256/160
GNDTDI
I/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27VCCGNDI/O28I/O29I/O30I/O31I/O32I/O33I/O34I/O35I/O36I/O37GNDVCC
I/O38I/O39I/O40I/O41I/O42GNDI/O43I/O44I/O45I/O46I/O47I/O48I/O49I/O50I/O51GNDVCC
I/O52I/O53I/O54I/O55I/O56I/O57I/O58I/O59TMSTCKGND
C15C14C13C12C11C10C9C8
C7C6C5C4C3C2C1C0
D14D12
D6D4E0E2E6
E10F0F1F2F3F4F5F6F7
F8F9
F10F11F12F13F14F15
GNDTDONCI/O139I/O138I/O137I/O136I/O135I/O134I/O133I/O132VCCGNDI/O131I/O130I/O129I/O128I/O127I/O126I/O125I/O124I/O123GNDI/O122I/O121I/O120I/O119I/O118VCCGNDI/O117I/O116I/O115I/O114I/O113I/O112I/O111I/O110I/O109I/O108GNDVCCI/O107I/O106I/O105I/O104I/O103I/O102I/O101I/O100NCGND
N15N14N13N12N11N10N9N8
N7N6N5N4N3N2N1N0M10
M6M2M0L4L6
L12L14K0K1K2K3K4K5K6K7
K8K9K10K11K12K13K14K15
GND
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
GND
VCC
I/O68
I/O69
I/O70
I/O71
I/O72
I/O73
I/O74
I/O75
I/O76
I/O77
CLK
1VC
CGND
I/O78
I/O79
I/O80
I/O81
GND
VCC
CLK
2I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
I/O88
I/O89
I/O90
I/O91
VCC
GND
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
I/O99
GND
G15
G14
G13
G12
G11
G10 G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
H14
H12 H6
H4 I4 I6 I12
I14 J0 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
J11
J12
J13
J14
J15
GND
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
CLK
0VC
CGND
I/O1
I/O0
I/O15
9I/O15
8GND
VCC
CLK
3I/O15
7I/O15
6I/O15
5I/O15
4I/O15
3I/O15
2I/O15
1I/O15
0I/O14
9I/O14
8VC
CGND
I/O14
7I/O14
6I/O14
5I/O14
4I/O14
3I/O14
2I/O14
1I/O14
0GND
B15
B14
B13
B12
B11
B10
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A14
A12
A6
A4
P4 P6 P12
P14
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
17466G-044
ispMACH 4A Family 51
208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160)
Top View208-Pin PQFP
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
101
102
103
104
156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
M4A3-512/160
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O CellPAL Block
ClockGroundInput Input/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
GNDTDONCI/O137I/O136I/O135I/O134I/O133I/O132I/O131I/O130VCCGNDI/O129I/O128I/O127I/O126I/O125I/O124I/O123I/O122I/O121GNDI/O120I/O119I/O118I/O117I/O116VCCGNDI/O115I/O114I/O113I/O112I/O111I/O110I/O109I/O108I/O107I/O106GNDVCCI/O105I/O104I/O103I/O102I/O101I/O100I/O99I/O98NCGND
GN
DI/O
17I/O
16I/O
15I/O
14I/O
13I/O
12I/O
11I/O
10G
ND
VCC
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CLK
0VC
CG
ND
I/O15
9I/O
158
I/O15
7I/O
156
GN
DVC
CC
LK3
I/O15
5I/O
154
I/O15
3I/O
152
I/O15
1I/O
150
I/O14
9I/O
148
I/O14
7I/O
146
VCC
GN
DI/O
145
I/O14
4I/O
143
I/O14
2I/O
141
I/O14
0I/O
139
I/O13
8G
ND
GN
DI/O
58I/O
59I/O
60I/O
61I/O
62I/O
63I/O
64I/O
65G
ND
VCC
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
I/O73
I/O74
I/O75
CLK
1VC
CG
ND
I/O76
I/O77
I/O78
I/O79
GN
DVC
CC
LK2
I/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
I/O88
I/O89
VCC
GN
DI/O
90I/O
91I/O
92I/O
93I/O
94I/O
95I/O
96I/O
97G
ND
GNDTDI
I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25VCCGNDI/O26I/O27I/O28I/O29I/O30I/O31I/O32I/O33I/O34I/O35GNDVCC
I/O36I/O37I/O38I/O39I/O40GNDI/O41I/O42I/O43I/O44I/O45I/O46I/O47I/O48I/O49GNDVCC
I/O50I/O51I/O52I/O53I/O54I/O55I/O56I/O57TMSTCKGND
C7C6C5C4C3C2C1C0
F7F6F5F4F3F2F1F0E7E5
E2E0H0H2H3
H5G0G1G2G3G4G5G6G7
J0J1J2J3J4J5J6J7
GNDTDI
I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25VCCGNDI/O26I/O27I/O28I/O29I/O30I/O31I/O32I/O33I/O34I/O35GNDVCC
I/O36I/O37I/O38I/O39I/O40GNDI/O41I/O42I/O43I/O44I/O45I/O46I/O47I/O48I/O49GNDVCC
I/O50I/O51I/O52I/O53I/O54I/O55I/O56I/O57TMSTCKGND
GN
DI/O
58I/O
59I/O
60I/O
61I/O
62I/O
63I/O
64I/O
65G
ND
VCC
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
I/O73
I/O74
I/O75
CLK
1VC
CG
ND
I/O76
I/O77
I/O78
I/O79
GN
DVC
CC
LK2
I/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
I/O88
I/O89
VCC
GN
DI/O
90I/O
91I/O
92I/O
93I/O
94I/O
95I/O
96I/O
97G
ND
K7 K6 K5 K4 K3 K2 K1 K0 I7 I6 I5 I4 I3 I2 I1 I0 L7 L6 L4 L1 M1
M4
M6
M7
P0 P1 P2 P3 P4 P5 P6 P7 N0
N1
N2
N3
N4
N5
N6
N7
B7 B6 B5 B4 B3 B2 B1 B0 D7
D6
D5
D4
D3
D2
D1
D0 A7 A6 A4 A1
HX1
HX4
HX6
HX7 EX
0EX
1EX
2EX
3EX
4EX
5EX
6EX
7
GX0
GX1
GX2
GX3
GX4
GX5
GX6
GX7
GN
DI/O
17I/O
16I/O
15I/O
14I/O
13I/O
12I/O
11I/O
10G
ND
VCC
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CLK
0VC
CG
ND
I/O15
9I/O
158
I/O15
7I/O
156
GN
DVC
CC
LK3
I/O15
5I/O
154
I/O15
3I/O
152
I/O15
1I/O
150
I/O14
9I/O
148
I/O14
7I/O
146
VCC
GN
DI/O
145
I/O14
4I/O
143
I/O14
2I/O
141
I/O14
0I/O
139
I/O13
8G
ND
M4A3-384/160
FX7FX6FX5FX4FX3FX2FX1FX0
CX7CX6CX5CX4CX3CX2CX1CX0DX5
DX3DX2DX0AX0AX2
AX5AX7BX0BX1BX2B3XBX4BX5BX6BX7
O0O1O2O3O4O5O6O7
GNDTDONCI/O137I/O136I/O135I/O134I/O133I/O132I/O131I/O130VCCGNDI/O129I/O128I/O127I/O126I/O125I/O124I/O123I/O122I/O121GNDI/O120I/O119I/O118I/O117I/O116VCCGNDI/O115I/O114I/O113I/O112I/O111I/O110I/O109I/O108I/O107I/O106GNDVCCI/O105I/O104I/O103I/O102I/O101I/O100I/O99I/O98NCGND
F7F6F5F4F3F2F1F0
G7G6G5G4G3G2G1G0E7E5
E2E0L0L2L3
L5J0J1J2J3J4J5J6J7
K0K1K2K3K4K5K6K7
O7
O6
O5
O4
O3
O2
O1
O0
N7
N6
N5
N4
N3
N2
N1
N0 P7 P6 P4 P1 AX1
AX4
AX6
AX7
CX0
CX1
CX2
CX3
CX4
CX5
CX6
CX7 BX
0BX
1BX
2BX
3BX
4BX
5BX
6BX
7
KX7KX6KX5KX4KX3KX2KX1KX0
JX7JX6JX5JX4JX3JX2JX1JX0LX5
LX3LX2LX0EX0EX2
EX5EX7GX0GX1GX2GX3GX4GX5GX6GX7
FX0FX1FX2FX3FX4FX5FX6FX7
B7 B6 B5 B4 B3 B2 B1 B0 C7
C6
C5
C4
C3
C2
C1
C0
A7 A6 A4 A1 PX1
PX4
PX6
PX7
NX0
NX1
NX2
NX3
NX4
NX5
NX6
NX7
OX0
OX1
OX2
OX3
OX4
OX5
OX6
OX7
17466Ga-044
52 ispMACH 4A Family
256-BALL BGA CONNECTION DIAGRAM (M4A3-256/128)
Bottom View256-Ball BGA
GND
GND
I/O116O3
I/O120P7
I/O123P4
GND
I12
GND
N/C
GND
N/C
N/C
GND
I1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
N/C
I/O113O6
N/C
I/O117O2
I/O119O0
I/O122P5
I/O125P2
I/O127P0
N/C
CLK3
CLK0
N/C
I/O0A0
I/O1A1
GND
N/C
VCC
I/O112O7
I/O114O5
I/O118O1
I/O121P6
I/O126P1
N/C
N/C
N/C
N/C
I/O2A2
I/O6A6
I/O108N4
I/O109N5
TRST
VCC
TDI
I/O115O4
VCC
I/O124P3
I13
N/C
N/C
I0
I/O3A3
VCC
I/O105N1
I/O106N2
I/O111N7
VCC
GND
I/O103M7
I/O107N3
I/O110N6
I/O100M4
I/O102M6
I/O104N0
VCC
I/O96M0
I/O98M2
I/O101M5
N/C
GND
N/C
I/O97M1
I/O99M3
GND
I11
N/C
N/C
GND
N/C
I10
I9
GND
N/C
I/O94L1
I/O92L3
GND
I/O82K5
VCC
I/O79J7
I/O77J5
I/O73J1
I/O70I6
I/O66I2
N/C
N/C
N/C
N/C
I/O61H2
I/O57H6
GND
20 19 18 17 16 15 14 13 12 11 10 9
I/O95L0
I/O93L2
I/O90L5
N/C
8
I/O91L4
I/O89L6
I/O86K1
VCC
7
GND
I/O88L7
I/O84K3
I/O81K6
6
I/O87K0
I/O85K2
I/O80K7
VCC
5
N/C
I/O83K4
ENABLE
VCC
TDO
I/O76J4
VCC
I/O67I3
I7
N/C
N/C
I6
I/O60H3
VCC
4 3
GND
N/C
I/O78J6
I/O75J3
I/O72J0
I/O69I5
I/O65I1
I/O64I0
N/C
CLK2
CLK1
I/O63H0
I/O59H4
I/O58H5
2 1
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
GND
I/O74J2
I/O71I7
I/O68I4
GND
I8
GND
N/C
N/C
GND
I/O62H1
GND
I5
GND
I/O4A4
I/O7A7
I/O5A5
I/O8B0
I/O11B3
I/O9B1
I/O12B4
I/O15B7
N/C
TCK
VCC VCC I/O18C5 VCC I/O24
D7I/O29
D2 I2 N/C I/O35E3
I/O54G1
I/O50G5
I/O48G7N/C VCC N/C VCC
I/O51G4
TMS
VCC
I/O56H7
I/O55G0
I/O53G2
GND
N/C
N/C
I/O10B2
GND
GND
I/O13B5
I/O14B6
GND
VCC
N/C
GND
I/O16C7
N/C
N/C
I/O17C6
I/O19C4
I/O20C3
I/O21C2
I/O22C1
GND
I/O23C0
I/O25D6
I/O26D5
I/O27D4
I/O28D3
I/O30D1
I/O31D0
N/C
GND
I3
N/C
GND
N/C
I4
GND
I/O33E1
N/C
GND
VCC
N/C
GND
I/O37E5
I/O34E2
I/O32E0
I/O41F1
I/O38E6
I/O36E4
I/O43F3
I/O39E7
GND
I/O46F6
I/O42F2
I/O40F0
I/O47F7
I/O45F5
I/O44F4
I/O52G3
I/O49G6
N/C
N/C
GND
GND
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE
============
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgram
C 7
17466G-045
ispMACH 4A Family 53
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192)
Bottom View256-Ball fpBGA
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A I/O167N15
I/O181O13
I/O180O12
I/O177O9
I/O174O6
I/O172O4
I/O191P14
I/O186P4
I/O1A2
I/O3A6
GCLK0 I/O9B1
I/O13B5
I/O15B7
I/O18B10
I/O20B12 A
B I/O165N13
I/O166N14
I/O182O14
I/O179O11
I/O175O7
I/O173O5
I/O168O0
I/O187P6
I/O0A0
I/O5A10
I/O7A14
I/O10B2
I/O16B8
I/O19B11
I/O21B13
NC B
C I/O163N11
I/O164N12
NC I/O183O15
I/O178O10
I/O170O2
I/O171O3
I/O189P10
I/O184P0
I/O6A12
I/O12B4
I/O14B6
I/O23B15
I/O22B14
TDI I/O39C15 C
D I/O158N6
I/O159N7
TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O17B9
I/O38C14
I/O37C13 D
E I/O156N4
NC I/O162N10
VCC I/O160N8
I/O161N9
I/O190P12
GCLK3 I/O188P8
I/O2A4
I/O8B0
NC GND I/O36C12
I/O35C11
I/O31C7 E
F I/O152N0
I/O157N5
I/O155N3
GND I/O154N2
I/O153N1
I/O176O8
I/O169O1
I/O185P2
I/O4A8
I/O11B3
I/O34C10
VCC I/O32C8
I/O30C6
I/O29C5 F
G I/O147M6
I/O150M12
I/O149M10
VCC I/O148M8
I/O151M14
VCC GND GND VCC I/O33C9
I/O28C4
GND I/O26C2
I/O25C1
I/O47D14 G
H I/O144M0
I/O146M4
I/145OM2
GND I/O136L0
I/O137L2
GND VCC VCC GND I/O27C3
I/O24C0
VCC I/O44D8
I/O43D6
I/O42D4 H
J I/O138L4
I/O139L6
I/O140L8
GND I/O142L12
I/O141L10
GND VCC VCC GND I/O46D12
I/O45D10
GND I/O49E2
I/O48E0
I/O50E4 J
K I/O143L14
I/O120K0
I/O121K1
VCC I/O123K3
I/O122K2
VCC GND GND VCC I/O41D2
I/O40D0
VCC I/O55E14
I/O54E12
I/O56F0 K
L I/O124K4
I/O125K5
I/O127K7
GND I/O130K10
I/O126K6
I/O98I4
I/O91H6
I/O75G3
I/O77G5
I/O52E8
I/O51E6
GND I/O59F3
I/O60F4
I/O57F1 L
M I/O128K8
I/O129K9
I/O131K11
GND I/O107J3
I/O105J1
I/O100I8
I/O90H4
I/O74G2
I/O80G8
I/O83G11
I/O53E10
VCC I/O68F12
I/O63F7
I/O58F2 M
N I/O132K12
I/O133K13
I/O135K15
VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O64F8
I/O61F5 N
P I/O134K14
I/O117J13
I/O118J14
I/O119J15
I/O108J4
I/O106J2
I/O101I10
I/O89H2
I/O93H10
I/O94H12
I/O79G7
I/O84G12
I/O87G15
TMS I/O65F9
I/O62F6 P
R I/O116J12
I/O115J11
I/O112J8
I/O111J7
I/O104J0
I/O102I12
I/O99I6
I/O96I0
I/O92H8
I/O72G0
I/O76G4
I/O81G9
I/O85G13
I/O71F15
I/O67F11
I/O66F10 R
T I/O114J10
I/O113J9
I/O110J6
I/O109J5
I/O103I14
GCLK2 I/O97I2
I/O88H0
GCLK1 I/O95H14
I/O73G1
I/O78G6
I/O82G10
I/O86G14
I/O70F14
I/O69F13 T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
17466G-047
54 ispMACH 4A Family
256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192)
Bottom View256-Ball BGA
GND
GND
I/O0GX6
I/O1EX7
I/O2EX0
GND
I/O3HX6
GND
I/O4HX0
GND
I/O5A2
I/O6A4
GND
I/O7D2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
I/O11FX7
I/O12GX7
I/O13GX5
I/O14GX3
I/O15GX0
I/O16EX1
I/O17EX4
I/O18HX5
I/O19HX1
CLK3
CLK0
I/O20A3
I/O21A7
I/O22D3
GND
I/O28FX5
VCC
I/O29GX4
I/O30GX1
I/O31EX6
I/O32EX5
I/O33EX2
I/O34HX4
I/O35HX2
I/O36A0
I/O37A5
I/O38D0
I/O39D4
I/O44FX6
I/O45FX3
I/O46FX4
VCC
TDI
I/O47GX2
VCC
I/O48EX3
I/O49HX7
I/O50HX3
I/O51A1
I/O52A6
I/O53D1
VCC
I/O58CX6
I/O59CX7
I/O60FX2
VCC
GND
I/O64CX5
I/O65FX1
I/O66FX0
I/O70CX2
I/O71CX3
I/O72CX4
VCC
I/O76DX6
I/O77DX7
I/O78CX0
I/O79CX1
GND
I/O84DX5
I/O85DX4
I/O86DX3
GND
I/O90DX2
I/O91DX1
I/O92DX0
GND
I/O96AX0
I/O97AX1
I/O98AX2
GND
I/O102AX3
I/O103AX4
I/O104AX7
GND
I/O148O6
VCC
I/O149N4
I/O150N2
I/O151N0
I/O152P4
I/O153P1
I/O154M5
I/O155M1
I/O156L4
I/O157L5
I/O158I0
I/O159I4
GND
20 19 18 17 16 15 14 13 12 11 10 9
I/O108AX5
I/O109AX6
I/O110BX2
I/O111B3X
8
I/O116BX0
I/O117BX1
I/O118BX5
VCC
7
GND
I/O122BX4
I/O123O0
I/O124O2
6
I/O128BX7
I/O129BX6
I/O130O1
VCC
5
I/O134O3
I/O135O4
I/O136O5
VCC
TDO
I/O137N1
VCC
I/O138P2
I/O139M6
I/O140M0
I/O141L3
I/O142L6
I/O143I5
VCC
4 3
GND
I/O164O7
I/O165N7
I/O166N5
I/O167N3
I/O168P5
I/O169P3
I/O170P0
I/O171M4
CLK2
CLK1
I/O172L0
I/O173L7
I/O174I1
2 1
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
GND
I/O181N6
I/O182P7
I/O183P6
GND
I/O184M7
GND
I/O185M3
I/O186M2
GND
I/O187L1
GND
I/O188L2
GND
I/O8B3
I/O9B4
I/O23D5
I/O24B0
I/O25B1
I/O40D6
I/O41B7
I/O42B6
I/O54D7
TCK
VCC VCC I/O67C0 VCC I/O80
F0I/O87
E5I/O93
E2I/O99
H2I/O105
H5
I/O160K0
I/O161K4
I/O162K7
I/O112G0 VCC I/O125
J1 VCC
I/O144K5
TMS
VCC
I/O175I3
I/O176K1
I/O177K2
GND
I/O189I2
I/O190I6
I/O10B5
GND
GND
I/O26B2
I/O27C7
GND
VCC
I/O43C6
GND
I/O55C5
I/O56C3
I/O57C4
I/O61C2
I/O62F7
I/O63F6
I/O68C1
I/O69F5
GND
I/O73F4
I/O74F3
I/O75F2
I/O81F1
I/O82E7
I/O83E6
I/O88E4
I/O89E3
GND
I/O94E1
I/O95E0
GND
I/O100H1
I/O101H0
GND
I/O106H4
I/O107H3
GND
VCC
I/O163J6
GND
I/O113G1
I/O114H7
I/O115H6
I/O119G4
I/O120G3
I/O121G2
I/O126J0
I/O127G5
GND
I/O131J2
I/O132G7
I/O133G6
I/O145J5
I/O146J4
I/O147J3
I/O178K3
I/O179J7
I/O180K6
I/O191I7
GND
GND
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
17466G-046
ispMACH 4A Family 55
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128)
Bottom View256-Ball fpBGA
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A TRST I/O117O5
I/O116O4
I/O113O1
I/O126P6
I/O124P4
I12 NC NC NC CLK0 I/O1A1
I/O5A5
I/O7A7
I/O10B2
I/O12B4
A
B I/O110N6
I/O111N7
I/O118O6
I/O115O3
I/O127P7
I/O125P5
I/O120P0
NC NC NC I1 I/O2A2
I/O8B0
I/O11B3
I/O13B5
NC B
C I/O108N4
I/O109N5
NC I/O119O7
I/O114O2
I/O122P2
I/O123P3
NC NC I0 I/O4A4
I/O6A6
I/O14B6
TDI I/O23C7
C
D NC I/O104N0
TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9B1
I/O22C6
I/O21C5
D
E I/O102M6
NC I/O107N3
VCC I/O105N1
I/O106N2
I13 CLK3 NC NC I/O0A0
NC GND I/O20C4
I/O19C3
I/O31D7
E
F I/O98M2
I/O103M7
I/O101M5
GND I/O100M4
I/O99M3
I/O112O0
I/O121P1
NC NC I/O3A3
I/O18C2
VCC I/O16C0
I/O30D6
I/O29D5
F
G NC I/O96M0
I11 VCC NC I/O97M1
VCC GND GND VCC I/O17C1
I/O28D4
GND I/O26D2
I/O25D1
I2 G
H I/O88L0
I10 I9 GND I/O89L1
I/O90L2
GND VCC VCC GND I/O27D3
I/O24D0
VCC NC NC NC H
J I/O91L3
I/O92L4
I/O93L5
GND I/O95L7
I/O94L6
GND VCC VCC GND I3 NC GND NC NC NC J
K NC NC NC VCC NC NC VCC GND GND VCC NC NC VCC I4 NC I/O32E0
K
L NC NC I/O80K0
GND I/O83K3
NC NC NC I/O59H3
I/O61H5
NC NC GND I/O35E3
I/O36E4
I/O33E1
L
M I/O81K1
I/O82K2
I/O84K4
GND I/O67I3
I/O65I1
NC NC I/O58H2
I/O48G0
I/O51G3
NC VCC I/O44F4
I/O39E7
I/O34E2
M
N I/O85K5
I/O86K6
ENABLE VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O40F0
I/O37E5
N
P I/O87K7
I/O77J5
I/O78J6
I/O79J7
I/O68I4
I/O66I2
NC NC NC I6 I/O63H7
I/O52G4
I/O55G7
TMS I/O41F1
I/O38E6
P
R I/O76J4
I/O75J3
I/O72J0
I/O71I7
I/O64I0
I7 NC NC NC I/O56H0
I/O60H4
I/O49G1
I/O53G5
I/O47F7
I/O43F3
I/O42F2
R
T I/O74J2
I/O73J1
I/O70I6
I/O69I5
I8 CLK2 NC NC CLK1 I5 I/O57H1
I/O62H6
I/O50G2
I/O54G6
I/O46F6
I/O45F5
T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE
============
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgram
C 7
I/O15B7
m4a3.256.128_256bga
56 ispMACH 4A Family
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192)
Bottom View256-Ball fpBGA
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A I/O175FX7
I/O181GX5
I/O180GX4
I/O177GX1
I/O166EX6
I/O164EX4
I/O191HX7
I/O186HX2
I/O1 A1
I/O3 A3
CLK0 I/O25D1
I/O29D5
I/O31D7
I/O10B2
I/O12B4 A
B I/O173FX5
I/O174FX6
I/O182GX6
I/O179GX3
I/O167EX7
I/O165EX5
I/O160EX0
I/O187HX3
I/O0A0
I/O5A5
I/O7A7
I/O26D2
I/O8B0
I/O11B3
I/O13B5
N/C B
C I/O171FX3
I/O172FX4
N/C I/O183GX7
I/O178GX2
I/O162EX2
I/O163EX3
I/O189HX5
I/O184HX0
I/O6A6
I/O28D4
I/O30D6
I/O15B7
I/O14B6
TDI I/O23C7 C
D I/O150CX6
I/O151CX7
TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9B1
I/O22C6
I/O21C5 D
E I/O148CX4
N/C I/O170FX2
VCC I/O168FX0
169FX1
I/O190HX6
CLK3 I/O188HX4
I/O2A2
I/O24D0
N/C GND I/O20C4
I/O19C3
I/O47F7 E
F I/O144CX0
I/O149CX5
I/O147CX3
GND I/O146CX2
I/O145CX1
I/O176GX0
I/O161EX1
I/O185HX1
I/O4 A4
I/O27D3
I/O18C2
VCC I/O16C0
I/O46F6
I/O45F5 F
G I/O155DX3
I/O158DX6
I/O157DX5
VCC I/O156DX4
I/O159DX7
VCC GND GND VCC I/O17C1
I/O44F4
GND I/O42F2
I/O41F1
I/O39E7 G
H I/O152DX0
I/O154DX2
I/O153DX1
GND I/O128AX0
I/O129AX1
GND VCC VCC GND I/O43F3
I/O40F0
VCC I/O36E4
I/O35E3
I/O34E2 H
J I/O130AX2
I/O131AX3
I/O132AX4
GND I/O134AX6
I/O133AX5
GND VCC VCC GND I/O38E6
I/O37E5
GND I/O57H1
I/O56H0
I/O58H2 J
K I/O135AX7
I/O136BX0
I/O137BX1
VCC I/O139BX3
I/O138BX2
VCC GND GND VCC I/O33E1
I/O32E0
VCC I/O63H7
I/O62H6
I/O48G0 K
L I/O140BX4
I/O141BX5
I/O143BX7
GND I/O114O2
I/O142BX6
I/O98M2
I/O91L3
I/O67I3
I/O69I5
I/O60H4
I/O59H3
GND I/O51G3
I/O52G4
I/O49G1 L
M I/O112O0
I/O113O1
I/O115O3
GND I/O123P3
I/O121P1
I/O100M4
I/O90L2
I/O66I2
I/O80K0
I/O83K3
I/O61H5
VCC I/O76J4
I/O55G7
I/O50G2 M
N I/O116O4
I/O117O5
I/O119O7
VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O72J0
I/O53G5 N
P I/O118O6
I/O109N5
I/O110N6
I/O111N7
I/O124P4
I/O122P2
I/O101M5
I/O89L1
I/O93L5
I/O94L6
I/O71I7
I/O84K4
I/O87K7
TMS I/O73J1
I/O54G6 P
R I/O108N4
I/O107N3
I/O104N0
I/O127P7
I/O120P0
I/O102M6
I/O99M3
I/O96M0
I/O92L4
I/O64I0
I/O68I4
I/O81K1
I/O85K5
I/O79J7
I/O75J3
I/O74J2 R
T I/O106N2
I/O105N1
I/O126P6
I/O125P5
I/O103M7
CLK2 I/O97M1
I/O88L0
CLK1 I/O95L7
I/O65I1
I/O70I6
I/O82K2
I/O86K6
I/O78J6
I/O77J5 T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
m4a3.384.192_256bga
ispMACH 4A Family 57
256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192)
Bottom View256-Ball fpBGA
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A I/O159KX7
I/O181OX5
I/O180OX4
I/O177OX1
I/O174NX6
I/O172NX4
I/O191PX7
I/O186PX2
I/O1A1
I/O3A3
CLK0 I/O17C1
I/O21C5
I/O23C7
I/O10B2
I/O12B4
A
B I/O157KX5
I/O158KX6
I/O182OX6
I/O179OX3
I/O175NX7
I/O173NX5
I/O168NX0
I/O187PX3
I/O0A0
I/O5A5
I/O7A7
I/O18C2
I/O8B0
I/O11B3
I/O13B5
N/C B
C I/O155KX3
I/O156KX4
N/C I/O183OX7
I/O178OX2
I/O170NX2
I/O171NX3
I/O189PX5
I/O184PX0
I/O6A6
I/O20C4
I/O22C6
I/O15B7
I/O14B6
TDI I/O39F7
C
D I/O150JX6
I/O151JX7
TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9B1
I/O38F6
I/O37F5
D
E I/O148JX4
N/C I/O154KX2
VCC I/O152KX0
I/O153KX1
I/O190PX6
CLK3 I/O188PX4
I/O2A2
I/O16C0
N/C GND I/O36F4
I/O35F3
I/O47G7
E
F I/O144JX0
I/O149JX5
I/O147JX3
GND I/O146JX2
I/O145JX1
I/O176OX0
I/O169NX1
I/O185PX1
I/O4A4
I/O19C3
I/O34F2
VCC I/O32F0
I/O46G6
I/O45G5
F
G I/O163LX3
I/O166LX6
I/O165LX5
VCC I/O164LX4
I/O167LX7
VCC GND GND VCC I/O33F1
I/O44G4
GND I/O42G2
I/O41G1
I/O31E7
G
H I/O160LX0
I/O162LX2
I/O161LX1
GND I/O120EX0
I/O121EX1
GND VCC VCC GND I/O43G3
I/O40G0
VCC I/O28E4
I/O27E3
I/O26E2
H
J I/O122EX2
I/O123EX3
I/O124EX4
GND I/O126EX6
I/O125EX5
GND VCC VCC GND I/O30E6
I/O29E5
GND I/O65L1
I/O64L0
I/O66L2
J
K I/O127EX7
I/O136GX0
I/O137GX1
VCC I/O139GX3
I/O138GX2
VCC GND GND VCC I/O25E1
I/O24E0
VCC I/O71L7
I/O70L6
I/O48J0
K
L I/O140GX4
I/O141GX5
I/O143GX7
GND I/O130FX2
I/O142GX6
I/O98AX2
I/O91P3
I/O75N3
I/O77N5
I/O68L4
I/O67L3
GND I/O51J3
I/O52J4
I/O49J1
L
M I/O128 FX0
I/O129FX1
I/O131FX3
GND I/O115CX3
I/O113CX1
I/O100AX4
I/O90P2
I/O74N2
I/O80O0
I/O83O3
I/O69L5
VCC I/O60K4
I/O55J7
I/O50J2
M
N I/O132FX4
I/O133FX5
I/O135FX7
VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O56K0
I/O53J5
N
P I/O134FX6
I/O109BX5
I/O110BX6
I/O111BX7
I/O116CX4
I/O114CX2
I/O101AX5
I/O89P1
I/O93P5
I/O94P6
I/O79N7
I/O84O4
I/O87O7
TMS I/O57K1
I/O54J6
P
R I/O108BX4
I/O107BX3
I/O104BX0
I/O119CX7
I/O112CX0
I/O102AX6
I/O99AX3
I/O96AX0
I/O92P4
I/O72N0
I/O76N4
I/O81O1
I/O85O5
I/O63K7
I/O59K3
I/O58K2
R
T I/O106BX2
I/O105BX1
I/O118CX6
I/O117CX5
I/O103AX7
CLK2 I/O97AX1
I/O88P0
CLK1 I/O95P7
I/O73N1
I/O78N6
I/O82O2
I/O86O6
I/O62K6
I/O61K5
T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O Cell PAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
m4a3.512.192_256bga
58 ispMACH 4A Family
388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256)
Bottom View388-Ball fpBGA
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A GND I/O243OX3
I/O240OX0
I/O241OX1
I/O236NX4
I/O231MX7
I/O228MX4
I/O226MX2
I/O255PX7
I/O251PX3
I/O248PX0
I/O0A0
I/O5A5
I/O6A6
I/O27D3
I/O30D6
I/O17C1
I/O22C6
I/O8B0
I/O10B2
N/C GND A
B N/C GND I/O245OX5
I/O242OX2
I/O238NX6
I/O234NX2
I/O232NX0
I/O229MX5
I/O224MX0
I/O253PX5
I/O249PX1
I/O2A2
CLK0 I/O26D2
I/O29D5
I/O31D7
I/O20C4
I/O9B1
I/O12B4
I/O13B5
GND TDI B
C I/O213KX5
TDO GND I/O247OX7
I/O244OX4
I/O239NX7
I/O235NX3
I/O230MX6
I/O227MX3
CLK3 I/O250PX2
I/O1A1
I/O7A7
I/O25D1
I/O16C0
I/O18C2
I/O23C7
I/O11B3
I/O15B7
GND I/O47F7
I/O44F4 C
D I/O210KX2
I/O212KX4
I/O215KX7
GND I/O246OX6
VCC I/O237NX5
I/O233NX1
VCC I/O254PX6
VCC I/O3A3
I/O24D0
VCC I/O19C3
I/O21C5
VCC I/O14B6
GND I/O46F6
I/O43F3
I/O41F1 D
E I/O207JX7
I/O209KX1
I/O211KX3
I/O214KX6
I/O45F5
I/O42F2
I/O40F0
I/O54G6 E
F I/O203JX3
I/O205JX5
I/O208KX0
VCC VCC I/O55G7
I/O52G4
I/O50G2 F
G I/O200JX0
I/O202JX2
I/O204JX4
I/O206JX6
VCC VCC N/C I/O225MX1
I/O252PX4
I/O4A4
I/O28D4
N/C VCC VCC I/O53G5
I/O51G3
I/O49G1
I/O39E7 G
H I/O221LX5
I/O222LX6
I/O223LX7
I/O201JX1
VCC N/C GND GND GND GND GND GND N/C VCC I/O48G0
I/O38E6
I/O37E5
I/O36E4 H
J I/O218LX2
I/O219LX3
I/O220LX4
VCC N/C GND GND GND GND GND GND GND GND N/C VCC I/O35E3
I/O34E2
I/O32E0 J
K I/O197IX5
I/O198IX6
I/O199IX7
I/O216LX0
I/O217LX1
GND GND GND GND GND GND GND GND I/O33E1
I/O63H7
I/O62H6
I/O61H5
I/O60H4 K
L I/O192IX0
I/O194IX2
I/O195IX3
I/O196IX4
I/O193IX1
GND GND GND GND GND GND GND GND I/O58H2
VCC I/O59H3
I/O57H1
I/O56H0 L
M I/O184HX0
I/O185HX1
I/O187HX3
VCC I/O186HX2
GND GND GND GND GND GND GND GND I/O69I5
I/O67I3
I/O65I1
I/O66I2
I/O64I0 M
N I/O188HX4
I/O189HX5
I/O191HX7
I/O190HX6
I/O162EX2
GND GND GND GND GND GND GND GND I/O89L1
I/O88L0
I/O71I7
I/O70I6
I/O68I4 N
P I/O160EX0
I/O161EX1
I/O163EX3
VCC N/C GND GND GND GND GND GND GND GND N/C VCC I/O92L4
I/O91L3
I/O90L2 P
R I/O164EX4
I/O165EX5
I/O166EX6
I/O177GX1
VCC N/C GND GND GND GND GND GND N/C VCC I/O74J2
I/O95L7
I/O94L6
I/O93L5 R
T I/O167EX7
I/O176GX0
I/O179GX3
I/O181GX5
VCC VCC N/C I/O152DX0
I/O131AX3
I/O122P2
I/O98M2
N/C VCC VCC I/O78J6
I/O76J4
I/O73J1
I/O72J0 T
U I/O178GX2
I/O180GX4
I/O183GX7
VCC VCC I/O80K0
I/O77J5
I/O75J3 U
V I/O182GX6
N/C I/O169FX1
I/O172FX4
I/O86K6
I/O83K3
I/O81K1
I/O79J7 V
W I/O168FX0
I/O170FX2
I/O173FX5
GND I/O143BX7
VCC I/O150CX6
I/O145CX1
VCC I/O153DX1
I/O123P3
VCC I/O96M0
VCC I/O104N0
I/O111N7
VCC I/O119O7
GND I/O87K7
I/O84K4
I/O82K2 W
Y I/O171FX3
I/O174FX6
GND I/O141BX5
I/O138BX2
I/O136BX0
I/O147CX3
I/O158DX6
I/O156DX4
CLK2 I/O132AX4
I/O121P1
I/O125P5
I/O99M3
I/O101M5
I/O106N2
I/O110N6
I/O115O3
I/O118O6
GND TMS I/O85K5 Y
AA I/O175FX7
GND I/O142BX6
I/O140BX4
I/O151CX7
I/O149CX5
I/O144CX0
I/O157DX5
I/O154DX2
I/O134AX6
I/O130AX2
I/O128AX0
CLK1 I/O127P7
I/O100M4
I/O103M7
I/O108N4
I/O109N5
I/O113O1
I/O116O4
GND TCK AA
AB GND N/C I/O139BX3
I/O137BX1
I/O148CX4
I/O146CX2
I/O159DX7
I/O155DX3
I/O135AX7
I/O133AX5
I/O129AX1
I/O120P0
I/O124P4
I/O126P6
I/O97M1
I/O102M6
I/O105N1
I/O107N3
I/O112O0
I/O114O2
I/O117O5
GND AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN DESIGNATIONS
CLKGNDII/ON/CVCCTDITCKTMSTDO
==========
I/O CellPAL Block
ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data Out
C 7
m4a3.512.256_388bga
ispMACH 4A Family 59
ispMACH 4A PRODUCT ORDERING INFORMATION
ispMACH 4A Devices Commercial and Industrial - 3.3V and 5VLattice programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combina-tion of:
1. Use 5.5ns for new designs.
128
FAMILY TYPEM4A3- = ispMACH 4A Family Low Voltage Advanced
Feature (3.3-V VCC)M4A5- = ispMACH 4A Family Advanced Feature
(5-V VCC)
M4A3- 256 Y C
MACROCELL DENSITY32 = 32 Macrocells 192 = 192 Macrocells64 = 64 Macrocells 256 = 256 Macrocells96 = 96 Macrocells 384 = 384 Macrocells128 = 128 Macrocells 512 = 512 Macrocells
I/Os/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP
/48 = 48 I/Os in 100-pin TQFP /64 = 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA/96 = 96 I/Os in 144-pin TQFP or 144-ball fpBGA
/128 = 128 I/Os in 208-pin PQFP, 256-ball BGA or 256-ball fpBGA/160 = 160 I/Os in 208-pin PQFP/192 = 192 I/Os in 256-ball BGA or 256-ball fpBGA/256 = 256 I/Os in 388-ball fpBGA
OPERATING CONDITIONSC = Commercial (0°C to +70°C)I = Industrial (-40°C to +85°C)
PACKAGE TYPESA = Ball Grid Array (BGA)J = Plastic Leaded Chip Carrier (PLCC)JN = Lead-free Plastic Leaded Chip Carrier
(PLCC)V = Thin Quad Flat Pack (TQFP)VN = Lead-free Thin Quad Flat Pack
(TQFP)Y = Plastic Quad Flat Pack (PQFP)YN = Lead-fee Plastic Quad Flat Pack
(PQFP)FA = Fine-pitch Ball Grid Array (fpBGA)FAN = Lead-free Fine-pitch Ball Grid Array
(fpBGA)CA = Chip-array Ball Grid Array (caBGA)
SPEED-5 = 5.0 ns tPD-55 = 5.5 ns tPD-6 = 6.0 ns tPD-65 = 6.5 ns tPD-7 = 7.5 ns tPD-10 = 10 ns tPD-12 = 12 ns tPD-14 = 14 ns tPD
-7
48 = 48-pin TQFP for M4A3-32/32 or M4A3-64/32M4A5-32/32 or M4A5-64/32
/
*Package obsolete, contact factory.
Conventional Packaging3.3V Commercial Combinations
M4A3-32/32 -5, -7, -10 JC, VC, VC48M4A3-64/32
-55, -7, -10
JC, VC, VC48M4A3-64/64 VCM4A3-96/48 VCM4A3-128/64 YC, VC, CACM4A3-192/96 -6, -7, -10 VC, FACM4A3-256/128 -55, -651, -7, -10 YC, FAC, SACM4A3-256/160
-7, -10YC
M4A3-256/192 FACM4A3-384/160
-65, -10, -12YC
M4A3-384/192 SAC, FACM4A3-512/160
-7, -10, -12YC
M4A3-512/192 FACM4A3-512/256 FAC
3.3V Industrial CombinationsM4A3-32/32
-7, -10, -12
JI, VI, VI48M4A3-64/32 JI, VI, VI48M4A3-64/64 VIM4A3-96/48 VIM4A3-128/64 YI, VI, CAIM4A3-192/96 VI, FAIM4A3-256/128 YI, FAI, SAIM4A3-256/160
-10, -12YI
M4A3-256/192 FAIM4A3-384/160
-10, -12, -14
YIM4A3-384/192 FAIM4A3-512/160 YIM4A3-512/192 FAIM4A3-512/256 FAI
60 ispMACH 4A Family
Most ispMACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4A3-256/128-7YC-10YI
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirmavailability of specific valid combinations and to check on newly released combinations.
5V Industrial CombinationsM4A5-32/32 -7, -10, -12 JI, VI, VI48M4A5-64/32
-7, -10, -12JI, VI, VI48
M4A5-96/48 VIM4A5-128/64 YI, VIM4A5-192/96 -7, -10, -12 VIM4A5-256/128 -10, -12 YI
5V Commercial CombinationsM4A5-32/32 -5, -7, -10, JC, VC, VC48M4A5-64/32
-55, -7, -10JC, VC, VC48
M4A5-96/48 VCM4A5-128/64 YC, VCM4A5-192/96 -6, -7, -10 VCM4A5-256/128 -65, -7, -10 YC
Lead-free Packaging3.3V Commercial Combinations
M4A3-32/32 -5, -7, -10 VNC, VNC48, JNCM4A3-64/32
-55, -7, -10VNC, VNC48, JNC
M4A3-64/64 VNCM4A3-128/64 VNCM4A3-192/96 -6, -7, -10 VNCM4A3-256/128 -55, -7, -10 FANC, YNCM4A3-256/160
-7, -10YNC
M4A3-256/192 FANCM4A3-384/192 -65, -10, -12 FANCM4A3-512/192 -7, -10, -12 FANC
3.3V Industrial CombinationsM4A3-32/32
-7, -10, -12
VNI, VNI48, JNIM4A3-64/32 VNI, VNI48, JNIM4A3-64/64 VNIM4A3-128/64 VNIM4A3-192/96
-10, -12VNI
M4A3-256/128 FANI, YNIM4A3-256/160 YNIM4A3-256/192
-10, -12, -14FANI
M4A3-384/192 FANIM4A3-512/192 FANI
5V Industrial CombinationsM4A5-32/32
-7, -10, -12
VNI, VNI48, JNIM4A5-64/32 VNI, VNI48, JNIM4A5-96/48 VNIM4A5-128/64 VNI, YNIM4A5-192/96 VNIM4A5-256/128 YNI
5V Commercial CombinationsM4A5-32/32 -5, -7, -10 VNC, VNC48, JNCM4A5-64/32
-55, -7, -10VNC, VNC48, JNC
M4A5-96/48 VNCM4A5-128/64 VNC, YNCM4A5-192/96 -6, -7, -10 VNCM4A5-256/128 -65, -7, -10 YNC
ispMACH 4A Family 61
Revision History
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Date Version Change Summary
- K Previous Lattice release.
August 2006 L Updated for lead-free package options.
September 2006 M Revised M4A3-256/160 208-pin PQFP connection diagram.
62 ispMACH 4A Family