isnap2110 reference board_design guide_w

Accelerating IP Storage Networks

TM

February 24, 2005 SBS 2110 DO 08 1.2.0

iSNAP®2110 Reference Board Design Guide

Silverback Systems Confidential

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Silverback Systems Confidential

Copyright © 2002–2005 Silverback Systems. All rights reserved.

This document contains proprietary information of Silverback Systems. No part of the work described herein may be reproduced. Reverse engineering of the hardware or software is prohibited and is protected by patent law.

This material or any portion of it may not be copied in any form or by any means, stored in a retrieval system, adopted or transmitted in any form or by any means (electronic, mechanical, photographic, graphic, optic or otherwise), or translated in any language or computer language without the prior written permission of Silverback Systems.

The information in this document is subject to change without notice. Silverback Systems makes no representation or warranties with respect to the contents herein and shall not be responsible for any loss or damage caused to the user by the direct or indirect use of this information. If you find any problems in the documentation, please report them in writing to Technical Publications at Silverback Systems.

While due care has been taken to deliver accurate documentation, Silverback Systems does not warrant that this document is error-free.

iSNAP is a registered trademark of Silverback Systems.

Linux is a registered trademark of Linus Torvalds. All other products or company names or trademarks mentioned herein are used for identification purposes only, and may be trademarks or registered trademarks of their respective owners.

Silverback Systems is located at 655 Campbell Technology Parkway, Campbell, CA 95008. Telephone: 408.558.1200; Fax: 408.558.1299. For more information about Silverback Systems, visit the Silverback web site at: www.silverbacksystems.com

SBS 2110 DO 08 1.2.02/05

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SILVERBACKRevision History

Date Version Changes

June 04 SBS 2110 DO 08 1.1.0 External Ethernet cables is Category 5e (see Section 1.4, “System Requirements”, on page 2).

SYSCLK is an 80 MHz oscillator and MCCLK is a 50 MHz oscillator with clock buffer (see Section Table 5.1, “Input Clock Source”, on page 21).

Appendix B: A minor change to the first paragraph in section B.2.3 DDR

SDRAM Clock Signals A minor change in B.3.4 SRAM Memory Devices and change in

part number of Cypress control SRAM (see Table B.7, “Recommended Control SRAM Devices,” on page 42).

February 05 SBS 2110 DO 08 1.2.0 Changed the name of the document from “iSNAP2110 Reference Board User’s Manual” to “iSNAP2110 Reference Board Design Guide”

Updated the document to reflect the following: Half-width memory device support. Rev 2.0 of the board layout design guidelines (APPENDIX B:

“Reference Board Design Guidelines”) Removed the Bill of materials (BOM) from this document (the BOM is

included in the design package).

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iv Silverback Systems Confidential iSNAP2110 Hardware Reference Manual

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SILVERBACKContents

1 Introduction 11.1 Audience 1

1.2 In This Manual 1

1.3 Package Contents 2

1.4 System Requirements 2

1.5 Product Overview 2

1.6 Other Sources of Information 2

1.7 Service and Support 3

2 Reference Board Architecture 52.1 Features 5

2.2 Hardware Specifications 6

3 Reference Board Interfaces 7

3.1 RGMII Gigabit Ethernet Interface 7

3.1.1 GE PHY Operating Mode Configuration 8

3.2 DDR SDRAM Memory Interface 8

3.3 Control SRAM Memory Interface 9

3.4 General Purpose Memory Interface 10

3.4.1 Flash Memory Interface 10

3.5 PCI/PCI-X Interface 11

3.5.1 PCI/PCI-X Present Signals 113.5.2 PCI Multifunction Support 123.5.3 PCI JTAG 12

3.6 JTAG Interface 12

4 Electrical and Mechanical Specifications 134.1 Power Consumption 13

4.2 Environmental Specifications 14

4.3 Mechanical Specifications 14

4.3.1 Dimensions 144.3.2 Board Stackup 154.3.3 Ground Scheme 15

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4.3.4 Mounting Hardware 16

4.4 Connectors 16

4.4.1 RJ45 Connectors 164.4.2 JTAG Connectors (Optional) 184.4.3 UART Daughter Card Connector (Optional) 18

5 Circuitry and Routing 215.1 Clock Circuitry 21

5.2 Reset Circuitry 23

5.2.1 iSNAP2110 Reset 23

5.3 Interrupt Routing 24

6 Setup and Configuration 256.1 Configuration and Status Parameters 25

6.1.1 LED Indicators 256.1.2 iSNAP2110 Configuration Options 266.1.3 General Purpose I/O Pins 26

Appendix A: Reference Board Layout 27

Appendix B: Reference Board Design Guidelines 31

B.1 Characteristics and Definitions 31

B.1.1 PCB Characteristics 31B.1.2 Definitions 32B.1.3 System Clocks 32

B.2 DDR SDRAM Interface Layout 34

B.2.1 VREF 34B.2.2 DDR SDRAM Memory Devices 35B.2.3 DDR SDRAM Clock Signals 35B.2.4 Address and Control Signals 38B.2.5 Data, Data Strobe and Data Mask signals 39

B.3 Control SRAM Interface Layout 40

B.3.1 Address Signals 41B.3.2 Control Signals 41B.3.3 Miscellaneous Signals 41B.3.4 SRAM Memory Devices 41B.3.5 SRAM Layout Guidelines 42B.3.6 SRAM Clock 42

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B.3.7 SRAM Data, Data Parity, and Byte Write Enable 43B.3.8 SRAM Address and Control 43

B.4 GPM Interface Layout 44

B.4.1 Flash Interface 44B.4.2 UART Daughter Card Connector Interface (Optional) 44B.4.3 GPM Flash Memory Device 44B.4.4 GPM Data and Data Parity 45B.4.5 GPM Address and Control 45

B.5 RGMII Interface Layout 47

B.5.1 RGMII Receive 47B.5.2 RGMII Transmit 48B.5.3 PCI(X) 48

Appendix C: Optional Configuration 49

Glossary 51

Index 59

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viii Silverback Systems Confidential iSNAP®2110 Reference Board Design Guide

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SILVERBACKFigures

2.1 Reference Board Block Diagram 6

3.1 Gigabit Interface 7

3.2 DDR SDRAM Memory Interface 8

3.3 Control SRAM Interface 9

3.4 GPM Interface 10

3.5 iSNAP Flash Layout for 2 MB Devices 11

3.6 JTAG Chain Configuration Block Diagram 12

4.1 iSNAP2110 Power Regulator BLock Diagram 13

4.2 iSNAP2110 Reference Board Stackup 15

4.3 iSNAP2110 Bracket Block Diagram 16

4.4 RJ45 Bock and Connector Pinout Diagram 17

4.5 UART Daughter Card Connector Pin-Out 19

5.1 iSNAP2110 Input and Output Clock Interface Block Diagram 22

5.2 Reference Board Interrupt Interface Block Diagram 24

A.1 iSNAP2110 Reference Board Layout, Top View 28

A.2 iSNAP2110 Reference Board Layout, Bottom View 29

B.1 PCB Recommended Dimensions 31

B.2 Clock Distribution – MCLK and CPU CLK 33

B.3 Clock Distribution – SYSCLK 33

B.4 VREF Generation 34

B.5 Example of DDR SDRAM Memory Array 35

B.6 DDR SDRAM Routing Guidelines – Clock Signals 36

B.7 DDR SDRAM Clock Topology 37

B.8 DDR SDRAM Address and Controls Topology 38

B.9 DDR SDRAM Data, Data Strobe, and Data Mask Topology 40

B.10 Example ZBT SRAM Memory Array 40

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B.11 SRAM Clock Signal Topology 42

B.12 SRAM Data, Data Parity, and Byte Write Enable Topology 43

B.13 SRAM Address and Control Signal Topology 43

B.14 GPM Data and Data Parity Signal Topology 45

B.15 GPM Address and Control Signal Topology – Option 1 46

B.16 GPM Address and Control Signal Topology – Option 2 46

B.17 RGMII Data/Clock ReceiveTopology 47

B.18 RGMII Data/Clock Transmit Topology 48

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SILVERBACKTables

3.1 Default Operating Mode Configuration 8

3.2 DDR SDRAM Data Strobe, Data Mask & Data Bus Mapping 9

4.1 Reference Board Power Consumption 13

4.2 Operating Conditions 14

4.3 Mechanical Specifications 14

4.4 GE Port Connectors 16

4.5 PCI Power and Ground Pins 17

4.6 JTAG Connector Pin-Out 18

4.7 UART Daughter Card Connector Pinout 18

5.1 Input Clock Source 21

5.2 Output Clock Source 22

6.1 BIST LEDs 25

6.2 GE PHY LEDs 26

6.3 iSNAP2110 GPM Strap Options 26

A.1 iSNAP2110 Reference Board Components 27

B.1 VREF Circuitry Relationship 34

B.2 Recommended DDR SDRAM Devices 35

B.3 DDR SDRAM Address and Controls Topology (ending at the center DDR SDRAM) 38

B.4 DDR SDRAM Address and Controls Topology - (starting at the center DDR SDRAM) 38

B.5 DDR SDRAM Address and Controls Topology (for all 20 Address and Control bits) 39

B.6 Data, Data Strobe, and Data Mask 39

B.7 Recommended Control SRAM Devices 42

B.8 Recommended Flash Device 44

C.1 HBA Memory Requirement 49

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xii Silverback Systems Confidential iSNAP®2110 Reference Board Design Guide

iSNAP®2110 Referenc

CHAPTER 1 Introduction

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SILVERBAC1.1 Audience

The iSNAP®2110 Reference Board Design Guide is intended for developers who are designing, developing, and delivering the Host Bus Adaptor (HBA) boards integrating the iSNAP2110 IP Storage Network Access Processor into their system for use with their storage applications.This guide describes the iSNAP2110 Reference Board, which contains the iSNAP2110 device and ancillary memory devices that allow you to run the iSNAP2110 Reference driver (in a Linux® environment) and access iSNAP2110 functionality. In addition to describing the board architecture and the board layout design guidelines, this guide includes a description of various types of interfaces to the iSNAP2110 Reference Board, generic power, thermal, mechanical, and connector specifications.

1.2 In This Manual

The iSNAP2110 Reference Board Manual is organized in the following fashion: Chapter 2, “Reference Board Architecture” provides an overview of iSNAP2110 Reference Board physical and functional architecture.

Chapter 3, “Reference Board Interfaces” provides a functional description of the major interfaces of the iSNAP2110 Reference Board.

Chapter 4, “Electrical and Mechanical Specifications” provides a functional description of the reference board electrical requirements, mechanical, and connector components.

Chapter 5, “Circuitry and Routing” contains clock circuitry, reset circuitry, and interrupts on the iSNAP2110 Reference Board.

Chapter 6, “Setup and Configuration” covers in detail how to set up and configure the iSNAP2110 Reference Board.

APPENDIX A: Reference Board Layout illustrates the placement of components on the iSNAP2110 Reference Board.

APPENDIX B: Reference Board Design Guidelines provides the iSNAP2110 Reference Board layout guidelines.

APPENDIX C: Optional Configuration provides a description of the iSNAP2110 supported memory configuration.

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Introduction

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SILVERBACK1.3 Package Contents

The iSNAP2110 Reference Board is part of the iSNAP21xx System Development Kit (SDK), which includes, the iSNAP21xx Reference Driver (Linux only), and a complete documentation set. The iSNAP2110 Reference Board also includes the iSNAP2110 processor. Within the Linux environment, the iSNAP2110 Reference Board and the iSNAP21xx Reference Driver can be used to configure your system and test some of the iSNAP2110 processor features (see the iSNAP2110 Getting Started Guide for an overview of suggested test scenarios).

1.4 System Requirements

Following are the minimum system requirements for the iSNAP2110 Reference Board:Host-based Configuration

PCI-based, Host PC with an available PCI-X or PCI slot Red Hat® Enterprise Linux® 3.0 operating system (if used with the iSNAP21xx

Reference Driver) External Ethernet cables – Category 5e, unshielded, twisted pair

In the above configuration, all required power and signals are provided through the PCI interface.

1.5 Product Overview

The iSNAP2110 Reference Board provides a platform for the iSNAP2110 processor.Dimensions

Height: 3.0 in (7.6 cm) Length: 6.6 in (16.8 cm)

Operating Temperature: 0°C to 55°C

Host Operating System: Linux (if used with the iSNAP2110 Reference Driver)

Power Consumption: 6.8W typical and 9.97W maximum, with 1MB ZBT SRAM and 64MB DDR DRAM.

1.6 Other Sources of Information

For an in-depth presentation of the Silverback Systems iSNAP2110 software, hardware design fundamentals and applications, see the following publications:

Introduction to the iSNAP

iSNAP21xx Device API Reference Manual

iSNAP21xx iSCSI Target Driver API Guide / iSNAP21xx iSCSI and TOE API Guide

iSNAP2110 Hardware Reference Manual

iSNAP Getting Started Guide

2 Silverback Systems Confidential iSNAP®2110 Reference Board Design Guide

Service and Support

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SILVERBACK1.7 Service and Support

Silverback Systems provides access to customer support via the Silverback website at the following address:

http://www.silverbacksystems/support.com

An Account ID and password, supplied by Silverback Systems, is required to access the information available from this link.

iSNAP®2110 Reference Board Design Guide Silverback Systems Confidential 3

https://supportcenteronline.com/ics/support/default.asp?deptID=613

Introduction

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CHAPTER 2 Reference Board Architecture
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SILVERBACThis chapter describes the physical and functional architecture of the iSNAP2110 Reference Board.

2.1 Features

The iSNAP2110 Reference Board contains the following features:Dual Gigabit-Ethernet ports compliant with IEEE 802.3Z standard. Both ports offer:

Full Duplex 1000BASE-T with 10/100/1000 speed, automatic MDI/MDIX detection, and auto-negotiation support. Reduced Gigabit Media Independent Interface (RGMII) PHY interface, compatible with

RGMII v1.3 specification.Onboard Memory

Note: See APPENDIX C: “Optional Configuration” for the memory configurations supported. Up to 128 MB of packet and context buffer memory (DDR SDRAM) using one

iSNAP2110 global memory layer (one chip-select) interface. In this reference board, DDR SDRAM may be used only in half-width (36-bits) configuration. The default design uses 64 MB DDR SDRAM for half-width memory operation. Up to 2 MB of Control Memory (ZBT SRAM) using one iSNAP2110 control memory

layer (one chip-select) interface. In this reference board, SRAM may be used only in half-width (36-bits) configuration. The default design uses 1 MB ZBT SRAM for half-width memory operation. Boot from Flash. Up to 2 MB of Flash memory. The default design also uses 2 MB of

Flash memory.Host Interface is PCI 2.3 and PCI-X 1.0a specification compliant.The PCI-X and PCI interface is 64-bit/133 Mhz/100 Mhz/66 Mhz or 64-bit/32-bit/33 MHz/66 MHz interface, respectively.

PCI Multifunction support with 4 interrupts (contact Silverback Systems for support of multi-function). D3 Hot and D3 Cold support.

Gigabit-Ethernet port dual LED indicators.

Green LED for Link/Activity indication. Bi-color LED for speed (1000/100/10) indication.

JTAG – 10-pins JTAG header for JTAG Scan test connector.

On-board reset/clock circuitry.

General purpose LEDs controlled by iSNAP2110 software for code tracing and status indication.


Reference Board Architecture

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SILVERBACK2.2 Hardware Specifications

Figure 2.1 is a functional block diagram of the iSNAP2110 Reference Board. The interfaces and circuit areas of the board are described in Chapter 3, “Reference Board Interfaces”, and Chapter 5, “Circuitry and Routing”.

Figure 2.1 Reference Board Block Diagram

The iSNAP2110 Reference Board integrates the iSNAP2110 processor into a working environment including the required connector interfaces and memory. When it is used in conjunction with the iSNAP21xx iSCSI Target Driver API Guide / iSNAP21xx iSCSI and TOE API Guide , the iSNAP2110 Reference Board is functional only in a Red Hat® Enterprise Linux® 3.0 operating environment. However, drivers can be ported to other operating systems, see “iSNAP21xx Porting Guide” for details.

2 Pin Header

GEPHY

GEPHY

SMBus

CS0n

1MBZBT SRAM

iSNAP2110

2MB Flash

64 MBDDRSDRAM

GPIO

Clocks Input

PCI/PCI-X Connector

PCI/P

CI-X

PCI/PCI-X 32/64 bit33/66/100/133Mhz

3.3V to 2.5V3.3V to 1.5V

Source from50Mhz Osc

10-pinsJTAG

Header

Power Soucce

Clock DistributionMCLK

CPU_CLKMDIO

Management I/F

Shielded RJ45 Connector withintegrated Gigabit EthernetMagnetic Transformer and LEDs

RJ-45

RJ-45GEPort 1

GEPort 0

RGMII

RGMII

JTAG

Source from80Mhz OscSYS_CLK

25MhzREFCLK

25MhzREFCLK

half-widthoperation

half-widthoperation



CHAPTER 3 Reference Board Interfaces

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SILVERBACThis chapter provides descriptions of the following interfaces on the iSNAP2110 Reference Board:

RGMII Gigabit Ethernet Interface

DDR SDRAM Memory Interface

Control SRAM Memory Interface

General Purpose Memory Interface (Flash Memory)

PCI/PCI-X Interface

JTAG Interface

3.1 RGMII Gigabit Ethernet Interface

The iSNAP2110 Reference Board provides two Gigabit-Ethernet ports (see Figure 3.1) to carry IP traffic from the network to the iSNAP2110 processor using CAT-5e cable.

Figure 3.1 Gigabit Interface

Both GE ports support full duplex 10/100/1000 speed with automatic MDI/MDI-X crossover detection and auto-negotiation. A straight cable or a crossover cable can be used to connect the Reference Board to a switch or another Reference Board. The GE PHY interfaces to the iSNAP2110 MAC through RGMII interface. The GE interface connects to the shielded RJ-45 connector through an integrated Gigabit Ethernet magnetic transformer and LED. A 25 Mhz external crystal clock inputs to the GE PHY is used for REF_CLK input.The MDIO Management Interface provided by iSNAP2110 is shared by both GE PHY ports. To access a specific PHY port, the software must specify the GE PHY address as follows:

GE PHY Port 0 Interface: PHY address 0x00h.GE PHY Port 1 Interface: PHY address 0x01h.

GE Port 1

GE Port 0

MDIO Mgmt I/F

RJ-45Connector

PHY

PHY

iSNAP

Processor

RJ-45Connector

RGMII

RGMII

Shielded RJ45 Connector withintegrated G igabit EthernetMagnetic transformer and LEDs

25MHzREFCLK

25MHzREFCLK


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3.1.1 GE PHY Operating Mode Configuration

The mode10/100/1000BaseT inputs force or presents the advertised link capabilities (speed and duplex) of the GE PHY. The FRC_DPLX (Force Duplex Mode) pin when set high indicates “duplex mode”. The ANEG_DIS (Auto-Negotiation Disable) pin when set low indicates “auto-negotiation enable”. When FRC_DPLX pin, ANEG_DIS pin and all of the MODE pins are left unconnected, the default termination setting is 10/100/1000BaseT full duplex, auto-negotiation enabled, MDI crossover enabled, energy detect enabled, and 125MHz clock out disabled.Configuration options may be overwritten by register writes to the PHY with the exception of the physical address (see Chapter 8, “Registers”, in the iSNAP2110 Hardware Reference Manual). Table 3.1 shows the default hardware operating mode configuration.

3.2 DDR SDRAM Memory Interface

DDR SDRAM acts as a data buffer for the iSNAP2110 and stores communication data between the iSNAP2110 and the Host. A single layer half-width memory of DDR SDRAM memory interface to the iSNAP2110 processor is shown in Figure 3.2.

Figure 3.2 DDR SDRAM Memory Interface

The DDR SDRAM half-width data path allows stuffing option for using only the lower half of the memory device (by appropriately setting the DDR SDRAM controller). The stuffing option supports devices with a minimum of 32 MB (2 128Mb x16 devices) and a maximum of 128 MB (2 512Mb x16 devices) memory size. The half-width memory data bus width is 32-bits for data plus 4-bits for ECC that ensure data integrity. (The remaining 4-bits of DDR SDRAM in the ECC data device data mask are not used).

Table 3.1 Default Operating Mode Configuration

ANEG_DIS FRC_DPLX MODE10 MODE100 MODE1000 Effect

0 (Internal Pull down) Low

1 (Internal Pull up) High

1(Internal Pull up) High



Advertise 10/100/1000Base-T full duplex mode, Auto-Negotiation Enable.

Data ECC

DDR SDRAMx16

iSNAP2110

DDR SDRAMx16

DDR SDRAMx16

32

432-bit data + 4-bit data parity


Control SRAM Memory Interface

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SILVERBACKTable 3.2 shows the data strobe, data mask, and data bus mapping table.

3.3 Control SRAM Memory Interface

The Control SRAM stores iSNAP2110 internal data structures. Figure 3.3 shows the half-width Control SRAM interface to the iSNAP2110 processor.

Figure 3.3 Control SRAM Interface

The Control SRAM half-width data path allows stuffing option for using only the lower half of the memory device (by appropriately setting the SRAM control register). The stuffing option supports devices with a minimum of 1 MB (x 36, 9Mb) and a maximum of 2 MB (x 36, 18Mb) memory size. The half memory data bus width is 36-bits, 32-bits for data and 4-bits for parity or ECC to ensure integrity.

Table 3.2 DDR SDRAM Data Strobe, Data Mask & Data Bus Mapping

Data Strobe Signal

Data Mask Signal

Data Bus Byte Masked

Connection

DDR_DS[8] DDR_DM[8]DDR_CB[7:4] Not Connected

DDR_CB[3:0] To ECC DDR SDRAM I/F

DDR_DS[7] DDR_DM[7] DDR_D[63:56] Not Connected




DDR_DS[3] DDR_DM[3] DDR_D[31:24] To DDR SDRAM 2




iSNAP2110

ZBT SRAMx36

32-bits data +4-bits data parity



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SILVERBACK3.4 General Purpose Memory Interface

The General Purpose Memory (GPM) consists of Flash memory. Figure 3.4 illustrates the GPM interface.

Figure 3.4 GPM Interface

The GPM bus interface is 16-bits wide and runs 2.5V LVCMOS (3.3V tolerant) I/O. The iSNAP2110 Reference Board uses GPM_CS0n chip select for Flash interface and GPM_CSn[3] for the UART daughter card interface.

3.4.1 Flash Memory Interface

The Flash Memory interface is 16-bits wide, runs 2.5V I/O, and supports up to 2MB. The system uses chip select GPM_CS0n to access Flash memory (see Figure 3.4). The Flash memory contains the default configuration parameters and run time code for the iSNAP2110 processor. It contains the Basic Boot Code required to bootup the iSNAP system. (For information on upgrading the Boot Code, see the Release Notes.)

Note: The iSNAP2110 supports CFI (Common Flash Memory Interface) Flash devices1.

1. Current version the Firmware (Boot Loader) requires CFI compliant Flash device.

iS N A P 2110

GPM

Bus x

16

F la shx16

UARTReady

ConnectorG P M _C S 3_n

S tu ff O p tion

G P M B us x8

G P M _C S 0_n


PCI/PCI-X Interface

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SILVERBACK Flash Layout Granularity

The iSNAP2110 requires the following granularity of the Flash layouts to support 1 MB or 2MB Flash memory devices:

Figure 3.5 iSNAP Flash Layout for 2 MB Devices

3.5 PCI/PCI-X Interface

The iSNAP2110 Reference Board has a PCI/X interface for communication with the Host and for supplying power and reset to the iSNAP2110 processor. The system is compliant with the PCI 2.3 and PCI-X 1.0a specifications. Depending upon the Host system slot used, the system is capable of the following frequencies:

PCI 32/64 bit, 33MHz/66MHz or PCI-X 64 bit, 66MHz/100MHz/l33MHz

I/O voltage, 3.3V DC

Form factor – short, variable height PCI card

The iSNAP2110 Reference Board is considered an Expansion or Add In board in PCI terminology and is both master (Initiator) and slave (Target) capable. The iSNAP2110 Reference Board is a single PCI load, indicating that no more than one PCI device (iSNAP2110 processor) is present on board.

3.5.1 PCI/PCI-X Present Signals

The PRSNT1# and PRSNT2# pins must be terminated appropriately on an expansion board. These pins indicate to the Host system that an expansion board is present in the slot and provides the total power requirements information of the iSNAP2110 Reference Board. PRSNT1# is grounded, and PRSNT2# is open indicating that the total power required is more than 14W but less than 25W.

Basic Boot(16KB) [0 to16KB ]

Extended Boot(32KB) [16 to 48KB ]

sysCfg(8KB) [48 to 56KB ]

Mandatory

Crash Dum p(256KB) [64 to 320KB ]

User Data(192KB) [320 to 512KB ]

Appl ication(512KB)

Optional

roCfg(8KB) [56 to 64KB ]

[For 1 MB F lash 512 to 1024KB]

Note: The values in Ital ics/Blue show the sectors offset and indicates the successive sectors for the Flash layout.

[For 2 MB F lash 512 to 2048KB]



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3.5.2 PCI Multifunction SupportPCI Multifunction supports four interrupts. The PCI interface INTA#, INTB#, INTC#, and INTD# pins are used to route iSNAP2110 interrupts to the Host.

3.5.3 PCI JTAGThe iSNAP2110 Reference Board does not support PCI JTAG, but PCI_TDO signal connects to PCI_TDI to ensure that the PCI JTAG scan chain is not broken.

3.6 JTAG Interface

The iSNAP2110 Reference Board has a connector for interfacing the iSNAP2110 to a JTAG Test Access Port (TAP) emulator in JTAG mode. The iSNAP2110 input pin AK29, JTAG_MODE will normally be tied to ground to indicate JTAG operation.The Reference Board provides a boundary-scan chain. It is a fairly simple chain comprised of cascading the TDI and TDO iSNAP2110 signals with the GE PHY devices. The JTG_TCK, JTG_TMS and JTG_TRSTn signals are connected to all the components in parallel.

Figure 3.6 JTAG Chain Configuration Block Diagram

JTAG_MODE

iSNAP2110

R

V33

Flash

RESET_N

JTG_TDI

JTG_TMS

JTG_TCK

JTG_TRST_N

JTG_TDO

PCX_RST_N

R

R

V33

R

V33

JTG_TDI

JTG_TDO

iSNAP_RST_OUTn

PCX_RSTn

JTG_TCKJTG_TMS JTG_TRSTn

GE PHY1

RSTn

JTG_TRSTnJTG_TCKJTG_TMS

JTG_TDOJTG_TDIJTG_TDOJTG_TDI

GE PHY 0

RSTn

JTG_TRSTnJTG_TCKJTG_TMS

4.7KΩR =



CHAPTER 4 Electrical and Mechanical Specifications
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SILVERBACThis chapter includes the power, thermal, mechanical, and connector specifications for the iSNAP2110 Reference Board.

4.1 Power Consumption

The Reference Board regulates power down from 3.3V to 2.5V, and 1.5V using onboard voltage regulators. The 2.5V power plane will support I/O buffers and core logic of third party devices. The 1.5V power plane will support the iSNAP2110 core logic and GE PHY. Table 4.1 shows the iSNAP2110 Reference Board power consumption, which meets the maximum power consumption limit.

Figure 4.1 iSNAP2110 Power Regulator BLock Diagram

Table 4.1 Reference Board Power Consumption

Description Maximum Power Consumption [W]a

a. These are worst-case calculated values.

3.3V plane 0.97

2.5V plane 4.30

1.5V plane 4.60

Total system 9.97

V33

V33

PCI/PCI-X Connector

3.3V to 1.5Vregulator6A (max)

3.3V to 2.5Vregulator3A (max)

iSN

AP

2110

Ref

eren

ce B

oard


Electrical and Mechanical Specifications

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SILVERBACK4.2 Environmental Specifications

Table 4.2 lists the iSNAP2110 Reference Board operating conditions.

4.3 Mechanical Specifications

4.3.1 Dimensions

The reference board complies with the PCI/PCI-X form factor. Its physical characteristics are detailed in Table 4.3.

Table 4.2 Operating Conditions

Temperature Operating: 0°C to 55°CStorage: - 40°C to +125°C

Voltage 3.3V (±10%)

Humidity Operating: Relative (non-condensing:10% to 90%)Storage: 5% to 95%

Table 4.3 Mechanical Specifications

Reference Board SpecificationsBoard Dimensions: Length: 6.6 in. ± 0.005 inches

Height: 3.0 in ± 0.005 inches Thickness: 0.062 in. ± 0.008 inches

Maximum Component Heights: Component side: 570 mils Solder side: 105 mils


Mechanical Specifications

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SILVERBACK4.3.2 Board Stackup

Figure 4.2 illustrates the iSNAP2110 Reference Board stackup.

Figure 4.2 iSNAP2110 Reference Board Stackup

4.3.3 Ground SchemeThe grounding scheme includes one layer divided into two separate ground planes: signal ground and chassis ground. The chassis ground islands run the height of the board from top to bottom and are separated from the signal ground planes underneath the Gigabit Ethernet components (RJ45).

prepreg 0.0037

0.0140CORE

prepreg 0.0035

0.0100CORE

prepreg 0.0035

0.0140CORE

prepreg

SIG/PLANEL1

SIGNALL2

SIGNALL4

SIGNALL5

SIGNALL7

0.0037

SIG/PLANEL8

FR4-6(inches)

Layer Copper(Oz)

L3 PLANE

L6 PLANE

55

Z0(Single Ended ) W(Single Ended )

Differential Z0 = xx Ω

Ω

55Ω

55Ω

55Ω

55Ω

55Ω

(inches)Layer Type

W is the finished line width

0.00425

0.00425

0.00400

0.00425

0.00425

0.00400

W(Differential )(inches)

0.0075

0.0075

0.0080

0.0075

0.0075

0.0080

D(Differential )(inches)

D is the finished line space

Note:

0.0037

0.0140

0.0035

0.0100

0.0035

0.0140

0.0037

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.0045

0.0041

0.0041

0.0045

0.0041

0.0041



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4.3.4 Mounting Hardware

A bracket is provided on the rear panel edge of the board for mounting the board in a standard PCI or PCI-X slot. This allows the RJ45 connectors and LEDs to be visible and accessible when the chassis is closed.

Figure 4.3 iSNAP2110 Bracket Block Diagram

4.4 Connectors

The iSNAP2110 Reference Board requires the following connectors:Two RJ45 connectors required for the copper Gigabit Ethernet ports.

One PCI/X Connector.

One JTAG connector (optional).

Note: Refer to Appendix A (in development) for the placement of the connectors and their dimensions.

4.4.1 RJ45 Connectors

The RJ45 connectors provide copper Ethernet connectivity to the Host via Port 0 and Port 1. Table 4.4 describes pin assignments for the GE interface connectors on the iSNAP2110 Reference Board.

Table 4.4 GE Port Connectors

Pin 1 2 3 4 5 6 7 8

Signal DA_P DA_M DB_P DC_P DC_M DB_M DD_P DD_M

POR

T 1

SilverbackSystems PO

RT

0


Connectors

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Figure 4.4 RJ45 Bock and Connector Pinout Diagram

The PCI connector used on the iSNAP2110 Reference Board also provides 3.3V and 5V power to the board. Figure 4.5 lists the power and ground pins.:

Table 4.5 PCI Power and Ground Pins

Pin# Description

B19 B25 B31 B36 B41 B43 B54 B59 B70 B79 B88 A10 A16 A21 A27 A33 A39 A45 A53 A59 A66 A75 A84

+3.3V

B3 B15 B17 B22 B28 B34 B46 B50 B51 B57 B64 B67 B73 B76 B82 B85 B91 B94 A18 A24 A30 A35 A37 A42 A48 A50 A51 A56 A63 A69 A72 A78 A81 A87 A90 A93

GND

B5 B6 B61 B62 A5 A8 A61 A62 +5V

1 2 3 4 5 6

7 8 9 10 11 12

13 14 15 16

iSN

AP

2110

Ref

eren

ce B

oard



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4.4.2 JTAG Connectors (Optional)

An on-board 10 pin JTAG header is used to access the iSNAP2110 JTAG interface. The JTAG header is a dual line, 2 Rows by 5 Pin connector. The JTAG pin assignment is shown Table 4.6.

4.4.3 UART Daughter Card Connector (Optional)

The UART daughter card connector is for development purposes only. The card has a provision for a 40 Pin, part number: AMP-TYCO 17902-1 connector interface. Figure 4.5 shows the Uart pin out diagram.

Table 4.6 JTAG Connector Pin-Out

Pin # Description Pin# Description

1 TCK – Test Clock In 2 GND – Ground

3 TDO – Test Data Out 4 VCC (3.3V)

5 TMS – Test Mode Select 6 TRST_N

7 N/C - Not connected 8 N/C – Not connected

9 TDI – Test Data In 10 GND – Ground

Table 4.7 UART Daughter Card Connector Pinout

Pin Signal Name Pin Signal Name

1 GND 2 V3.3

3 GND 4 V3.3

5 GND 6 V3.3

7 GND 8 V3.3

9 INT 10 ISNAP_RST_OUTn

11 NC 12 GPM_WE_N

13 GPIO[1]/GPM_CSn[3] 14 NC

15 GPM_A[2] 16 NC

17 GPM_A[1] 18 NC

19 GPM_A[0] 20 GPM_D[7]

21 NC 22 GPM_D[6]

23 NC 24 GPM_D[1]

25 NC 26 GPM_D[2]

27 GPM_OEn 28 GPM_D[5]

29 GPM_D[0] 30 GPM_D[4]

31 NC 32 GPM_D[]3]

33 V3.3 34 GND


Connectors

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Figure 4.5 UART Daughter Card Connector Pin-Out

35 V3.3 36 GND

37 V3.3 38 GND

39 V3.3 40 GND

Table 4.7 UART Daughter Card Connector Pinout (Continued)

Pin Signal Name Pin Signal Name

13579111315171921232527

293133353739

24681012141618

202224262830323436

3840



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CHAPTER 5 Circuitry and Routing

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SILVERBACThis chapter provides descriptions of the following circuit and interrupts on the iSNAP2110 Reference Board:

Clock Circuitry

Reset Circuitry

Interrupt Routing

5.1 Clock Circuitry

The iSNAP2110 receives clock inputs from a number of sources and generates clock outputs. All clocks are LVCMOS logic level. The input clock sources are described in Table 5.1.

Figure 5.1 shows the iSNAP2110 and the system level clock (both input and output clocks) interface block diagram.

Table 5.1 Input Clock Source

iSNAP2110 Input Clock Frequency Source Type External, Oscillator

PCX_CLK 33/66/100/ 133MHz PCI/PCI-X host computer

CPUCLK 50MHz External 50 MHz Osc with clock buffer

SYSCLK 80MHz External 80 MHz Osc

MCLK 50MHz External 50 MHz Osc with clock buffer

GPP_CLK Not used Not used

GMACCLK Not used Not used

GE0_RXCLK 2.5/25/125Mhz From GE0

GE1_RXCLK 2.5/25/125Mhz From GE1

TCK adjustable External JTAG


Circuitry and Routing

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Figure 5.1 iSNAP2110 Input and Output Clock Interface Block Diagram

The output clock sources are described in Table 5.2.

Table 5.2 Output Clock Source

iSNAP2110 Output Clock Frequency Source Type Internal, PLL

Logic Levels

SRM_CLK 125MHz PLL (=2.5*MCLK) 2.5V LVCMOS

SRM_DUP_CLK (not used) 125MHz PLL (=2.5*MCLK) 2.5V LVCMOS

GPM_CLK (Not used) 125MHz SRM_CLK Internal 2.5V LVCMOS

iSNAP2110OSC50Mhz

MCLK

CPU_CLK

SYS_CLK

QMSSRAM

QMSSRAMSRM_CLK

GE 0

DDRSDRAM

GE0_GTXCLK

GE 1GE1_GTXCLK

DDRSDRAM

DDRSDRAM

DDR_FBK_CLK_P/N

DDR_CLK[0]_P/N

DDR_CLK[2]_P/N

x16 ECC

2.5/25/125Mhz

150Mhz

150Mhz

25Mhz

125Mhz

50Mhz

80Mhz

GE1_RXCLK

GE0_RXCLK

x16

x16

PCX_CLK

2.5/25/125Mhz

GMACLK

2.5/25/125Mhz

2.5/25/125Mhz

0 ohm

NO_LOAD

CLK125

CLK125

From PCX connector

OSC80Mhz

CDCV304

REF_CLK

25Mhz REF_CLKPHY1_CLK

PHY2_CLK

NC

NC

NC = Not Connected

DDR_CLK[1]_P/NNC


Reset Circuitry

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5.2 Reset Circuitry

The PCI-X Pin (PCX_RSTn) resets the iSNAP2110. The iSNAP2110 signal, iSNAP_RST_OUTn, resets the Flash, GE PHY, and UART devices. The JTG_TRSTn input pin of the iSNAP2110 and GE TRSTn pin are typically tied down but can be connected to the JTG_TRSTn input, using the appropriate stuff option. See Figure 3.6, “JTAG Chain Configuration Block Diagram,” on page 12 for the reset circuitry.

5.2.1 iSNAP2110 Reset The input pin, the PCI-X reset signal (PCX_RSTn) will reset the iSNAP2110. The output pin (RST_OUTn), of the iSNAP2110 contains the qualified internal chip reset. This active low qualified Reset Output from the iSNAP2110 is the input to the Boot Flash and GE PHYs (see the iSNAP2110 Hardware Reference Manual for details).

FLH_CLK (Not used) f/2 or f/4, f=GPMClk Internal 2.5V LVCMOS

DDR_CLK[2]/_N 150 MHz PLL (=3*MCLK) SSTL-2 Differential

DDR_CLK[1]/_Na 150 MHz PLL (=3*MCLK) SSTL-2 Differential

DDR_CLK[0]/_N 150 MHz PLL (=3*MCLK) SSTL-2 Differential

GE1_GTX CLK 2.5/25/125 MHz SRM_CLK(/50,/5,/1) Internal

2.5V LVCMOS

GE0_GTXCLK 2.5/25/125 MHz SRM_CLK(/50,/5,/1) Internal

2.5V LVCMOS

PHY1CLK Not used Internal, SYS_CLK input /2

2.5V LVCMOS

PHY2CLK Not used Internal, SYS_CLK input /2

2.5V LVCMOS

a. Not connected.

Table 5.2 Output Clock Source (Continued)

iSNAP2110 Output Clock Frequency Source Type Internal, PLL

Logic Levels


Circuitry and Routing

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SILVERBACK5.3 Interrupt Routing

The iSNAP2110 interrupt input pin is driven by one of the GE PHY interrupts—both selectable by 0 ohm resistors or by the UART interface. The iSNAP2110 sends an interrupt to the Host via any of the PCI/X signal INTx# in a Host-based configuration (see the iSNAP2110 Hardware Reference Manual for details).

Figure 5.2 Reference Board Interrupt Interface Block Diagram

iS N A P 2110G E P H Y 0

IN T #

PCI/P

CI-X

Con

necto

r

G E P H Y 1

IN T #

IN T A #

IN T n

IN T D #

IN T C #

IN T B #

R

2.5V

UART

daug

hter

card

Con

necto

r N ote : U A R T daugh te r ca rd inve rts the in te rrup t to d rive low



CHAPTER 6 Setup and Configuration

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SILVERBACThis chapter describes the installation and configuration of the iSNAP2110 Reference Board.

6.1 Configuration and Status Parameters

The operational status of the iSNAP2110 Reference Board is indicated by a set of onboard LEDs indicating BIST status and GE port status.

6.1.1 LED Indicators

6.1.1.1 BIST LEDs

BIST LEDs indicate development and debugging status, which are shown in Table 6.1.

Table 6.1 BIST LEDs

BIST bits LED Description

ISNAP_BIST<0> DS1 BIST self test indication for successful boot up from the Flash image ON: PassOFF: Fail

ISNAP_BIST<1> DS2 BIST self test indication for DDR SDRAM TestON: PassOFF: Fail

ISNAP_BIST<2> DS3 BIST self test indication for ZBT SRAM TestON: PassOFF: Fail


Setup and Configuration

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6.1.1.2 Gigabit-Ethernet LEDs

Gigabit Ethernet activity, link and speed status are provided by the RJ45 modules. The GE PHY LEDs are shown in Table 6.2.

6.1.2 iSNAP2110 Configuration Options

There are twenty pins of the iSNAP2110 GPM address bus, which are sampled on power up to direct the iSNAP2110 to configure itself in various states. GPM_SA[19:14, 12:0] use their default value, and GPM_SA[13] must be pulled up through a 470 ohm resistor to 2.5V. The strap option is shown in Table 6.3.

6.1.3 General Purpose I/O Pins

There are eighteen pins on the iSNAP2110, which can be used as General Purpose inputs or outputs (GPIOs). Some of the pins have predefined usage in the iSNAP firmware. Each of the GPIO pins can be used either in its normal function for one of the modules within the iSNAP2110, or as a GPIO. See Section “3.6 GPIO Interface” of the“iSNAP2110 Hardware Reference Manual” for a list of functional Pins used as general purpose I/O Pins.

Table 6.2 GE PHY LEDs

GE LED LED Color Description

Link Status(10/100/1000 Speed)

Bi-Color LEDGreen/Orange

GREEN: 1000 speedORANGE: 100 speedOFF: 10 speed.

Link Activity Green ON: Link is establishedOFF: Link is NOT establishedBlinking: Activity

Table 6.3 iSNAP2110 GPM Strap Options

Strap Source Strap Name Strap Description Resistor Default

Value

GPMSA[13] bypass_sys_PLL_out Bypass PN PLL PLLoutB and use system oscillator for system clock

R34 Pull Up (High)



APPENDIX A: Reference Board Layout

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SILVERBACTable A.1 lists the key components on the Reference Board Layout. (A complete the Bill of Materials is included with the design package.) These components are identified in both the top view and bottom view of the Reference Board. Figure A.1 and Figure A.2 refers to Reference Board Revision 2.0.

Note: The columns labeled “Item No.” and “Ref. No.” refers to the columns labeled the same in the Bill of Materirals (BOM) included witht the design package.

Table A.1 iSNAP2110 Reference Board Components

Item No. Ref. No. DescriptionTop View18 U1 Storage Network Processor, ISNAP2110

16 U7 Flash 1Mb x 16, 70ns, 48TSOP

15 U2, U11, U15 DDR SDRAM 256 Mb, 16 MB x16, SSTL-2

19 U8 ZBT SRAM, 9Mb, 256KbX36, 167MHZ, 2.5V

20 U9, U14 Gigabit-Ethernet PHYs (10/100/1000)

22 U4, U13 RJ-45 Conenctors

11 DS1-DS3 BIST status LEDs

12 U3 Voltage Regulator, 3.3V to 2.5V

13 U12 Switch Regulator 3.3V to 2.5V

14 U10 1:4, 8-Pin TSSOP Clock Buffer

41 X1, X3 Crystal 25 MHz

42 X4 Oscillator 50 MHz

43 X2 Oscillator 80 MHz

21 J2 JTAG (10 Pins)

Bottom ViewOptinal (Not Stuffed)

J3 UART I/F board-to-board connector


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Figure A.1 iSNAP2110 Reference Board Layout, Top View

U2Item No: 15

U11Item No: 15

U15Item No: 15

J2Item No: 21

U8Item No: 18

U7Item No: 16

U4Item No: 22

U13Item No: 22

U14Item No: 20

U9Item No: 20

X3Item No: 41

X1Item No: 41

X4Item No: 42

U10Item No: 14

X2Item No: 43

U1Item No: 18

U3Item No: 15

U12Item No: 12


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Figure A.2 iSNAP2110 Reference Board Layout, Bottom View

J3 - Not stuffedUART Connector


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APPENDIX B: Reference Board Design Guidelines
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SILVERBACThis chapter describes the Silverback Systems Reference Board design guidelines and recommendations. The chapter includes: guidelines for the board layout of the external DDR SDRAM, ZBT SRAM, and GPM memory interfaces as well as the RGMII and PCI/PCI-X interfaces. Topics addressed include choice of memory device, placement of parts, maximum trace length, and routing requirements as well as power, grounding and impedance characteristics. For detailed information on the iSNAP2110, please refer to the iSNAP2110 Hardware Reference Manual.

Note: The layout guidelines are based on the iSNAP2110 ver2.0 Reference Board simulation.

B.1 Characteristics and Definitions

B.1.1 PCB Characteristics

That following is a general guideline for the PCB characteristics of all the interfaces. The actual dielectric coefficient, thickness and copper weight will be determined by the PCB fabrication facility along with the designer, taking in count:

Layer count.

Desired typical impedence (Z0).

Cost.

Total board thickness and size.

Figure B.1 PCB Recommended Dimensions

To achieve the required timing and Signal Integrity (SI), the PCB should follow these recommendations:

Controlled impedance: single ended, Z0 = 50Ω, and differential Z0 = 100Ω.

The trace width W (see Figure 4.2 on page 15) is determined by the relative Dielectric Coefficient Er, and the available thickness of dielectric H, and is calculated to achieve 50Ω.

Trace separation is S ≥ 2 x W (center-to-center).

W

S

H

S = Trace SeparationW = Trace WidthH = Dielectric thickness


Characteristics and Definitions

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General layout considerations:Traces should be routed with a minimum numbers of vias and minimum layer switching.

All signals are routed in layers that are adjacent to the GND planes.

Note: Extra care should be taken when placing and routing the board to meet timing budget and avoid SI problems.

B.1.2 Definitions

This section describes the terminology used in this appendix.Extended Net – An extended net intersects one or more passive device (resistor, inductor or capacitor). Each net segment is represented by an individual transmission line in the topology.

Pin-Pair – A pair of logically connected pins, e.g., a driver-receiver connection. A group1 of pin-pairs need not be directly connected to each other but must exist on the same net or extended net.

Target pin-pair – One of the pin-pairs explicitly defined as the target within a group of pin-pairs. All the other pin-pairs in the group are matched against this target pin-pair within the given delta2 and tolerance3. Within a group of pin-pairs:

If all the pin-pairs have a delta value, the pin-pair with the smallest delta value is selected as the target pin-pair. If more than one pin-pair has the same (smallest) delta value, the pin-pair with the longest length is selected as the target.

Note: The target pin-pair is referenced by all the other pin-pairs within a group of pin-pairs.

B.1.3 System Clocks

The clock inputs to the iSNAP2110 (MCLK, CPUCLK, and SYSCLK) are single ended (Figure B.2 and Figure B.3). The 50MHz oscillator drives a 1:2 clock buffer with one output each connected to MCLK and CPUCLK. The trace lengths should be as short as possible. An 80 MHz oscillator drives the SYSCLK input. The following are the design recommendations:

Route the clocks next to a GND layer with a minimum of vias.

To avoid crosstalk, separate clock signals from other signals. Clock signals should be separated from other signals by a distance of S, which is at least three times the trace width (i.e., X ≥ 3W – see Figure B.1).

Keep the clocks away from the edge of the board and any connectors.

1. Group of pin-pairs – a user-specified collection of pin-pairs constrained by a match length.2. Delta – the difference between each pin-pair and the target pin-pair. If the delta is zero, all the pin-pair are

required to match. For example, here all deltas are 0 mils

3. Tolerance – the skew allowed when matching a group of pin-pairs. For example, ±50 mils, indicate that the range between the shortest and longest pin-pairs is 100 mils. The target pin-pair has 0 mils tolerance.


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Figure B.2 Clock Distribution – MCLK and CPU CLK

Figure B.3 Clock Distribution – SYSCLK

Segment L11 L12Lengtha

a. All trace lengths are in inches

0.25” As short as possible

Matching From pin to pin (L11+L12) one pin-pair should be = the target pin-pair ±50 mils



0.25” As short as possible

Matching N/A

Clock Buffer CDCV

50 MHz

MCLK

CPU CLK

33ΩL11 L12

33ΩL11 L12

OSC

iSNAP2110

80 MHz SYS CLK

33ΩL21 L22OSC

iSNAP2110


DDR SDRAM Interface Layout

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SILVERBACKB.2 DDR SDRAM Interface Layout

This section outlines the necessary layout guidelines for a board with iSNAP2110 and a DDR SDRAM interface (see Table B.2). The DDR SDRAM interface is designed to run at a frequency of 150MHz. The DDR SDRAM samples the data at both rising and falling edges of the strobe. The address and controls are sampled at the rising edge of the clock.

B.2.1 VREF

The following JEDEC SSTL-2 standard for VREF circuitry relationship ensures successful operation of the DDR SDRAM (Table B.1): 1. VREF will sink very low current (leakage current).2. VREF should be implemented with a local voltage divider per each DDR SDRAM component

and iSNAP2110 VREF. This is to enable tracking of the local VDD of the specific component. The two thevenin resistors should be placed very close to their corresponding component (Figure B.4).

Figure B.4 VREF Generation

Table B.1 VREF Circuitry Relationshipa

a. All voltages are referenced to Vss, which is defined as the device GND.

Symbol Parameter Min Type Max UnitsVDD Device Supply Voltage VDDQ N/A V

VDDQ Output Supply Voltage 2.3 2.5 2.7 V

VREF Input Reference Voltage 1.15 1.25 1.35 V

4.7K 1%

4.7K 1%

VDDQ

VREFVTT

VTT Island close to M

emories

Rpack

Rpack

Rpack

Cap

Cap

Cap

Cap

Cap

1.25VV

RM

0.1µF

0.1µF


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SILVERBACKB.2.2 DDR SDRAM Memory Devices

The choice of memory depth and width will affect the part count for the DDR SDRAM memory subsystem design. This section covers the x16 width with three devices per memory array4 (Figure B.5). The iSNAP2110 is capable of supporting a maximum of 4 memory arrays using the four chip select signals (CS0_N - CS3_N).

Figure B.5 Example of DDR SDRAM Memory Array

Note: The iSNAP2110 does not prevent the designer from choosing other topologies, as the principles used in the three devices per memory array design may be scaled down or extended.

If DDR SDRAM (256 Mb – 16Mb x 16) devices are used, the amount of memory will be 64 MB per memory array. In a dual memory array subsystem, these devices will output a total capacity of 128 MB. In a quad memory array subsystem, these devices will output a total capacity of 256 MB. The DDR SDRAM devices used on this reference design are in a 66 pin TSOP package available from companies such as Samsung, Hynix, and Micron. These are pin for pin compatible replacement devices for one another. Table B.2 lists the recommended DDR SDRAM devices

B.2.3 DDR SDRAM Clock Signals

The DDR SDRAM clocks (DDR_CLK[2:0]) are driven by the iSNAP2110. In the reference design, only two clock pairs are used DDR_CLK[2]P/N and DDR_CLK[0]P/N. The DDR_CLK[2:0]P/N pairs must be designed taking into account the AC timing parameters. Refer to Chapter 5 “Clocking and Timing” of the “iSNAP2110 Hardware Reference Manual” for details.

4. A memory array is a cluster of memory devices sharing the same chip select signal.

Table B.2 Recommended DDR SDRAM Devices

Manufacturer Device Organization Description Package Part NumberSamsung DDR SDRAM 16Mb x 16 256 Mb SSTL-2, DDR333@CL=2.5 TSOP-II 66 K4H5638F-TC/LB3

Hynix DDR SDRAM 16Mb x 16 256 Mb SSTL-2, DDR333@CL=2.5 TSOP-II 66 HY5DU561622DT-J

Micron DDR SDRAM 16Mb x 16 256 Mb SSTL-2, DDR333@CL=2.5 TSOP-II 66 MT46V16M16TG-6T

CS0_N

iSNAP2110

One Memory ArrayECC

DATA

DDR SDRAMx 16

DDR SDRAMx 16

4

32



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The following are the design recommendations (see Figure B.6): Ensure that the clock phase at the feedback input is within ± 100ps of the phase at memory.

Keep the clocks away from the edge of the board and any connectors.

Traces should be routed with a minimum numbers of vias and no layer switching.

Each signal must have a reference layer with the following characteristics:

The GND plane(s) as first choice or the PWR plane(s) as a second choice.No splits or discontinuities.

To allow best mutual coupling, signals pairs (positive and negative parts of a signal) should be routed with the recommended distance, D (see Figure 4.2, “iSNAP2110 Reference Board Stackup,” on page 15).

The placement of the parallel termination and its Vias must be placed in such a way that it prevents the signals from being too far apart (see Figure B.6).

To avoid crosstalk, separate the clock signals from each other. The signals should be separated from each other by a distance of S, which is at least three times the trace width (i.e., X ≥ 3W – see Figure B.1)

Figure B.6 DDR SDRAM Routing Guidelines – Clock Signals

iSNAP Via

Clock Trace in aninner layer (adjacentto a GND plane)

ParallelTermination Via

Memory Via

D - RecommendedDistance


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Figure B.7 DDR SDRAM Clock Topology

Note: DDR_CLK1_P/N is not used. The differential resistor should be placed at the junction of L1 and L2, which is the split point of the differential pair.



1.25” 1.25”

Matching From pin to pin (L1+L2), each of the four pin-pairs should be = the target

pin-pair ± 25 mils.

DDR SDRAM (ECC)

DDR SDRAM CLK #2

DDR SDRAM CLK #0

DDR SDRAM FB CLK

100

100 Ω

iSNAP2110

L2

L2

L1

L1 L2

L2

Ω

L1

L1

L2

L2

L2

L2

DDR SDRAM

DDR SDRAM



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B.2.4 Address and Control Signals

The Address and Control lines (RAS, CAS, CS, WE, BA and CKE) should all be routed following the same topology. Figure B.8 shows a typical address and control bit, each with 3 loads. Each address and control bit goes to the center DDR SDRAM first.

Figure B.8 DDR SDRAM Address and Controls Topology

The following lists the rules/options for matching lengths for address and control bits: Table B.3 shows the rules that apply for the portion of the topology ending at the center DDR SDRAM device among the address and control signals.

Table B.4 shows the rules that apply for the two portions of the topology starting at the center DDR SDRAM device going to the other two loads for each individual signal. .

Table B.3 DDR SDRAM Address and Controls Topology (ending at the center DDR SDRAM)

Segment L1 L11Length a


0.5” 3.0”

Matching From pin to pin (L1+L11) one pin-pair should be = the target pin-pair ±25 mils.

Table B.4 DDR SDRAM Address and Controls Topology - (starting at the center DDR SDRAM)

Segment L2Length a


0.75" ≤ L2 ≤ 1.0"

Matching From pin to pin (L2) one pin-pair should be = the target pin-pair ±25 mils

iSNAP2110

33Ω

DDR SDRAM

L2

L11L1

L2

DDR SDRAM

DDR SDRAM

See tables B.3, B.4, and B.5 for various options.


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Table B.5 shows the rules that apply for all 20 Address and Control bits, with one or more loads .

B.2.5 Data, Data Strobe and Data Mask signals

Each byte of data (DQ[i]) and the ECC byte, the corresponding data strobe (DQS[n]) and mask (DQM[n]) (Table B.6) should be routed together, with an inter-group5 matching of ± 500 mils and intra-group matching of ± 50 mils. The overall length of any given byte should be between 1.5 and 2.5 inches (Figure B.9).

General layout considerations (see Figure B.9):Traces should be routed with a minimum numbers of vias and no layer switching.

Each signal must have a reference layer with the following characteristics:

The GND plane(s) as first choice or the PWR plane(s) as a second choice.No splits or discontinuities.

To avoid crosstalk, separate signals from each other. Signals should be separated from each other by a distance of S, which is at least twice the trace width (i.e., S ≥ 2W – see Figure B.1).

Keep L1 as short as possible. The maximum allowed length is 500mils.

Table B.5 DDR SDRAM Address and Controls Topology (for all 20 Address and Control bits)

Segment L1 L11 L2Length a


0.5" 3.0” 0.75" ≤ L2 ≤ 1.0"

Matching From pin to pin (L1+L11+L2) one pin-pair should be = the target pin-pair ± 50 mils

5. Group (intra or inter) is defined as 8 data bits and the corresponding data strobe and data mask signals.

Table B.6 Data, Data Strobe, and Data Mask

DQ[i]i = [n*8]:[(n*8) + 7]a

a. n = 0 to 3

DQS[n] DQM[n]

DQ[7:0] DQS[0] DQM[0]

DQ[15:8] DQS[1] DQM[1]

DQ[23:16] DQS[2] DQM[2]

DQ[31:24] DQS[3] DQM[3]

ECC-D [7:0] DQS[8] DQM[8]


Control SRAM Interface Layout

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Figure B.9 DDR SDRAM Data, Data Strobe, and Data Mask Topology

B.3 Control SRAM Interface Layout

The iSNAP2110 Control Memory SRAM interface provides clock, data, address and control signals to the external SRAM memory. The iSNAP2110 provides two copies of the SRAM clock on pins SRM_CLK and SRM_DUP_CLK. Each clock signals can be routed to a maximum of four devices. Data is 72 bits wide and runs 2.5V I/O. There are 64 bits of data (SRM_D [63:0]), and 8 bits of parity (SRM_DP [7:0]), to support data integrity. There are 20 bits of address on pins SRM_A [19:0]. A shared pin, A20/SRM_CSn[3], may be used as SRM_A20 if SRM_CSn[3] is not used. The four chip select outputs (SRM_CSn [3:0]), are active low. These pins allow connection for up to four memory arrays (Figure B.10). The Write Enable, SRM_WEn, is active low. There are eight SRAM byte write enable outputs (SRM_BWn[7:0]), which are also active low.

Figure B.10 Example ZBT SRAM Memory Array

Segment L1 L2 Lengtha

a. All trace lengths are in inches.

0.5" 1.0" ≤ L2 ≤ 2.0"

Intra-Group matching Within a 10 bit groupb

b. 8-Bits data + Strobe + Mask

From pin to pin (L1+L2), each of the 10 pin-pairs should be = target pin-pair ±50 mils.

Inter-Group matching Among all the 10 bit groupsb.

From pin to pin (L1+L2), each of the 10 Bit groups should be = the target pin-pair ±500 mils

iSNAP2110

ΩL2L1

DDR SDRAM33

CS0_N

iSNAP2110

One Memory Array

DATA + ECC ZBT SRAMx36


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SILVERBACKB.3.1 Address Signals

There are 20 bits of address on the 4.5 Mb devices with two pins reserved for future density (address) expansion. These are the 20th and 21st bits on pins 43 (36 MB) and 42 (72 MB). These bits may be left as no connects.

B.3.2 Control Signals

The pipelined ZBT SRAMs used have linear and interleaved burst mode capability. The interleaved burst mode is not used in this design. The following synchronous control signals to the ZBT SRAMs are all grounded: CKEn, CE2n and ADV/LD_N. The following asynchronous inputs are also grounded: OEn, LBOn. CE2 is pulled high. Therefore, linear burst mode is used continuously, clock is enabled continuously, new addresses are clocked immediately on the next rising edge of the clock, and the output drivers are always enabled. The ZZ pin is connected to GPIO[13], which is controlled by the iSNAP2110 when entering low power standby mode. The CEn pin is always sampled immediately when a new address is clocked.The iSNAP2110 SRAM Write Enable is active low and is connected to the R/Wn input on all the SRAMs. When SRM_WEn is low, writes will occur on any bytes that have an active low synchronous Byte Write Enable. The iSNAP2110 has eight SRAM byte write enable outputs, which are active low. Each SRAM device has four Byte Write Enables and four corresponding data bytes with parity bits. BWAn corresponds to DQA [7:0] and DQPA and so on through BWDn and DQD [7:0] and DQPD.

B.3.3 Miscellaneous Signals

The SRAM manufacturer data sheet for connection of VDD, VDDQ, and VSS should be followed. For some manufacturers, VDD pins, 14, 16, and 66, are mode pins, which should be connected to a voltage of VIH or greater; these can be connected to VDD. For some manufacturers, these are NC (not connected) pins.

B.3.4 SRAM Memory Devices

The choice of SRAM depth and width will affect the part count for the SRAM memory subsystem design. This section covers the x36 width with one device per memory array. Since the iSNAP2110 is capable of supporting 4 memory array of SRAM by four chip select outputs, a single, dual or quad memory array design is supported using either one, two, or four x36 devices.

Note: The iSNAP2110 does not prevent the designer from choosing other topologies, as the principles used in the one device per memory array may be extended.

If 256 Kb x 36 (9 Mb) device is used, which yield 9 Mb per memory array. In a dual memory array subsystem these devices will yield a total capacity of 18 Mb. In a quad memory array subsystem these devices will yield a total capacity of 36 Mb. The SRAM devices used are 100 pin TQFP, pipelined ZBT SRAMs available from companies such as Samsung and Cypress (Table B.7). These are pin-for-pin compatible replacement devices for one another.


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B.3.5 SRAM Layout Guidelines

These guidelines are specific to a single memory array (Figure B.10 on page 40) SRAM memory subsystem with one clock. Figure B.11, Figure B.12, and Figure B.13 show the SRAM memory signal constraints (clock, data, address and control, and chip select) between the iSNAP2110 and the SRAM memory chips. The reason for the specification of the branch lengths and termination values is due to the timing and signal integrity characteristics required for the SRAM interface to function properly with the given memory components and physical layout.

B.3.6 SRAM Clock

The 125 MHz clock signal, SRM_CLK should be routed first and always adjacent to a GND plane with a minimum of vias and matched trace length. When routing SRM_CLK, place the series resistor as close as possible to the iSNAP2110. Then match the rest of the trace lengths to meet the topology described in Figure B.11.

Note: SRM_DUP_CLK is not used.

Figure B.11 SRAM Clock Signal Topology

Table B.7 Recommended Control SRAM Devices

Manufacturer Device Description Package Part NumberCypress ZBT SRAM 9 Mb 2.5V VDD, 2.5VDDQ, 200 MHz,

256 Kb x 36, pipelined100 TQFP CY7C1354BV25-200AC

Samsung ZBT SRAM 9 Mb 2.5V VDD, 2.5VDDQ, 250 MHz, 256 Kb x 36, pipelined

100 TQFP K7N803649B-QC20

Segment L1 L2

Lengtha


0.25” 12.0”

33Ω

ZBT SRAMiSNAP2110

L1 L2


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SILVERBACKB.3.7 SRAM Data, Data Parity, and Byte Write Enable

The SRM_D [31:0], SRM_DP [3:0], and SRM_BW[3:0] are routed point-to-point. Lengths should be matched to within ±50 mils (Figure B.12).

Figure B.12 SRAM Data, Data Parity, and Byte Write Enable Topology

B.3.8 SRAM Address and Control

The SRAM address signals SRM_A [19:0] and the Write enable signal SRM_WE_N should match the Data and Chip Select signals lengths within ±50 mils. Each of these signals is connected to one load (Figure B.13).

Figure B.13 SRAM Address and Control Signal Topology

Segment L1 L2a

a. Driver to receiver

Lengthb

b. All trace lengths are in inches

0.5” 2.0”


Segment L1

Lengtha


1.5”


iSNAP2110

L2L1

ZBT SRAM

33Ω

iSNAP2110

L1

ZBT SRAM


GPM Interface Layout

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SILVERBACKB.4 GPM Interface Layout

The iSNAP2110 GPM interface provides data, address, and control signals to the Flash.

B.4.1 Flash InterfaceThe Flash memory contains the default configuration parameters for the iSNAP2110, as well as runtime GPP code. After reset, the iSNAP2110 starts accessing the flash to upload PCI-X register definition values and initial values for other on-chip memory elements. The Flash occupies the 2 MB at CPM_CS0n memory bank. The Flash interface is 16-bit wide.

B.4.2 UART Daughter Card Connector Interface (Optional)

The UART daughter card connector on the iSNAP2110 Reference Board is optional. It connects to a RS232 serial port interface. Only the GPM_D[7:0], GPM_A[2:0] and GPM_CS[3:2]_N are routed to this connector.

B.4.3 GPM Flash Memory DeviceA 1 Mb x16 (16 Mb) Flash memory device is used, which is equivalent to 2 MB. The Flash used is a 48 pin TSOP-48 package from ATMEL. Table B.8 shows the recommended ATMEL Flash device used with the iSNAP2110.

Table B.8 Recommended Flash Devicea

a. Flash Device is CFI compliant.

Manufacturer Device Description Package Part Number ATMEL Flash 1 Mb x 16, 70 ns TSOP-48 AT49BV162A-70TI


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SILVERBACKB.4.4 GPM Data and Data Parity

The GPM_D [15:0] should be routed as a one layer Tee (Figure B.14).

Figure B.14 GPM Data and Data Parity Signal Topology

B.4.5 GPM Address and Control

The GPM address signals GPM_A [19:0] and the enable signal GPM_WEn, GPM_OEn should be matched to the data and chip select signals lengths. GPM_A [19:0] should be routed as a single layer Tee, where GPM_A [2:0], has two loads (Flash and UART), and GPM_A [19:3] has one load (Flash). The GPM_WEn and GPM_OEn signals are also routed as a single layered Tee with two loads, Flash and UART connector. Place the series resistor as close to iSNAP as possible. Figure B.15 and Figure B.16 shows two possible topologies for GPM address control.

Segment L1 L2

Lengtha


2.0" ≤ L1 ≤ 3.5" 0.5" ≤ L2 ≤ 1.0"


N/A

iSNAP2110

L1

L2

UART (Optional)

Flash


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Figure B.15 GPM Address and Control Signal Topology – Option 1

Figure B.16 GPM Address and Control Signal Topology – Option 2

Note: The above trace lengths and matching applies to both option 1 and 2.

Segment L1 L2 L3

Lengtha


2.0" ≤ L1≤ 2.5" 0.5"≤ L2 ≤ 1.0" 0.5"≤ L2 ≤ 1.0"


N/A

2.5V

470 Ω

iSNAP2110

L1 L4L2

Option 1: Pull up strapping option = 470 ohmsThis applies to GPM_A[13]

Strap Options

Option 1

L3

Flash UART (Optional)

470 Ω

iSNAP2110

L1

This applies to GPM_A[12]Option 2: Pull down strapping option = 470 ohm

Strap Options

Option 2

L4L2 L3

Flash UART (Optional)


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SILVERBACKB.5 RGMII Interface Layout

The GE interface is based on the RGMII standard. These are 4-bits of data and a clock, which work at DDR speed. The data is latched on both the rising and the falling edges of the clock (either the Tx or the Rx clock).The RGMII interface consists of four independent segments: two Rx and two Tx ports. Each can be routed independently as long as the length and tolerances stated below (“RGMII Receive” on page 47 and “RGMII Transmit” on page 48) are followed.

Note: The PHY device should support RGMII, if not, external glue logic will be required.

B.5.1 RGMII ReceiveFor the Receive part of the RGMII, the routing length can be anything between 1.0" to 1.5", as long as all the data and clock per port are kept the same length with a tolerance of ±25 mils (see Figure B.17).

Figure B.17 RGMII Data/Clock ReceiveTopology

Segment L1

Lengtha


1.0" ≤ L1 ≤ 1.5"


iSNAP2110

L1

PHY


RGMII Interface Layout

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B.5.2 RGMII TransmitFor the Transmit part of the RGMII, the routing length can be anything between 1.2" to 1.8", as long as all the data and clock per port are kept the same length with a tolerance of ±25 mils (Figure B.18).

Figure B.18 RGMII Data/Clock Transmit Topology

B.5.3 PCI(X)The iSNAP2110 PCI/PCI-X interface is both PCI 2.3 and PCI-X 1.0a compliant. Please refer to the PCI specifications for further details.

Segment L1

Lengtha


1.2” ≤ L1 ≤ 1.8”

Matching From pin to pin (L1) one pin-pair should be = the target pin-pair ±25 mils.

iSNAP2110

L1

PHY



APPENDIX C: Optional Configuration

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SILVERBACThe various types of memories on the iSNAP2110 Reference Board are Double Data Rate (DDR) SDRAM, SRAM and Flash, with different stuff options. Various Reference Board stuff options are: Full width DDR SDRAM/SRAM or Half width DDR SDRAM/SRAM memories. The memory stuff options for DDR SDRAM and SRAM are independent of each other.

Note: The “Full Width” configuration requires a minimum of two more memory components and offers 220K IOPS across the two ports. The “Half Width” configuration can fit into a more compact Low Profile PCI footprint with less components and a lower BOM.

SDRAMThe external SDRAM serves as a data buffer for receive packets. The SDRAM also stores connection/context information and control block data used for communications between the iSNAP2110 and the Host system.

Full-width: SDRAM memory supports a minimum of 128 MB and a maximum of 256 MB memory size. The full memory data bus width is 72-bits of data and ECC that ensures data integrity.

Half-width: SDRAM option supports a minimum of 64 MB and a maximum of 128 MB memory size. The half memory data bus width is 36-bits of data and ECC.

SRAM

The SRAM is controlled by the Event/Queue Manager (E/QMgr) and is used to store the iSNAP2110 internal data structures. The SRAM type is Zero Bus Turnaround (ZBT).

Full-width: SRAM memory supports a minimum of 2 MB and a maximum of 4 MB. The full memory data bus width is 72-bits of data and ECC that ensures data integrity.

Half-width: SRAM memory supports a minimum of 1 MB and a maximum of 2 MB memory size. The half memory data bus width is 36-bits of data and ECC.

Table C.1 lists the memory requirements for HBA.

Table C.1 HBA Memory Requirement

Memory typeFull width mode Half width Mode

Min Max Min Max

SDRAM 128 MB 256 MB 64 MB 128 MB

SRAM 2 MB 4 MB 1 MB 2 MB

Flash 1 MB 2 MB 1 MB 2 MB


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FlashThe Flash memory device interfaces to the iSNAP2110 through the General Purpose Processor (GPP) and is used to store configuration parameters and runtime GPP code for the iSNAP2110. It is also used to upload PCI-X register definition values and initial values for all functional elements in the iSNAP2110 (PNs, Registers, and Flexible Logic Engine architecture (FLE)). The minimum required Flash size is 1MB.


Glossary

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ACK TCP or iSCSI Acknowledge command

ADM Receive Admission (obsolete term, usually used in conjunction with RxADM -- see “Classification Engine Rx”)

AHS Additional Header Segment – A variable-length header that optionally follows the 48-byte Basic Header Segment in an iSCSI packet.

API Application Programming Interface

ARP Address Resolution Protocol

ASQ Application Stream Queue

ASF Alert Standard Format – Defines interfaces that provide access and manageability in OS-absent environments

- B -BHS Basic Header Segment

BIST Built-In Self Test

Block ID ID passed to the Control Bus to identify a specific module for register access. (Only required for Event Queue Manager registers.)

Broadcast A transmission from one sender to all receivers

BSD Berkeley Software Distribution

- C -CIFS Common Internet FIle System (Windows NT environment standard); Format for accessing and

storing data; runs over TCP/IP.

CID Connection Invariant Data – packet header information that is constant across all frames for a particular connection (e.g., IP source and destination addresses).

CLI Command Line Interface

Command Descriptor Block (CDB)

The standard format for SCSI commands. CDBs are commonly 6, 10, or 12 bytes long, though they can be 16 bytes or of variable length.

Command Sequence Sequence of Encapsulation Engine Tx (akaTxSYN) bytes (describes a portion of a packet).

Command Stream Sequence of Encapsulation Engine Tx (aka TxSYN) transmission bytes.

Completion Entry An entry returned by a Completion Notification in the Completion Queue of the Queue Set used to send a command to the iSNAP; contains Status (S) bits which indicate if an error was present in the original command.

Completion Item Descriptor

A Queue Set entry on a Completion Queue

Completion Notification

A 16-byte entry in a Completion Queue indicating that a transaction is complete and no exception information is present

Completion Queue Used to send Completion Notifications from the iSNAP to the Host. (Part of a Queue Set that also contains a Work Queue.)

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SILVERBACKContext A structure which describes an abstract functional element of the system such as a TCP stream

or an iSCSI session.

Context ID The ID of a structure which describes an abstract functional element of the system such a TCP stream or an iSCSI session

Control Hub Performs register reads and writes to modules within the iSNAP

Control Plane Maintains the Process Control Block (PCB) for the TCP connection

CPB Connection Parameter Block

CP-ULP Critical Path and Upper Layer Protocol processing.

CRC Cyclic Redundancy Check – detects data transmission errors; see CRC Manager

CRC Manager Manages the CRC function

- D -DAFS Direct Access File System. Another format for rmote file I/O. Intendd to be much more efficient

that CIFS.

DAS Direct Attach Storage – Storage connected directly to the compute platform.

DDR-DRAM Double Data Rate DRAM

DDR-SDRAM Double Data Rate Syncronous DRAM – supports data transfer on both edges of each clock cycle

DDR-SSRAM Double Data Rate Synchronous SRAM

Device ID Code assigned to a specific device by a vendor. The Device ID for the iSNAP2100 is 0x2100 (big endian).

DFM Design for Manufacture

DFT Design for Test

Direct Address 32-bit physical address in iSNAP2100 memory.

DIrect Data Placement

Data transfer directly into the host application memory space (eliminates time consuming memory copy operations and improves system performance)

DMA Direct Memory Access

DRAM Dynamic Random Access Memory

- E -ECC Error correcting code

EEPROM Electrically eraseable programmable read only memory

EJTAG Enhanced JTAG

EO Execution Object. Classification (Rx) to Event/Queue Manager communication structure.

EPROM Eraseable programmable read only memory

ER Error Recovery

Execution Object See “EO”

- F -FC Fibre Channel

FFL Firmware Foundation Layer – abstraction layer software between upper layer applications and the hardware

FLE Flexible Logic Engine – programmable nanoprocessors which can be set to perform a variety of tasks depending on the instructions in the local control store

FLEA Flexible Logic Engine Architecture

FLID Free List ID

52 SIlverback Systems Confidential

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SILVERBACKFree List A collection of MODs used for managing the allocation and deallocation of MODs and MOs

FUB Functional Unit Bus (iSCSI)

- G -GB Gigabyte (2 to the 30th power or l,073,741,824 bytes. One gigabyte is equal to 1.024

megabytes.)

GE Gigabit Ethernet

GMAC Gigabit Ethernet Media Access Controller – transmits and receives data to/from the GMII interface

Gpbs Gigabits per second, a data transfer speed measurement for high-speed networks such as Gigabit Ethernet (a gigabit equals 1,000,000,000 bits).

GPCS Gigabit Physical Coding Sublayer – encodes and decodes the GMII interface for fiber channel.

GPM General Purpose Memory

GPP General Purpose Processor – one located on iSNAP2100

- H -HBA Host Bus Adapter; a hardware card that plugs into a computer and provides a specific interface.

The term HBA is commonly used for SCSI adapters and Fibre Channel adapters. Ethernet adapters are called network interface controllers (NICs).

HCC Host Command Controller (abbreviated HCCTL or HCC)

Header Data Splitting Separating the data and header information in a network packet and directing the information to a specific location in Host memory space.

Host Address A 32-bit or 64-bit address in the PCI or PCI-X bus space

Host Command Descriptor

Consists of both a Work Item Descriptor (WID) and an Work Item.

Host Descriptor A command block the host sends to the iSNAP that contains detailed iSNAP2100 command instructions.

HQ Host Queue

HQS Host Queue Set

- I -IB Interface Buffer – interface buffer mechanism within the WID interconnect

ICB Interconnect Control Buffer – the buffer interface on an interconnect port. The ICB provides a decoupling between the interconnect internal and port external structure

ICC iSCSI Command Context – the internal representation of a SCSI command in local DRAM. An ICC is a superset of a CDB and allows chaining and references to associated data structures

ICMP Internet Control Message Protocol

ICT In-Circuit Test

IF Interface

Index Cardinal instantiation of a structure in memory.

Initiator The originating end of a SCSI conversation (the device that requests data). Typically a controlling device such as a server or workstation. See also "Target."

INTCX Interconnect

IOCTLs I/O Control – service calls which are included in Core Services and which are used for bootup and configuration of the iSNAP device

IP Internet Protocol


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SILVERBACKIP CP The IP Control Plane component in the Host drive; consists of ARP, Route Entity, and ICMP

Entity

IP SAN Same concpet as SAN except that the communication mechanism is Internet Protocol.

IP Storage Storage devices that use Internet Protocol to transport their data.

iSCSI Internet SCSI (Small Computer System Interface), an IP-based storage networking standard for linking data storage facilities. (Parallel SCSI protocol mapped onto Internet Protocol.)

iSCSI CBD Command Descriptor Block (CBD) used to communicate with the iSNAP 2100 iSCSI service via the Host Interface (see “Command Descriptor Block”).

iSCSI CP The iSCSI Control Plane component in the Host driver; maintains local iSCSI identity and capabilities, a list of all iSCSI sessions on this system, and the identity of the remote partner for each session

iSCSI DP iSCSI Data Plane; an upper layer data plane responsible for using the TCP byte stream to send and receive iSCSI PDUs efficiently

iSCSI Interface Queue

Used to send and receive all iSCSI and TCP connection management messages for those connections in use for iSCSI and off-loaded to the iSNAP2100

ISID Initiator Session Identifier; a 48-bit number, generated by the initiator, that uniquely identifies a session between the initiator and the target. This value is created during the login process, and is sent to the target with a Login PDU.

iSNS Internet Storage Name Server; a lightweight discovery protocol that can be deployed in centralized iSNS servers, IP storage switches, and target devices. The name registration service enables IP storage devices to register their attributes and address, analogous to the Fibre Channel SNS. Can reside anywhere within the IP network.

ITT Initiator Task Tag – assigned by initiator to each iSCSI task that it issues. While a task exists,this tag must uniquely identify it session-wide.

I2C Inter-IC – A multi-master bus, which means that multiple chips can be connected to the same bus and each one can act as a master by initiating a data transfer.

- J -JTAG Joint Test Action Group of the IEEE

- K -

- L -LED Light Emitted Diode

Link Layer Interface Queue

Used to send and receive Link Layer packets

LL Link Layer

LU Logical Unit

LUN Logical Unit Number; technically, the LUN is the number that identifies a sub-element within a SCSI target device. In common usage, LUN is used to refer to the device itself, although LU (Logical Unit) is the more proper term.

LUT Look Up Table

- M -MAC or MAC Layer Media Access Controller or Media Access Control Layer. Responsible for moving data packets

across a shared channel.

Mb or Mbit Megabit


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SILVERBACKMB or MByte Megabyte

Memory Object A block in DRAM

MO Memory Object – buffer in DRAM or host memory. May contain packet data or context information; may also be customized by the customer for other data storage use.

MOD Memory Object Descriptor – a structure that maintains reference to a memory object as well as to information specific to and associated with the object

MIB Management Information Base – list of status and count event statistics maintained for both transmit and receive

MII Management Media Independent Interface Management

MMAMSI Message Signaled Interrupts. A system performance enchancement that allows status messages

to be posed to a host without a system interrupt.

Multicast A broadcast message from one sender to many receivers.

- N -NAS Network Attached Storage. A storage device that is attached to a LAN and provides file-oriented

storage to clients. Data is transferred in file formats (FIFS, NFS are common file formats).

NDMP Network Data Managment Protocol. Initially developed to facilitate tape backup operations over IP.

NFS Network File System. Allows all network users to access shared files stored on computers of different types. (Format for accessing/storing data across network created by SUN – widely used).

NIC Network interface controller

NOP No Operation A command given to the CPU that causes nothing to happen. Sometimes used as a tool to control timing-sensitive tasks.

NP Node Processor

- O -Object ID See “Index”

OLTP Online transaction processing. The request and delivery of data betwen an Initiator (server) and Target (disk) in a real-time environment.

OQ Object Queue

- P -PB Parameter Block

PCB Process Control Block; an existing component of all TCP/IP implementations; a data structure that maintains the state of a TCP connection and its relationship with other structures

PCI Peripheral Component Interface – A local 32 or 64-bit bus that runs at speeds depending on the version. PCI-x buses are 64 bits and run at up to 133 MHz.

PDU Protocol Data Unit

PER PN Execution Request

PET Packet Event Trap protocol

PHY Physical Layer

PIO Peripheral Input/Output command

PN Processor (or Programming) Node – four Processor Nodes are located on the iSNAP chip

PNC Processor (or Programming) Node Controller


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SILVERBACKPrimitive A PCI register that controls the operation of a Queue Set

PROM Programmable Read Only Memory

Protocol Machine Provides all TCP capability, including reliable delivery of all bytes (through acknowledgement and retransmission mechanisms such as timers), avoidance of network congestion (through back-off mechanisms), re-assembly of packets received out of order.

PWM Pulse Width Modulation

- Q -QSCB Queue Set Control BlockQueue List of linked or unlinked objects.

Queue Descriptor A structure that fully defines and describes a Queue

Queue Length The maximum valid value an index pointer into the queue can assume, and equals [(Queue Size)-1]. Entries of Queue size N are mapped to index values [0,..., N-1] or [,.., (queue length)]. See Queue Size.

Queue Set A pair of queues comprised of a Work Queue and its associated Completion Queue

Queue Set Entry The structure of a Work Queue and Completion Queue

Queue Set Control Block

A data structure that fully describes a Queue Set (one Work Queue and one Completion Queue); records Producer/Consumer Pointers for the Queue Set; and defines placement of the Queue Set within Host memory.

Queue Set ID A unique value that identifies a specific Queue Set.

Queue Size The size of a Work Queue or a Completion Queue measured in number of entries. See Queue Length.

- R -R2T Request to Transmit confirmation – SCSI response to a request to send command. The SCSI

initiator waits for an R2T from the target before sending the data ORReady to Transfer. R2T is sent by target when it is ready to receive data.

RAID Redundant Array of Independent Disks

RAM Random Access Memory

RCMP Remote Management Control Protocol

RDMA Remote Direct Memory Access – Mechanisms for fast, low latency data transfers between remote CPUs typically separated over a LAN.

RGMII Reduced Gigabit Media Independent Interface

ROM Read Only Memory

RPC Remote Process Communication – A mechanism that allows different Hosts to communicate with each other. (Widely used and similarly to IPC (Interprocessor Communication).)

- S -SAN Storage Area Network – a storage network dedicated to storage traffic exclusively. A network of

host computers and mass storage devices. Used to share disks and tapes with multiple hosts. Data is accessed in block mode.

SCSI Small Computer Serial Interface

SDI Serial Debugging Interface

SDRAM Synchronous DRAM

SM Session Management (or Manager) (iSCSI)

SMP Symmetric Multiprocessing


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SILVERBACKSN Sequence Number (iSCSI)

SNAP Storage Network Access Processor

SNIA Storage Networking Industry Association

SPI-3 System Packet Interface Level 3

SPI-POS SPI Packet Over SONET

SRAM Static Random Access Memory

SSRAM Synchronous SRAM

Stream A memory abstraction structure that provides a continuous stream of bytes

Stream Address A specific data stream address from which data can be read

Streaming Interface SPI-3 serial I/O interface

Summary Descriptor A Queue Set entry on a Summary Queue.

Summary Item A 4-byte entry in a Summary Queue.

Summary Queue A special queue used in conjunction with the Interrupt mechanism to identify which Queue Sets contain Completion Notifications.

Sum QID Summary Queue ID

SMBus System Management Bus – A two-wire interface through which various system component chips can communicate with each other and with the rest of the system. It is based on the principles of I2C.

- T -TAP Test Access Port

Target The receiving end of a SCSI conversation, typically a device such as a disk drive, tape drive, or scanner. See also "Initiator."

TBI Ten Bit Interface

TCP Transmission Control Protocol

TCP CP The TCP Control Plane component in the Host drive

TLV Time-Length-Value – Encoding method used for encoding optional parameters passed between the Host and iSNAP. Used by the TCP Interface.

TM Task Management

TOE TCP/IP Offload Engine – a piece of hardware that implements the TCP/IP stack, and thereby "offloads" this task from the main processor. Accelerates TCP protocol in special purpose hardware. There are two types: Partial Offload, which typically handles only the Fast Path, in order packets; and Full Offload, which manages out-of-order and missing packets. (This hardware may be a custom ASIC or a network processor with firmware.)

TSID Target Session Identifier, a 16-bit number, generated by the target, that uniquely identifies a session between the initiator and the target. This value is created during the login process, and is sent to the initiator with a Login Response PDU.

TTC TCP Timing Controller

TTQ TCP Transmit Queue

TTT Target Transfer Tag (iSCSI)

- U -UART Universal asynchronous receiver transmitter

UDP User Datagram Protocol – runs on top of IP networks (direct method for broadcasting messages)

ULP Upper Layer Protocol


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SILVERBACKUTP Unshielded Twisted Pair

- V -Vendor ID Code assigned to the vendor who created the device.

VFS Virtual File System

Virtualization Automation of functions in the storage infrastructure that simplifies the management and operation of storage devices.

VI Virtual Interface – A low latency, high bandwidth protocol that allows different hosts to communicate with each other.

VLAN Virtual LAN (IEEE 802.1Q/p) – allows stations on disparate networks to appear as if they are all members of the same LAN

- W -WIE Work Item Entry – same as a WID

Work Item (WI) The Work Item describes the service the Host requests of the iSNAP and the parameters for the service request. The last 8 bytes of the WI contain the Base Address and Length to which the WID points.

Work Item Descriptor (WID)

A 16-byte Queue Set entry in a Work Queue sent to the iSNAP. Contains the iSNAP data structures exchanged between the Host and the iSNAP. Includes a pointer to the last 8 bytes of the Work Item.

Work Queue Used to send requests from the Host to the iSNAP; contains a WID of 16 bytes with a pointer to a Work Item.

- X -XTR Designator for iSNAP in the iSNAP code.

-Y-

- Z -ZBT Zero Bus Turnaround (133 MHz)


iSNAP®2110 Reference Boa

Index

CONFIDENTIA

L

SILVERBACK

AActivity indication 5AK29 pin 12

BBill of materials 27BIST LED 5Board interfaces 7boundary-scan chain 12bracket 16

CCircuit areas 6Circuitry and routing 21Configuration options 26Connector

PCI 11Context buffer memory 5Control memory 5Control SRAM 9DDDR SDRAM 8Dimensions 2, 14

EEthernet interface 7FFeatures 5Flash memory 5Form factor 11

GGE interface pin assignments 16Gigabit ethernet interface 7HHardware specifications 6Height 2

II/O voltage 11input clock 21iSNAP2110

processor. 2system development kit 2

JJTAG 5JTAG test mode 12JTAG_MOD 12JTG_TCK 12JTG_TMS 12JTG_TRSTn 12

LLED indicator 5, 25

activity 25GPIO 25link 25

Length 2Link indication 5link status LEDs 26

MMaximum heights 14Memory interface

DDR SDRAM (Global Memory) 8Flash (general purpose memory) 10GPM 10ZBT SRAM (control memory) 9

Multifunction support 5Oonboard memory 5Operating temperature 2operational status 25output clock 22

rd Design Guide Silverback Systems Confidential 59

CONFIDENTIA

L

SILVERBACK

PPCI

connector 11frequencies 11interface 11multi-function 12

physical characteristics 14pin-pair 32

target pin-pair 32Ports

Ethernet 5Power

consumption 2Product overview 2RRelated publications 2RGMII 5RJ-45 connectors 7SSystem requirements 2Ttarget pin-pair 32target-pin-pair

delta 32group of pin-pairs 32tolerance 32

TD0 12TD1 12

VVoltage

Supply 11

60 Silverback SystemsConfidential iSNAP®2110 Reference Board Design Guide

isnap2110 reference board_design guide_w

Documents

silverback web site

silver b

c o n fid en tia

design package

minor change

registered trademarks

section table

sram memory devices