irjet-discover and remove the local, bridging errors using fault tolerance technique

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056

Volume: 02 Issue: 05 | Aug-2015 www.irjet.net p-ISSN: 2395-0072

© 2015, IRJET ISO 9001:2008 Certified Journal Page 356

DISCOVER AND REMOVE THE LOCAL, BRIDGING ERRORS USING FAULT

TOLERANCE TECHNIQUE

S.Palaniyappan1, I.Ilayaranimangammal2

1Assistant Professor, Dept of EEE, Dhanalakshmi Srinivasan Institute of Research &Technology, Tamil Nadu, India 2Radio Jockey, Madurai Rainbow FM 103.3Mhz, All India Radio, Tamil Nadu, India

---------------------------------------------------------------------***---------------------------------------------------------------------Abstract –To disclose and removal the errors in the

Flow chart of all the electronic systems using the tool

RAPTOR. By analyzing the characteristics of Problem

Analyzing Diagram and structured flowchart, and a

structure identification and coding algorithm are put

forward for structured flow diagram and PAD. Finally a

integrated development platform is developed using

such algorithms, including flowchart modeling, code

automatic generation Fault tolerance technique using

TMR for exposure and expulsion the soft errors in the

digital systems. Faults are exposing and eliminated

without interrupting the normal functioning of the

circuit. Single point of failure, is removal and

implemented as a fault tolerant using a Triple Modular

Redundancy (TMR). Conventional lockstep scheme uses

duplication with comparison (DWC), the presence of

fault is detected, but it fails to indicate the location of

fault which is overcome in enriched lockstep by triple

modular redundancy (TMR). TMR technique

incorporates both temporary and permanent faults.

The new intensifying lockstep scheme requires

significantly shorter recovery time than conventional

lock step. It uses significantly less number of slices.

Keywords– structured Flow chart, Fault tolerance, Single-Event Upset (SEU), Triple Modular Redundancy (TMR), problem analysis diagram, integrated development platform.

I INTRODUCTION Flow chart describes the control logic of a program by top-down process. For PAD (problem analysis diagram),it has the capability of top-down and left-right. So we can say if flowchart is a one-dimension chart, then PAD is a two-dimensional chart[1]. The basic idea of redundancy is to implemented multiple copies of the same circuit, and compare the outputs of each circuits. Disparity in these outputs indicates the occurrence of an error. Redundancy technique can be implemented at various levels such as circuits, systems etc. This process of switching is a simple

process when both the designs meet the system restrictions identically [2]. Logic paths in between the flip-flops are composed of hard-wired, non-reconfigurable gates. Hence they are immune to SEUs. A fully fault tolerant system has the ability to detect and then corrects the hardware occurrence and return the system to its normal functionality. An optimal design will minimize the amount of extra logic required to detect and then correct the occurrence of the fault An extreme temperature change is one of the reasons in which fault tolerance is necessary for devices operating in harsh operating environments, as found, for example, in space and military applications [13] [6].In this paper section II focus on single-event upsets (SEU) and types of upsets. Then SEU mitigation techniques were discussed. In section III proposed method IV, the experimental & results are discussed V. Finally, the paper was concluded in section

2. MITIGATION TECHNIQUES It is a process of applying design techniques to strengthen the functional integrity of the circuit, and protect it from the effect of any Single Event Upset. Fault-tolerant methods [6], [8] used to mitigate logic errors in FPGA based on redundancy technique are as follows. RAPTOR for detect & correct the error in the flow diagram of digital systems. Duplication with Comparison (DWC) for detecting faults and Triple Modular Redundancy (TMR) with majority voter for masking fault.

2.1 Testing the Flow Chart of Duplication with Comparison Technique

RAPTOR Tool is used to verify the DWC flow chart, each symbols are checked whether its suitable or not then This tool is used to all the digital circuits. This step is very important in testing field. Its beginning step of testing.

2.2 Algorithm for DWC Technique Start the circuit design. Give input to the digital systems (Both the

circuits are accept same input value). Check both the circuit outputs, If output is mismatching its Faulty else Fault

free.




Simulate the flow chart & evaluate each symbol.

Run the flow chart.

2.3 Flow Diagram of DWC Technique

Fig-1: Flow

chart for DWC

Technique

2.4 Design the block diagram of Duplication with Comparison Technique

Duplication with Comparison (DWC) is a detecting technique, in which the circuit to be protected is replicated twice and the results produced by the original circuit and the outputs of replicated circuits are compared to detect faults is given in figure 2.2. Two identical circuits ADDER1 and ADDER2 receive the same inputs and simultaneously execute the same instructions, their results are compared step by- step at each clock cycle. Circuit ADDER2 generates the reference results to be compared against those of ADDER1 that provides the system output. Basically, DWC is able to detect but not to correct errors and also fails to indicate the fault location, since it cannot point out the faulty circuit. However, it could be capable to tolerate temporary faults, provided that it is supported by some re-execution procedure. In case of FPGA implementation, the system

needs also to be reconfigured to recover correct functionalities.

OUTPUT MISMATCHING Fig -2: Duplication with Comparison (DWC)

2.5 Testing the Flow Chart of Triple Modular Redundancy Technique

RAPTOR Tool is used to verify the TMR flow chart, each symbols are checked whether its suitable or not then This tool is used to all the digital circuits. This step is very important in testing field. its beginning step of testing. To detect and correct the errors in the Flow diagram of all digital systems using RAPTOR. By analyzing the characteristics of PAD and structured flowchart, and a structure identification and coding algorithm are put forward for structured flow diagram and PAD. Finally a integrated development platform is developed using such algorithms, including flowchart modeling, code automatic generation.

2.6 Algorithm for TMR

Start the circuit design. Give input to the circuits (All three

circuits are accept same input value and feed to a common voter).

The Voter takes a majority vote to provide the correct output.

This Flow Diagram is draw by RAPTOR Tool.

Simulate the flow chart & evaluate each symbol.

Run the flow chart.

OUTPUT 1

ADDER 1 ADDER 2

OUTPUT 2

COMPARE

INPUT

Start

Two Systems

Get

input

1010

Sys1=

Sys2

Fault

free

Faulty

End

Yes No



© 2015, IRJET ISO 9001:2008 Certified Journal 58

2.7 Flow diagram of TMR Technique

Fig-3: Flow chart for TMR Technique

2.8 Design the block diagram of Triple Modular Redundancy Technique

Triple Modular Redundancy (TMR) is the most reliable safeguard for total device failure as it rapidly detects and corrects SEUs.Three copies of the same circuit are connected to a “majority voter” which is used to obtain the fault free output is shown in figure 2.4 This method works as long as all the faults are confined to one of the redundant blocks. The latency will be increased because of the voter in the circuit’s critical path.

Fig-4: Triple Modular Redundancy (TMR)

TMR has a capability to protect both sequential and combinational circuits. A more efficient implementation of the TMR is focused in the sensitive logic, for example the memory cells to be protecting again SEU . It operates with the main aim of removing all single points of failure from the circuit. Each set of

the triplicates circuit has its own set of inputs, to avoid errors occurring due to propagation of wrong inputs.

2.9 Majority voter circuit

A

B V

C

Fig-5: Majority voter circuit

The majority voters perform a very important task in the TMR approach, because they are able to block the effects of an upset through the logic at the final output in figure 4.3. In this way, the voters can be placed in the end of the combinational and sequential logic blocks, creating barriers for the upset Table 1: Majority voter truth table

3. ENHANCED LOCKSTEP ARCHITECTURE The basic lockstep scheme [7] uses the realization of DWC at the processor level. Unfortunately, it can only detect errors without indicating the faulty module. In order to alleviate this limitation, the new Enhanced Lockstep scheme is shown in Figure 3, which provided with the mean to identify the faulty circuit. It allows continuing the execution with the remaining fault-free circuit. This technique involves with the operation of two identical circuits with synchronized clocking. A mismatching between the output values of the circuit indicates the occurrence of SEU. Recovery actions such as reinitializing and switching to safe mode are implemented. Figure 7

INPUT OUTPUT

A B C V

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

INPUT

MAJORITY VOTER

ADDER 3

ADDER 2

ADDER 1

OUTPUT

Start

Three Systems

Get

input0100

End

Majority voter

Output




shows the architecture of the fault-tolerant system, whose two main blocks are Enhanced Lockstep scheme and the fault-tolerant (FT) Configuration Engine. Error Correcting Code (ECC) is used for detection and identification of single and double-bit errors in the given data.The reset input may be tied to logic 0 for free-running SEU detection and correction in the circuit that do not require access to the configuration memory during normal operation.[12] Two identical circuits ADDER1and ADDER2 and are the most essential part of the Enhanced Lockstep scheme. Their outputs are identical during fault-free functioning, any mismatching indicating error(s). If there is an error indication, the output signals of the PLB bus and the peripheral outputs are compared by the Comparator/Multiplexer (COMP MUX). If there is a mismatching occurs between any of the two circuits, a signal will be generated. When an error is detected between the circuits, since all the resources of two circuits are blended together it, there is no possibility of differentiating the faulty circuit.

Fig-6: Enhanced Lock Step Scheme

In order to distinguish the faulty circuit, two blocks are used are the Comparator (COMP) and Multiplier (MUX). COMP that indicates any mismatch between the outputs Out1 and Out2 of CUT1 and CUT2 (containing the PLB and final output signals). [14] And the MUX, which connects one of the circuit to the system output, so that if one of them is reported to be faulty, the other is switched on. The switching is an atomic operation executed in one clock cycle. Once the error is localized by the FT Configuration Engine the affected processor is reconfigured to eliminate its configuration upset. Synchronization process is used for the newly reconfigured one to the same state as the correct one, thus enabling them to continue executing the same task in lockstep again. The recovery process of the Enhanced Lockstep scheme is handled by the Context Recovery Block (CRB).

4. RESULTS& IMPLEMENTATION

4.1Result of Duplication With Comparison Flow Chart

Fig-7: Result Verification of Duplication with Comparison

Flow Chart

RAPTOR Tool is used to verify the flow chart, each symbols are checked whether it’s suitable or not then this tool is used to all the digital circuits. This step is very important in testing field. It’s beginning step of testing. To detect and correct the errors in the Flow diagram of all digital systems using RAPTOR. Start the system design. Give input to the circuits (Both the circuits are accept same input value).Check both the circuit outputs if output is mismatching its Faulty else fault free. This Flow Diagram is draw by RAPTOR Tool. Simulate the flow chart & evaluate each symbol. Run the flow chart and then finalize which one is faulty system.

4.2Result of Detecting the Transients Faults

Fig-8: Detect the Transients faults

Two identical circuits ADDER1 and ADDER2 receive the same inputs simultaneously execute the same instructions, and their results are compared step by-step at each clock cycle. ADDER2 generates the reference results to be compared against those of ADDER1 that provides the




system output. DWC is able to detect but not to correct errors, because it cannot point out the faulty processor and it has capable to tolerate temporary faults, provided that it is supported by some re-execution procedure. Here both the circuits are fault free.

4.3 Result of Triple Modular Redundancy Flow Chart

Fig-9: Result Verification of TMR Technique Flow Chart by

Raptor RAPTOR Tool is used to verify the TMR flow chart, each symbols are checked whether its suitable or not then this tool is used to all the digital circuits. This step is very important in testing field. Its beginning step of testing. To detect and correct the errors in the Flow diagram of all digital systems using RAPTOR. Start the system design. Give the binary input to the circuits (All three circuits are accept same input value and feed a common voter).The Voter takes a majority vote to provide the correct output. This Flow Diagram is draw by RAPTOR Tool. Simulate the flow chart & evaluate each symbol .Run the flow chart then finally report which one is faulty .

4.4 Result Of Detecting and Correcting The Transients Faults

Fig-10: Detect and correct the transients faults

The TMR scheme uses three identical logic blocks performing the same task in tandem with corresponding outputs being compared through majority voters. The majority voters perform a very important task in the TMR approach, because they are able to block the effects of an upset through the logic at the final output. The triple modular redundant ripple carry adder (TMR-RCA) is used as the reference circuit. This adder is the simplest approach for both detecting and correcting faults. Using the ripple carry adders is shown in Figure 3. The technique involved in information redundancy includes the use of error-correcting codes. Fault occur in any one of the adder is compared with the fault-free adders, in order to indicate the faulty one.

5. CONCLUSION Conventional lockstep scheme uses duplication with comparison (DWC), the presence of fault is detected, but it fails to indicate the location of fault which is overcome in enriched lockstep by triple modular redundancy (TMR).Enhanced lockstep scheme uses triple modular redundancy (TMR) as a fault tolerant to detect and eliminate transient faults. It reduces both area and time consumption considerably. The errors can be reduced, performing the previous technological considerations, to sets of bits which are candidate to flip at the same time. The performance and efficiency of the circuit can be improved and the simulation time is reduced.

REFERENCES [1] Hung-Manh Pham, Student Member,IEEE,Sebastien Pillement,Member,IEEE,and Stanislaw J.Piestrak,Member,IEEE “Low-Overhead Fault-Tolerance Technique For A Dynamically Reconfigurable Softcore Processor” IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 6, JUNE 2013 [2]Nicholas, Kiamal Pekmestzi, and Dimitris Gizopoulos, “Efficient Memory Repair Using Cache-Based Redundancy” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, JANUARY 2013 [3] Ioannis Doudalis, James Clause, Guru Venkataramani, , Milos Prvulovic, and Alessandro Orso, “Effective and Efficient Memory Protection Using Dynamic Tainting” IEEE TRANSACTIONS ON COMPUTERS, VOL. 61, NO. 1, DECEMBER 2012 [4] Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, “A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems” IEEE EMBEDDED SYSTEMS LETTERS, VOL. 3, NO. 3, SEPTEMBER 2012 [5] Abate F, Sterpone L, Lisboa C A, Caron L, and Violante M, “New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA




Embedded Processors”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 4, AUGUST 2011 [6] Brian Pratt, Michael Caffrey, James F Carroll, Paul Graham, Keith Morgan, and Michael Wirthlin, “Fine-Grain SEU Mitigation for FPGAs Using Partial TMR” IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 4, MAY 2010. [7] Keith Morgan, Michael Caffrey, Paul Graham, Eric Johnson, Brian Pratt, and Michael Wirthlin, “SEU-Induced Persistent Error Propagation in FPGAs”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 52, NO. 6, DECEMBER 2009. [8] Heather Quinn, Paul Graham, Member, and Brian Pratt, “An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 6, DECEMBER 2008. [9] Ichinomiya Y et al., “Improving the robustness of a soft-core processor against SEUs by using TMR and partial reconfiguration”, IEEE Annu. Int. Symp. On Field-Programmable CustomComputing Machines, AUGUST 2008 [10] Lanuzza M., “An efficient and low-cost design methodology to improve SRAM-based FPGA robustness in space and avionics applications,” Proc. Int. Workshop on Reconfigurable Computing Architectures, Tools and Applications, Lect. Notes on Computer. Sci., vol.5453, pp. 74–84, December 2007. [11] Liu S F et al., “Increasing reliability of FPGA-based adaptive equalizers in the presence of single event upsets,” IEEE Trans. Nucl. Sci., vol. 58, no. 3, pp. 1072–1077, SEPTEMBER. 2007. [12] Alderighi M et al., “Evaluation of single event upset mitigation schemes for SRAM based FPGAs using the FLIPPER fault injection platform,” in Proc. 22nd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, Rome, Italy, 26–28 Sep. 2007. [13] Baumann R, “Soft Errors in Advanced Computer Systems,” in IEEE Design and Test of Computers. New-York-London: IEEE Computer Society, vol. 22, pp. 258–266, May–June 2006. [14] Dutton B and Stroud C, “Single event upset detection and correction in Virtex-4 and Virtex-5 FPGAs,” in Proc. ISCA 24thInt. Conf. on Computers and their Applications (CATA 2009), New Orleans, Louisiana, USA, 8-10 pp. 57–62. Apr. 2005

BIOGRAPHY S.PALANIYAPPAN obtained Diploma Electrical and

Electronics Engineering in the year 2006 and got District first from MIET Polytechnic College and his Bachelor degree in Electrical & Electronics Engineering from A.C College of Engineering and Technology Karaikudi in the year 2009 and Master degree in Power Systems Engineering from University College of Engineering, Anna

University Chennai, BIT Campus Tiruchirappalli in the year 2013. He is an Assistant Professor with the department of Electrical & Electronics Engineering at Dhanalakshmi Srinivasan Institute of Research

&Technology in Perambalur, Tamil Nadu India. He had published International Journal in IEEE explorer. He got Best paper award for International conference and also presented IEEE International Conference, National Conferences. His research area includes the application of soft computing techniques in power system and smart grid challenges. I.ILAYARANIMANGAMMAL received her B.E degree in

Engineering from Sethu Institute of Technology, Kariapatti, Virudhunagar Dist, and Tamil Nadu in 2010. and Master degree in VLSI Design from

Shanmuganathan Engineering College, Thirumayam, Pudukkottai Dist, Tamil Nadu in 2014. She is former Lecturer with the department of Electronics and

Communication Engineering in Sudharsan

Engineering College at Pudukkottai District, Tamil Nadu. Now she is a Radio Jockey in Madurai FM rainbow 103.3 MHz, All India Radio. She has published International Journal in IEEE explorer and presented IEEE International Conferences and National Conferences. Her research interest is Testing domain, Software tool development areas.

irjet-discover and remove the local, bridging errors using fault tolerance technique

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