ip integration from transistor to package level
TRANSCRIPT
IP integration
from Transistor to Package level
Speaker name : Philippe Galy
TRD/CCDS/PIMDS/IP-infrastructure
1
CONSEIL D’ORIENTATION DU GIP CNFM
StMalo 28/11/2012
28/11.2012 Ph Galy JP CNFM 2012
Outline 2
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
28/11.2012 Ph Galy JP CNFM 2012
3
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
28/11.2012 Ph Galy JP CNFM 2012
Context 4
IP integration question of scale factor
4
System Assembly Manufacturing Design
IP or Macro IP is a complex design
Integration need to be compliant to package level
Different solutions are offered for our
customers to success
28/11.2012 Ph Galy JP CNFM 2012
Context 5
Complex Process flow
Complex facilities
Etching ; Plasma, RIE , Implantation …
Flavors of substrate : Bulk or PD/FD SOI
Manufacturing context
200 – 300 mm Wafer Human
Machine
28/11.2012 Ph Galy JP CNFM 2012
Context 6
Thin & Thick oxide gate transistor
High K metal gate
Different topologies ; sub nanometer
Scale down of transistors & metal layers
Flavors of substrate : Bulk or PD/FD SOI
Technology context : FEOL
FD SOI
gate
Thin Silicon film
Bulk
gate
Silicon Substrate
Planar MOSFETs
Gordon Moore
20 nm
14 nm
10 nm and beyond
28/11.2012 Ph Galy JP CNFM 2012
Context 7
Stack metal : M1 to M11
Low K inter dielectric
Complex Stack & Via structure
Technology context : BEOL
Metal Stack
(BEOL)
Gate stack
Sub-Nano
MOS transistor
(FEOL)
28/11.2012 Ph Galy JP CNFM 2012
Context 8
Dig/ ANA/ RF IP
LOW leakage IP
GO1/GO2 IP transistors
Multi Applications
1 000 000 000 XTors
High Density Memory
High Density Blocks
Complex IO ring
IP context
SOC view
28/11.2012 Ph Galy JP CNFM 2012
Context 9
9
90/80 nm
2004-2007
65/55 nm
2005-2010
45/40 nm
2008-2011
32/28nm
2009-2014
20nm
2012-20xx
Mtr
50
100
200
500
1000
3CPU’s, 250MHz,
~3W,
Hierarchical Design,
Wire bonding
5 CPU’s, 500MHz
~3-4W, WB,
FE integration
8 CPU/GPU’s, 1-2GHz,
~3-7W, FC,
system
on single package
6 CPU/GPU’s, 700MHz,
~3-6W, WB,
Flip-Chip,
System Co-design
10 CPU/GPU’s,
>2GHz, ~3-7W,
Flip Chip / 3Dstack
Heterogeneous
PMIC
FEnd
Apps
Network
Dig/ ANA/ RF SOC
LOW power / FAST SOC
Multi processor
Multi Applications
1 000 000 Trs
SOC context
28nm FDSOI Available
- 24 nm possible
- Back Bias
- Poly Bias
- Co integration (Bulk + FD SOI)
28/11.2012 Ph Galy JP CNFM 2012
Context 10
Dig/ ANA/ RF
Multi Dice
Multi connections
Thermal behavior
Package context
Design/SOC Assembly Final Package
Backside view
28/11.2012 Ph Galy JP CNFM 2012
Context 11
Dig/ ANA/ RF SOC
Power management
Multi Applications
Multi Chips
Multi protocol
Multi standard
Multi environment
Robust solution
Full Plat-Form solution
System context
28/11.2012 Ph Galy JP CNFM 2012
12
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
28/11.2012 Ph Galy JP CNFM 2012
ESD event : True life 13
At least four standards are used to qualify a solution
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
Human Metallic Model (HMM or Gun)
5
10
15
20
0 20 40 60 80 100 120 0
t ns HBM 4 kv
MM 200V
HBM IEC 8kV contact
CDM 500V
A 30
Comparison
HBM, CDM, CDM & IEC Stress
Different energy stresses: 1A, 2A & 30A
Different stress durations: 1ns to 100ns
28/11.2012 Ph Galy JP CNFM 2012
ESD Challenges 14
Chip context Digital/Analog/RF and multi powers/Dice
Thin & Thick oxide gate transistor
Scale down of transistors/metal layers
Low power / Fast signal
Multi balls (1000) / multi dice/huge die size (100mm2)
Flavors of substrate : Bulk or PD/FD SOI
14
ESD context Different energy stresses: 1A, 2A & 30A
Different stress duration: 1ns to 100ns
One or Two pins stressed
Can occurs all along the chip lifetime
ESD Co-design Challenge
Provide efficient power devices
Provide efficient trigger circuit
Optimize : Silicon area, leakage, parasitic capacitance
Address all ESD standards for all IPs/Ios (RF/ANA/Dig)
Develop Robust & reliable ESD strategy for SOC (IO+core)
Take into account process discrepancy
ESD Tools/Checkers Challenge
Checker for IP/IO & core IPs
Pertinent /Robust/portable checkers
Perform a Robust Design
thanks to checkers
10 000 000 instances & more CCDS
28/11.2012 Ph Galy JP CNFM 2012
Device Solutions 15
Different devices are required to address this challenge
Power device as primary protection
Fast device as secondary protection
Standard device as trigger element
Advanced device as new solution
Optimize silicon area
Optimize signal integrity
Don’t forget robust Metal & Via connection
(not discussed here)
28/11.2012 Ph Galy JP CNFM 2012
Device Solutions 16
R
TC
(Body + gate bias)
0
0.5
1
1.5
2
2.5
3
3.5
4
0.E+00 5.E-07 1.E-06 2.E-06 2.E-06
Vo
lta
ge
(V
)
Time (s) 0
0,02
0,04
0,06
0,08
0,1
0 1 2 3 4
Curr
ent
(A
)
Voltage (V)
Single BIMOS
Dynamic Response
Quasi-static Response
Design solution to catch :
- Dynamic ESD event
- Quasi Static ESD event
Zener !
BIMOS Tr = Bipolar + MOS Effects (Theoritical view)
Example : BIMOS transistor
28/11.2012 Ph Galy JP CNFM 2012
Device Solutions 17
Example : Triac power device
Gate N
A2 A2
A1 A1
Gate N
SC
R#
1
SC
R#
2
Classic Equations
(*) Equation de Poisson
(*) Equation de continuité
(*) Equation de transport
(*) Equation de la chaleur
saN
dNnp
pnq
),(2
pnUpn
pnq
pnt
,,
),(
1),( J
),(,),(,),(),(, pnpnD
pnqpnpn
pnqpn J
TpnpnTpnkpnpnpn
qpn ),(),(,,),(),(, J
TTpnt
TSipC
Si Q)(
),(
EJ
Basic schematics
0
0,5
1
1,5
2
0 1 2 3 4 5 6 7 8
Voltage (V)
Cu
rre
nt (
A)
R_GN=100 Ohms
R_GN=1 Ohm
R_GN_T=100
OhmsR_GN_T=1 Ohm
28/11.2012 Ph Galy JP CNFM 2012
Device Solution 18
N+
N+
P+
P+
Pw N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
N
N
P
P
Pw
Matrix Cross Section Sub Matrix
A1 A2 A2
Nwell
Pwell Pwell Pwell
P+ N+ P+ N+ P+ N+
Example : Beta Matrix
Extraction
point
0
1
1.5
0 2 4 6 8 10
0.
5
Isotherm IV response
Voltage (V)
Cu
rre
nt
(A)
3D TCAD Current density extraction
Power device
Concept
3D TCAD
results
28/11.2012 Ph Galy JP CNFM 2012
Device Solution 19
Example : Beta Matrix & HC
Cross section Zoom In
d
dtf (k,r,t )
tf (k,r,t )
d
dtkk f (k,r,t )
d
dtrr f (k,r,t )
t(n, p) gi r (n, p) giu n,p (n, p)
F
hkgi giCi
),(
,,
,, ,),(
2
31
pn
pnpn
Tpnpnq
wUUpn
tq pn
EJS
pnpnpn Upn
tq ,),(, ),(
J
pnpn Cpnpnt
,,),(),( vr
“Hot”
Equations set
3D TCAD study
FA
28/11.2012 Ph Galy JP CNFM 2012
Trigger Solution 20
Trigger Circuit :
Dynamic detection event in the ESD range time
Static detection event through threshold
Both detection
Optimize silicon area
Fast response
Low energy behavior
Designed for the ESD window
28/11.2012 Ph Galy JP CNFM 2012
ESD IP Solution 21
R
C
R
C
SC
R +
SC
R
MO
SS
WI+
dio
de
SCR SCR
Mosswi
R&D differentiation : Before & After IP integration
Before After Before After
28/11.2012 Ph Galy JP CNFM 2012
ESD IP Solution 22
Example : HBM+MM+CDM+HMM
Power device + Dynamic Trigger
Modular approach
P2
P1 D1
Dual SCR
R
R
Ele
men
tary
Mo
du
le
IO IO
VDD2
VSS1
VDD1
VSS2
IO IO Clamp
VDD1
Clamp
VDD2 T C
T C
T C
T C
T C
T C
T C
T C
Ne
w E
SD
ne
two
rk
Silicon measurements
28/11.2012 Ph Galy JP CNFM 2012
ESD protection strategy 23
ESD Gun
Board/ Chip context Digital/Analog/RF and multi powers/Dice
Thin & Thick oxide gate transistor
Multi chips / multi dice / multi balls
Flavors of substrate : Bulk or PD/FD SOI
External connectors/ PCB routing
23
ESD GUN context
Energy stress: 30A at least
Stress duration: 1ns rise time to 100ns
Two pins stressed contact or air discharge
Power off & Power on
Standard : IEC 61000-4-2
ESD Gun Co-design Challenge Provide efficient power devices
Provide fast trigger circuit
Optimize : Silicon area,
leakage,
parasitic capacitance
Address all ESD standards (HBM/MM/CDM)
Avoid LU
28/11.2012 Ph Galy JP CNFM 2012
ESD protection strategy 24
Field plate
CDu
t
RTE
ST
1W
RAR
C
LTEST
RCHR
G
1GW
VCD
M
Ground plate
CPM
Time [sec]
Curr
ent [A
]
Development of package model
Evaluation of protection
devices in time range of
CDM
Evaluation of full CDM
protection strategy on IO
Development of tools devoted for CDM study
1 2 3 4 Identification of the main phenomenon involved during stress Static CDM
check on IP
Dynamic CDM
Check on IP block
Basic schematic of the problem to simulate
Kelvin Pad
frame for
VFLTP &
VF TCS
• Pogo pin contribution
• Package contribution
• Metal contribution
• Design contribution
• Layout contribution
• Substrate contribution
ESD CDM
28/11.2012 Ph Galy JP CNFM 2012
ESD protection strategy 25
ESD CDM
Extract #1
@ 6 ps Extract #2
@ 249 ps
Extract #3
@ 326 ps Extract #4
@ 512 ps
Global view of extractions & activities . Link with TDDB
R&D collaboration
Macro IP
28/11.2012 Ph Galy JP CNFM 2012
26 CDM silicon signatures
CDM silicon signatures & physical phenomenon :
Typical CDM silicon signatures identified
Physical mechanism : Snapback and/or dielectric breakdown
Examples of signatures see below
10-Jan-13
Snapback
Snapback
Multi Holes in gate Hole in gate (Soft fail)
Hole in gate
Drain side
Tong effect = Hole +
partial Snapback
Substrate current
Filament (hard fail) Backside view
Failure Analysis Item
&
associated expertises
28/11.2012 Ph Galy JP CNFM 2012
ESD RF & Beyond ! 27
FOCUS
Best Solution
Local clamp
STM C65 SCR+Diode
(15µm x 15µm)
Ref : Dimitri Liten ICICDT 2010
How to reach the ESD/RF targets
2KV HBM for 20 GHz bandwidth at least
400 MHz 30 GHz
Our target
28/11.2012 Ph Galy JP CNFM 2012
ESD RF & Beyond ! 28
∂µ Fµν = - 4п Jν
Fµν = ∂µ A
ν - ∂ν A
µ
Aν = (φ,A), Jν = (ρ,J)
∂ν Aν = 0
Jn = q μn n (E + vn × B) + k T μn ∇. n
Jp = q μp p (E + vp × B) – k T μp ∇. p
E = -∇φ - ∂t A , B = ∇× A
∇· J = - ∂t ρ + U
J = σ.E + μH J × B
Ma
xw
ell
Sili
co
n
Quadri vectors :
Lorenz gauge :
Faraday tensor :
Maxwell equation:
Vectors :
Transport equations :
Coupled with Lorenz force
Continuity equation :
Me
tal
Transport equation : Coupled with Lorenz force
R&D collaboration
28/11.2012 Ph Galy JP CNFM 2012
ESD RF & Beyond : Minimize parasitic Capa 29
FEOL+BEOL extraction Bandwith calculation
BEOL
FEOL
FEOL + BEOL parasitic capacitance calculation thanks to coupled equations for local
clamp solution
It’s possible to extract E, B fields into the structure (@10GHz)
E(V/m)
FEOL+ BEOL capacitance
= 80 fF
28/11.2012 Ph Galy JP CNFM 2012
ESD RF & Beyond ! 30
Best Solution
Local clamp
STM C65 SCR+Diode
(15µm x 15µm)
400 MHz 30 GHz
Our target
New target
C40,32 demonstrators
How do to ?
28/11.2012 Ph Galy JP CNFM 2012
Beyond : Embedded protection in propagation line 31
Jn distribuition
in Si substrate
E distribution Hdistribution Topology
RF
Measurements
Model Measure
28/11.2012 Ph Galy JP CNFM 2012
32
Full 3D ESD device Current density Time Evolution
Metal behavior R&D collaboration
28/11.2012 Ph Galy JP CNFM 2012
33
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
28/11.2012 Ph Galy JP CNFM 2012
34 Package & 3D connection
34
SOP (Small
Outline Package)
QFP (Quad
Flat Package)
BGA (Ball Grid Array)
PGA (Pin Grid Array)
Pin number
QFN (Quad
Flat
No-leads) 500 pins
1500 pins
48pins
64pins
200pins
1 000 pins
16pins DIL (Dual
In Line)
Complexity of package increases with technology node !
Several layers, material …
SOC, SIP ….
28/11.2012 Ph Galy JP CNFM 2012
35 SIP 3D interconnect
Example of contribution on signal Integrity
Cu pillar, Ball , TSV 3D interconnect
Multi substrate package layers
Interposer …..
35
32 nm stacked
on 65 nm Die
TSV
TSV
40GHz
28/11.2012 Ph Galy JP CNFM 2012
Transient domain 36
• DDR application
• To include BDPROG IO spice netlist
• Load => Memory + Memory Package (POP configuration)
• Bump RDL impact
IO:BDPROGMOBLPDDRSCARUDQP_URISO_SF_1V2_D
Q_FC_LIN_PHY
Zout=34Ω
ASRCN<6:0> = 0101000
ASRCP<6:0> = 1010101
Spectre models – Typical corners
output_package
Package
(SDRDQ2) IO Spice Netlist
X p
F
Freq = 500MHz
Vhigh = 1V
TL model
MSub
W,L input
Vs
Bump to RDL impact
28/11.2012 Ph Galy JP CNFM 2012
37
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
28/11.2012 Ph Galy JP CNFM 2012
38 IP integration with Flexframe Tool
Synchronicity
ANA
DIG
SUPPLY
STAND
.
IP IO Offer
Special
Others
…
gnde
esdsub
e s d s u b
v d d e
g n d e
Mto
p IO
pin
LB
IO
pin
Integration
• Design & topology for example ESD IP
• Flex frame integration and generator tool
Flexframes
Final Delivery
IPs
(schematic
+ block
layout)
ESD Design …
28/11.2012 Ph Galy JP CNFM 2012
39
Check before/after IP development
• Database environment setup
• Topologic checks : DFM …
• Electric checks : PISI/ESD/ERC/Aging …
• Reports & waivers file
CAD/TOPO/EC Checkers Tool
Macro level
Nano level
28/11.2012 Ph Galy JP CNFM 2012
I/O ring builder/checkerTool 40
IO Builder/Checker during development
• Builder/checker IO focused
• Multi engines & thread
• Data Model IP level
• Provide optimized robust solution
Proposed Solution Area: 0.62 mm² PLL example
Area: 0.21 mm²
28/11.2012 Ph Galy JP CNFM 2012
41
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
28/11.2012 Ph Galy JP CNFM 2012
Partners & collaborations 42
R&D collaborations
• Universities & Laboratories • Thesis (open positions )
• Internships
• Projects development
• CAD Providers
• National & European projects
• Consortium