io362af usb pd 3.0 type-c e-marker data sheet - fan-lun.com · green pakcage: lead free (rohs...

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IO362AF

USB PD 3.0

Type-C E-Marker

Data Sheet Revision 2.0

April, 2018

ENE RESERVES THE RIGHT TO AMEND THIS DOCUMENT WITHOUT NOTICE AT ANY TIME. ENE

ASSUMES NO RESPONSIBILITY FOR ANY ERRORS APPEAR IN THE DOCUMENT, AND ENE DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ENE PRODUCTS

INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, OR

INFRINGEMENT OF ANY PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS. THIS

DOCUMENT CONTAINS CONFIDENTIAL INFORMATION OF ENE PRODUCTS. ANY UNAUTHORIZED USE

OR DISCLOSURE IS PROHIBITED.

This confidential document is restricted to circulation and only issued to:

Recipient

Company

Serial

Number

Copyright© 2016, ENE Technology Inc. All rights reserved.

Headquarters

4F-1, No.9, Prosperity Rd.,

Science-based Industrial Park,

Hsinchu City, Taiwan, R.O.C

TEL: 886-3-6662888 FAX: 886-3-6662999

http://www.ene.com.tw

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4F, No.88, Bauchiau Rd.

Shindian City, Taipei,

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TEL: 886-2-89111525

FAX: 886-2-89111523

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Revision

Revision Description Date

1.0 1. First release 2016/11

1.1 1. Add USB-IF Certification TID Number. 2016/12

1.2 1. Modify the top-side marking 2017/01

1.3 1. Revise Part Number Description 2017/01

1.4 1. Modify the bit type of 0x88[3] &[1] 2017/02

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Index

1. OVERVIEW .................................................................................................................................................. 1

1. 1 FEATURES ................................................................................................................................................ 1

1.2 BLOCK DIAGRAM .................................................................................................................................... 1

1.3 TYPICAL APPLICATION SCENARIOS ........................................................................................................ 1

1.4 PART NUMBER ......................................................................................................................................... 2

2. PIN ASSIGNMENT ...................................................................................................................................... 2

3. HARDWARE TRAP FOR TEST MODE ................................................................................................... 2

4. ELECTRICAL CHARACTERISTICS ...................................................................................................... 3

4.1 ABSOLUTE MAXIMUM RATING ............................................................................................................... 3

4.2 IO BUFFER ELECTRICAL CHARACTERISTICS......................................................................................... 3

4.3 RECOMMEND OPERATION CONDITION ................................................................................................... 3

4.4 OPERATING CURRENT ............................................................................................................................. 3

5. PACKAGE INFORMATION ...................................................................................................................... 4

5.1 DFN 8-PIN OUTLINE DIAGRAM .............................................................................................................. 4

5.2 PART NUMBER AND TOPSIDE MARKING ................................................................................................. 4

APPENDIX FUNCTION AND REGISTER DESCRIPTION (FOR ENE INTERNAL USE ONLY) ... 5

A.1 INTERNAL MEMORY MAP ...................................................................................................................... 5

A.2 GPIO....................................................................................................................................................... 5

A.2.1 GPIO ATTRIBUTE TABLE .................................................................................................................... 6

A.3.2 GPIO REGISTER DESCRIPTIONS ......................................................................................................... 6

A.3 GENERAL PURPOSE WAKE-UP CONTROLLER (GPWU) ........................................................................ 8

A.3.1 GPWU FUNCTION DESCRIPTION ........................................................................................................ 8

A.3.2 GPWU REGISTERS DESCRIPTION ...................................................................................................... 8

A.4 WATCHDOG TIMER (WDT) .................................................................................................................. 10

A.4.1 WDT FUNCITON DESCRIPTION ......................................................................................................... 10

A.4.2 WDT REGISTERS DESCRIPTION (0XFC80~0XFC8F/0X0100~0X011F)........................................... 10

A.5 SMBUS/I2C MASTER CONTROLLER ................................................................................................... 12

A.5.1 FSM_ MASTER REGISTER DESCRIPTION ......................................................................................... 12

A.6 X-BUS INTERFACE (XBI) MODULE AND EMBEDDED FLASH ............................................................... 15

A.6.1 XBI REGISTERS DESCRIPTION .......................................................................................................... 15

A.6.2 EMBEDDED FLASH PROTECTION ...................................................................................................... 20

A.7 BMC REGISTERS DESCRIPTION .......................................................................................................... 21

A.7.1 BMC FUNCTION DESCRIPTION ......................................................................................................... 21

A.8.2 BMC REGISTERS DESCRIPTION ....................................................................................................... 21

A.8 MISC REGISTERS DESCRIPTION ......................................................................................................... 26

A.10 8051 MICROPROCESSOR .................................................................................................................... 30

1

IO362AF USB PD 3.0 Type-C E-Marker

USB-IF Certification TID: 1060065

1. Overview The IO362AF is a USB PD3.0 Type-C E-Marker IC for USB cables. It supports SOP’ messages for passive cables.

1. 1 Features Integration of two isolation diodes and two Ra

No external R, C passive components required on PCB Operating VCONN range: 2.7V~5.5V

8051 + embedded flash architecture facilitating application customization

EDI Serial Two-Wire Debugging or In-System Programming Interface

Field Programmable via CC interface

ESD HBM 8KV

Green Pakcage: Lead Free (ROHS compliant) /Halogen Free (IEC 61249-2-21)

Package: DFN-8 dimension: 2x3x0.75mm

1.2 Block Diagram

4b/5b

Encoder

BMC

Encoder

BMC

Decoder

SOP

Detect

5b4b

Decoder

MCU

EDICK

POFR

ADCO Flash

VBMC

LDO LDO

VCONNA

EDIDA

Ra

Debug &

Prog

Interface

CRC

BIST CRCGPIO

Ports

WDT

32MHz

16MHz

32787Hz

÷48832787Hz

VCC

40K

EH

B

Ra

VCONNB

VM

LDO

BMC

IO1/FIDIO0/WP#

1.3 Typical Application Scenarios

Figure-1 demonstrates a USB cable with IO362AF within one USB plug. The IO362AF is responsible for SOP’

communication with the DFP regardless of it is being plugged into the DFP side or the UFP side.

BMCCC

GND

VCONN

CC

VCONN

GND

Cable Plug Cable Plug

SOP’

DFP UFP

Pad

VCONNA VCONNB

IO0/WP#

Ra

SOP’SOP”

Detect

FID

CC

VCONN

Typical Cable (FID=GND)

Legend: The red wires representing circuit paths being powered

2

1 3

4

6

5NC

7EDIDA

8EDICK

Note: Do not connect pin7 and pin8 to GND

Figure-1 Typical Cable with E-maker IC at one-end of the plug

2

1.4 Part Number Part

Numbter Package Outline

IO362 AF DFN-8

2x3x0.75mm

4

3

2

1

5

6

7

8VCONNA

BMC

VCONNB

FID

EDICK

EDIDA

IO0/WP#

NC

(bottom view)

GND

The Thermal Pad is GND

1.5 Order Information

MOQ quantity 3Kpcs(T/R)

2. Pin Assignment Name Pin Description

VCONNA Power Supply

BMC The Bi-phase Mark Coding Controller Interface (CC)

VCONNB Power Supply

FID The FID pin should be tied to GND for a typical cable application where IO362AF acts as SOP’

EDIDA ENE Debug Interface (EDI) Data Port

This pin is internally pull-up to VCC via 40KΩ. Note: Do not connect to GND on PCB

EDICK ENE Debug Interface (EDI) Clock Port

This pin is internally pull-up to VCC via 40KΩ. Note: Do not connect to GND on PCB

IO0/WP# Multi-Function Pin:

1. IO0:GPIO00 2. WP#: eFlash Protection (Low=Protection Locked)

NC No Connect

GND Ground

3. Hardware Trap for Test Mode The HW Trap option enables the chip to enter into test mode, which is a special operating mode for testing and

debug purpose only. To enter into the test mode, the following steps should be met:

1. The EDICK/EDIDA/NC pins should be connected to GND externally during power-on reset period.

2. The EDI tool should be connected and apply a specific password bit patterns.

Pin Name POR asserted (low) POR De-asserted(High) Test Mode Enable

EDICK Internal Pull-up 40KΩ Internal Pull-up 40KΩ Connect to GND

EDIDA Internal Pull-up 40KΩ Internal Pull-up 40KΩ Connect to GND

NC Internal Pull-up 40KΩ Floating Connect to GND

3

4. Electrical Characteristics 4.1 Absolute Maximum Rating

Item Symbol Condition Min Typ Max Unit

DC Supply Voltage VCONN - -0.3 5 6.0 V

Power Dissipation P tot VCONN=5V W

Junction Operating Temperature Tj 150 oC

Storage Temperature Tstg -50 150 oC

Thermal resistance junction to case θjc 21.3 oC/W

Thermal resistance junction to Ambient θja 58.3 oC/W

4.2 IO Buffer Electrical Characteristics Based on condition VCONN=5.0V and 25

oC temperature unless otherwise noted

Parameter Symbol Min Typ. Max Unit Condition Input Low Threshold Vt- 1.9 V

Input High Threshold Vt+ 3.0 V

Hysteresis VTH 1.1 V

Input Leakage Current ILIL 1 μA

Input Leakage Current ILIH 1 μA

Input Pull-Up Resistance RPU 36K Ω

Input Capacitance CPU 5.5 pF

Output Capacitance COUT 5.5 pF

Bi-directional Capacitance CBID 5.5 pF

Output Drive Low Current IOL 22 mA Sink current up to 0.4V @16mA mode

10 mA Sink current up to 0.4V @4mA mode

Output Drive High

Current IOH

19 mA Source current down to 4.5V @ 16mA mode

4 mA Source current down to 4.5V @ 4mA mode

4.3 Recommend Operation Condition

Symbol Parameter Limits

Unit Min Typ Max

VCONN Power Source Voltage 2.7 5.5 V

GND Ground Voltage -0.3 V

Top Operating Temperature -40 85 ℃

4.4 Operating Current

State Parameter Limits

Unit Typ

Operating Normal operating mode with 8051/eFlash= 16MHz/32MHz clocking 9.8 mA

Deep Sleep All modules OFF (with Ra=1KΩ) 5.16 mA

4

5. Package Information 5.1 DFN 8-Pin Outline Diagram

Top View

Side View

Bottom View

DFN Outline Dimensions

DIM Min. Typ. Max.

A 0.7 0.75 0.8

A1 0 0.02 0.05

A2 － 0.55 0.57

A3 0.203 REF

b 0.2 0.25 0.3

D 2BSC

E 3BSC

e 0.5BSC

K 0.2 --- ---

D2 1.35 1.40 1.45

E2 1.25 1.30 1.35

L 0.30 0.35 0.40

Unit mm

Package 2x 3 x 0.75 , 0.5 PITCH

5.2 Part Number and Topside Marking

X X X X X X X

Pin 1 Mark

Date Code

Part Number

362

Revision Package Fn Code

F: DFN-8

Reserved

A: Revision #

5

Appendix Function and Register Description (for EnE internal use only)

A.1 Internal Memory Map

The following table summarizes the memory map space

No Module Descriptions Address Range Size (Byte)

1 GPIO General purpose I/O 0x0000~0x007F 128

2 GPWU General purpose wakeup event 0x0100~0x017F 128

3 WDT Watchdog timer 0x0200~0x027F 128

4 FSMBus FSM_Master 0x0300~0x037F 128

5 XBI X-bus interface 0x0400~0x047F 128

6 MISC MISC 0x0500~0x057F 128

7 BMC BMC Controller 0x0600~0x067F 128

A.2 GPIO The GPIO structure is illustrated as following diagram. There are several register settings determine the GPIO

states, including pin definition for GPIO function or alternative function, GPIO input/output mode, output open-drain

enable, input pull-up resistor enable and output current driving selection.

GPIOFS are function selection registers for GPIO function or alternative output function for output mode

GPIOOD are open-drain enable registers for output function.

GPIOOE are output enable registers for output mode

GPIOPU are pull-up enable registers for input mode

GPIOIE are input enable registers for input mode

GPIOIN are input data ports

GPIOD are output data ports

.

Output

Buffer

Pull-up Enable

GPIOIN

GPIOIE

Alt. Input

GPIOFS

GPIOD

Alt. Output

GPIOOE

GPIOFS

Alt. Output Enable

GPIOOD

I/O PIN

1

0

0

0

1

1

6

A.2.1 GPIO Attribute Table

GPIO Alt. Selection Reg. Input

Enable

Output

Enable

Pull Up

(40KΩ)

Open

Drain

Output

Current

GPIO00 GPIOFS00.[0](WP#) V V V V 4-16mA

GPIO06 GPIOFS00.[6](SCL) V V V V 4-16mA

GPIO07 GPIOFS00.[7](SDA) V V V V 4-16mA

A.3.2 GPIO Register Descriptions

Function Selection Register Address Name Type. Description Default

0: General purpose output (GPO) function selected

1: Alternative output function selected.

0x0000 GPIOFS00 R/W bit[0:7] correspond to GPIO00~GPIO07 Function Selection Note: GPIO02/03/04/05 don’t exist in IO362

0x00

0x0001 GPIOFS08 R/W bit[0:7] correspond to GPIO08 Function Selection

Note: GPIO08 doesn’t exist in IO362 0x00

Output Enable Register Address Name Type. Description Default

0: Output Disable 1: Output Enable

0x0010 GPIOOE00 R/W bit[0:7] correspond to GPIO00~GPIO07 Output Enable

Note: GPIO02/03/04/05 don’t exist in IO362 0x00

0x0011 GPIOOE08 R/W bit[0:7] correspond to GPIO08 Output Enable Note: GPIO08 doesn’t exist in IO362

0x00

Output Data Port Register Address Name Type. Description Default

0x0020 GPIOD00 R/W bit[0:7] correspond to GPIO00~GPIO07 Output Data Port Note: GPIO02/03/04/05 don’t exist in IO362

0x00

0x0021 GPIOD08 R/W bit[0:7] correspond to GPIO08 Output Data Port output


Input Data Port Register Address Name Type. Description Default

0x0030 GPIOIN00 RO bit[0:7] correspond to GPIO00~GPIO07 Input Data Port

Note: GPIO02/03/04/05 don’t exist in IO362 0xFF

0x0031 GPIOIN08 RO bit[0:7] correspond to GPIO08 Input Data Port

Note: GPIO08 doesn’t exist in IO362 0xFF

Pull-up Enable Register Address Name Type. Description Default

0: Pull-Up resistor disable 1: Pull-Up resistor enable

0x0040 GPIOPU00 R/W bit[0:7] correspond to GPIO00~GPIO07 Pull-Up Resistor Enable Note: GPIO02/03/04/05 don’t exist in IO362

0x00

0x0041 GPIOPU08 R/W bit[0:7] correspond to GPIO08 Pull-Up Resistor Enable


Open Drain Enable Register Address Name Type. Description Default

0: Open drain disable 1: Open drain enable.

0x0050 GPIOOD00 R/W bit[0:7] correspond to GPIO00~GPIO07 Open Drain Enable

Note: GPIO02/03/04/05 don’t exist in IO362 0x00

0x0051 GPIOOD08 R/W bit[0:7] correspond to GPIO08 Open Drain Enable


Input Enable Register Address Name Type. Description Default

0: GPIO input mode disable 1: GPIO input mode enable.

0x0060 GPIOIE00 R/W bit[0:7] correspond to GPIO00~GPIO07 Input Enable

Note: GPIO02/03/04/05 don’t exist in IO362

0x01

0x0061 GPIOIE08 R/W bit[0:7] correspond to GPIO08 Input Enable Note: GPIO08 doesn’t exist in IO362

0x00

Output current Register Address Name Type. Description Default

7

0: GPIO Output current 4mA 1: GPIO Output current 16mA

0x0070 GPIOOC00 R/W bit[0:7] correspond to GPIO00~GPIO07 Output current

Note: GPIO02/03/04/05 don’t exist in IO362

0x00

0x0071 GPIOOC08 R/W bit[0:7] correspond to GPIO08 Output current

Note: GPIO08 doesn’t exist 0x00

8

A.3 General Purpose Wake-up Controller (GPWU)

A.3.1 GPWU Function Description The GPIO module provides flexible methods to wake up or interrupt the chip, including level-trigger, edge-trigger

and toggle-trigger. To enable the wakeup function of a ceratin GPIO pin, that GPIO must be configured in Input mode. In

order to support wakeup from various input signal conditions, the respective register settings associated with that GPIO

should be programmed properly as summarized below:

Wakeup Enable

0: Disable

1: Enable

Polarity

0:↓/ L

1:↑/ H

Edge/Level

0: Edge

1: Level

Toggle

0: Disable

1: Enable

Description

1 X X 1 Signal toggle trigger

1 0 0 0 Falling edge trigger

1 0 1 0 Low level trigger

1 1 0 0 Rising edge trigger

1 1 1 0 High level trigger

For every wakeup source, there is an associated pending flag will become asserted if the wakeup condition is met.

However, during the RUN and IDLE modes, the pending flag bit will become asserted regardless of the Wakeup Enable

bit is enabled or disabled once the trigger condition is met.

During the STOP mode, only the level trigger wakeup is supported. The conditions that wakeup events can become

outstanding are described in the below table.

Wakeup Enable

0: Disable

1: Enable

Polarity

0:↓/ L

1:↑/ H

Edge/Level

0: Edge

1: Level

Toggle

0: Disable

1: Enable

Description

1 0 X X Low Level trigger

1 1 X X High Level trigger

A.3.2 GPWU Registers Description GPIO Wakeup Event Enable

Address Name Bit Type Description Default

0: Wakeup event disable 1: Wakeup event enable

0x0100 GPWUEN00 7-0 R/W Bit[0:7] correspond to GPIO00~GPIO07 Wakeup Event Switch

Note: GPIO02/03/04/05 don’t exist 0x00

0x0101 GPWUEN08 7-0 R/W Bit[0:7] correspond to GPIO08 Wakeup Event Switch Note: GPIO08 doesn’t exist

0x00

GPIO Wakeup Event Pending Flag Address Name Bit Type Description Default

0: No wakeup event 1: Wakeup event pending

0x0110 GPWUPF00 7-0 R/W1C Bit[0:7] correspond to GPIO00~GPIO07 Wakeup Pending Flag Note: GPIO02/03/04/05 don’t exist

0x00

0x0111 GPWUPF08 7-0 R/W1C Bit[0:7] correspond to GPIO08 Wakeup Pending Flag

Note: GPIO08 doesn’t exist

0x00

GPIO Wakeup Polarity Selection Address Name Bit Type Description Default

0: Low active (level trigger) / Falling (edge trigger)

1: High active (high trigger) / Rising (edge trigger)

0x0120 GPWUPS00 7-0 R/W Bit[0:7] correspond to GPIO00~GPIO07 Wakeup Polarity Select Note: GPIO02/03/04/05 don’t exist

0x00

0x0121 GPWUPS08 7-0 R/W Bit[0:7] correspond to GPIO08 Wakeup Polarity Select


GPIO Wakeup Level/Edge Trigger Selection Address Name Bit Type Description Default

0: Edge trigger 1: Level trigger

0x0130 GPWUEL00 7-0 R/W Bit[0:7] correspond to GPIO00~GPIO07 Wakeup Level/Edge Select


0x0131 GPWUEL08 7-0 R/W Bit[0:7] correspond to GPIO08 Wakeup Level/Edge Select Note: GPIO08 doesn’t exist

0x00

9

GPIO Wakeup Input Change (Toggle) Trigger Selection

Note: This setting will ignore the corresponding bit of GPWUELxx. Address Name Bit Type Description Default

0: Toggle trigger disable 1: Toggle trigger enable

0x0140 GPWUCHG00 7-0 R/W Bit[0:7] correspond to GPIO00~GPIO07 Wakeup Toggle Trigger


0x0141 GPWUCHG08 7-0 R/W Bit[0:7] correspond to GPIO08 Wakeup Toggle Trigger


*New GPWU interrupt

10

A.4 Watchdog Timer (WDT)

A.4.1 WDT Funciton Description The 14-bit WDT timer runs off the unit time step of 32.787KHz clock, which is devided by 488 from the 16MHz

ADCO outut. Its maximum time out period is 2^14 * 1

32787 = 0.5sec. The WDT triggers the system reset in three

options:

- Reset the 8051 microprocessor only.

- Reset the whole logic, except GPIO modules.

- Reset the whole logic, including GPIO modules.

A.4.2 WDT Registers Description (0xFC80~0xFC8F/0x0100~0x011F) WDT Configuration


0x0200 WDTCFG 7 RSV Reserved (Clock source from ADCO ) 0x00

6~3 R/W WDT disable password

Writing 1001b to this field will force WDT to disable

2 RSV Reserved

1 R/W WDT interrupt enable

0: Disable 1: Enable

0 R/W WDT enable 0: N/A

1: Enable WDT, clear WDT interrupt flag and WDT reset flag, restart WDT

counter. P.S. When both WDTCFG [0]&[1] are set, if WDT counter counts to half-way

and the WDT interrupt flag WDTPF[1] is not cleared, the WDT timeout reset will

occur. Refer to PXCFG(reset domain)

WDT Pending Flag


0x0201 WDTPF 7-2 RSV Reserved 0x00

1 R/W1C WDT interrupt flag Once the timer counts to half of 14-bit WDT Match Register (WDTM1308 [6:0]:

WDTM0700[7:0]:), an interrupt occurs. If the timer counts to 14-bit WDT Match

Register, a WDT reset occurs.

0 R/W1C WDT reset flag Once the timer counts to 14-bit WDT Match Register, a WDT reset occurs and

this flag is set.

WDT Counter Match Bit 1308


0x0202 WDTM1308 7~6 RSV Reserved 0x00

5~0 R/W The MSB 6 bits of WDT Match Register

The WDT timer unit step is 30.5us * 210 = 31.25ms. The overall

Note: The concatenated value must at least ≧3 due to design limitation.

WDT Counter Match Bit 0700


0x0203 WDTM0700 7-0 R/W The LSB 8 bits of WDT Match Register

The WDT timer unit step is 30.5us * 210 = 31.25ms. The overall

Note: The concatenated value must at least ≧3 due to design limitation.

0x00

WDT Firmware Configuration Register 0


0x0204 WDTFCR0 7~0 R/W The register is configured by firmware and there is no any hardware function 0x00

WDT Firmware Configuration Register 1


0x0205 WDTFCR1 7~0 R/W The register is configured by firmware and there is no any hardware function 0x00

Program Counter Value High Byte When WDT Reset Address Name Bit Type Description Default

0x0206 WDTPCH 7~0 RO The PC value high byte when WDT reset occur Note:

This Register can’t be reset by WDT reset event

0x00

11

Program Counter Value Low Byte When WDT Reset Address Name Bit Type Description Default

0x0207 WDTPCL 7~0 RO The PC value low byte when WDT reset occur Note:


0x00

Stack Pointer Value When WDT Reset Address Name Bit Type Description Default

0x0208 WDTSP 7~0 RO The SP value when WDT reset occur

Note:


0x00

WDT Reset Selection Address Name Bit Type Description Default

0x0209 WDTTRS 7~0 RSV Reserved 0x00

1 R/W Setting of WDT timeout reset for GPIO

0: GPIO module will not be reset when WDT timeout reset occurs. 1: GPIO module will be reset when WDT timeout reset occurs.

0 R/W WDT timeout reset selection

0: reset whole chip, selective GPIO module.

1: reset 8051 only

12

A.5 SMBus/I2C Master Controller

A.5.1 FSM_ Master Register Description

FSM_Master Configuration Address Name Bit Type Description Default

0x0310 FSMBCFG 7 WO

STOP signal SMBus will issue STOP signal while this bit is written

0x00

6 RSV Reserved

5 R/W

Dynamic gating clock enable (for logic clock)

Dynamic gating clock is HW auto control. 0: disable (default) 1: enable

4 WO HW Reset

Write one toreset, Reset All HW circuit except register value

3 R/W

Select Bus idle time

0: 64us

1:128us(for SMBus low clock, ex: 7.8KHz)

2 R/W Host Notify enable 0: disable 1: enable

1 R/W Timeout function enable

0: disable 1: enable

0 R/W

SMBus function enable The all logic controller will be reset when disable this function except register

value and host notify function.

0: disable 1: enable

FSM_ Master Flexible Protocol

Note: Please make sure this control field is ready before issuing Flexible protocol. Address Name Bit Type Description Default

0x0311 FSMBFRT

7~4 RSV Reserved 0x00

3 R/W CMD byte 0: no CMD byte on protocol 1: CMD byte on protocol

2 R/W CNT byte

0: no CNT byte on protocol 1: CNT byte on protocol

1 R/W PEC byte 0: no PEC byte on protocol 1: PEC byte on protocol

0 R/W STOP signal

0: no stop signal on protocol 1: Stop signal on protocol

FSM_ Master CRC Value Address Name Bit Type Description Default

0x0312 FSMBPEC 7-0 RO Generated PEC value 0x00

FSM_ Master Operating Frequency High Address Name Bit Type Description Default

0x0313 FSMBOFH 7 RSV Reserved 0x00

6~0 R/W SMBus clock High Length = (FSMBOFH [6:0]+1) * 0.5us

FSM_ Master Operating Frequency Low Address Name Bit Type Description Default

0x0314 FSMBOFL 7 RSV Reserve 0x00

6~0 R/W SMBus clock Low Length = (FSMBOFL [6:0]+1) * 0.5us

Operating Frequency = 1MHz ~ 7.8KHz

FSM_ Master Interrupt Enable Address Name Bit Type Description Default

0x0315 FSMBIE 7~3 RSV Reserve 0x00

2 R/W Interrupt Enable of block data array

1 R/W Interrupt Enable of Host Notify protocol completed

0 R/W Interrupt Enable of completed

FSM_ Master Interrupt Pending Flag Address Name Bit Type Description Default

0x0316 FSMBPF

7~3 RSV Reserve 0x00

2 R/W1C

Block data array pending flag

If RX/TX data are over 32 bytes, the user can control the protocol progress via this bit.

0: Continue Block Data Array protocol

1: Stop Block Data Array protocol

13

Completed data preparation before clearing this bit and then the protocol

progress will be continued.

1 R/W1C Host Notify Protocol Complete pending flag This bit is event pending flag of Host Notify command complete

0 R/W1C

Complete pending flag

This bit is event pending flag of bus complete In SMBus: Protocol complete

In I2C/PM Bus (Flexible SMBus): Read/Write Package complete.

FSM_ Master Received PEC Value Address Name Bit Type Description Default

0x0317 FSMBPECB 7-0 RO The PEC value received from the SMBus. 0x00

FSM_ Master Protocol Address Name Bit Type Description Default

0x0318 FSMBPRTCL 7 R/W SMBus transaction with PEC (Packet Error Check)

0: Disable 1: Enable.

0x00

6-0 R/W HW Mode protocol.

02h: Quick Write

03h: Quick Read 04h: Send Byte

05h: Receive Byte

06h: Write Byte 07h: Read Byte

08h: Write Word

09h: Read Word 0Ah: Write Block

0Bh: Read Block

0Ch: Word Process 0Dh: Block Process

Flexible Mode protocol: 7Fh: Flexible Protocol for I2C/PMBus

others: Reserved

FSM_ Master Status Address Name Bit Type Description Default

0x0319 FSMBSTS 7 RO

SMBus status of Master State Machine

0: busy state 1: idle state 0x00

6 RO

SMBus status of Host Notify State Machine

0: busy state 1: idle state

5 RO Reserve

4-0 RO Error code.

00h: no error

10h: slave address no ACK 12h: command no ACK

13h: slave data no ACK

17h: lost arbitration 18h: bus timeout

19h: unsupported protocol

1Ah: bus busy 1Eh: STOP fail

1Fh: PEC (Packet Error Check) error

others: Reserved

FSM_ Master Address Port Address Name Bit Type Description Default

0x031A FSMBADR 7-1 R/W Slave address (7-bits long). 0x00

0 R/W

Data direction bit

0: Write 1: Read Note: This bit is ignored in HW mode protocol

FSM_ Master Command Port Address Name Bit Type Description Default

0x031B FSMBCMD 7-0 R/W Command port 0x00

14

FSM_ Master Data Array (32 Bytes) Address Name Bit Type Description Default

0x031C ~

0x033B

FSMBDATx 7-0 R/W

Data port 0x00

FSM_ Master Block Count Address Name Bit Type Description Default

0x033C FSMBCNT 7-0 R/W Block Count. The Block Count can be either: 1. For TX: Set by firmware before transaction starts

2. For RX: Set by the hardware controller by extracting the Byte Count

information from the data received from slave device “0x00”stands for 32-byte length in a block transfer.

0x00

FSM_ Master Host Notify Protocol Address Address Name Bit Type Description Default

0x033D

FSMBNADR 7-0 RO This register is the slave address for Host Notify protocol 0x00

FSM_ Master Host Notify Data Address Name Bit Type Description Default

0x033E FSMBNDAT0 7-0 RO Host Notify data (low byte) 0x00

0x033F

FSMBNDAT1 7-0 RO Host Notify data (high byte) 0x00

FSM_Master Internal Block Counter Value Address Name Bit Type Description Default

0x0380 FSMBICN 7-0 RO Internal Block Counter Value Register

It will be reset when the FSM_Master detected the START signal

0x00

15

A.6 X-Bus Interface (XBI) Module and Embedded Flash

A.6.1 XBI Registers Description

XBI Configuration


0x0400 XBICFG 7~5 RSV Reserved 0x05

4 R/W Enable hardware debug mode operation for embedded flash

3 RSV Reserved

2~0 R/W Delay Cycles setting for embedded flash access

Set this value to add the delay cycle after issuing EF command by EF controller.

CAUTION! Please set this value AFTER ADCO trimming value restoration

if unlocked mode is preferred, or MCU may be crashed unexpectedly.

XBI Configuration 2 Address Name Bit Type Description Default

0x0401 XBICFG2 7~5 RSV Reserved 0x04

2 R/W Reset XBI arbiter while in idle/stop mode.


1~0 RSV Reserved

XBI Embedded Flash Address (17-bit) = [EFA2(1 bits): EFA1(8 bits): EFA0(8 bits)] Address Name Bit Type Description Default

0x0402 EFA0 7~0 R/W Embedded Address lower 8-bits (A7:A0) 0x00

0x0403 EFA1 7~0 R/W Embedded Address middle 8-bits (A12:A8) 0x00

0x0404 EFA2 7~0 RSV Reserved 0x00

XBI Embedded Flash Output/Input Data Port Address Name Bit Type Description Default

0x0405 EFDAT 7~0 R/W Input (read) / Output (write) data port of Embedded flash interface. 0x00

XBI Embedded Flash Command Port Address Name Bit Type Description Default

0x0406 EFCMD 7-0 R/W Commands support for embedded flash. Writing this register will force the

protocol start. Please note, the address phases must be prior to command phase.

Embedded flash command support:

02h Page latch

03h Read

12h Continuous latch 13h Continuous read

Note: The continuous command will increase the value of the register

EFA0~EFA2 after the command finish 20h Erase selected page

60h Chip Erase

Note: This command will erase the entire embedded flash content and hence cause the 8051 code erased. The firmware should never use this command

otherwise the 8051 will be hung. 70h Program selected page

80h Clear HVPL data

90h Read Trim data from special rows A0h Burst Write

B0h Bulk Program

0x00

XBI Embedded Flash Configuration/Status Register


0x0407 EFCFG 7~4 RSV Reserved 0x00 3 R/W Write enable of EFCMD register


2 RSV Reserved

1 RO Embedded flash controller accessing in busy status.

0: not busy 1: busy

0 RSV Reserved

16

XBI Embedded Flash Output Data for Read compare Address Name Bit Type Description Default

0x0408 EFDATR 7-0 RO Output data to embedded flash interface. 0x00

XBI Embedded Flash Burst Write Address Name Bit Type Description Default

0x0409 EMFBURW 7-1 RSV Reserved 0x00

0 R/W Abort Burst Write (Page Latch)


XBI Erase Waiting Time of Embedded Flash Controller Address Name Bit Type Description Default

0x040A EFCEWT 7 RSV Reserved

0x12 6~0 R/W Setting for Erase Waiting Time by 256us time unit

Note that Default is 4.5ms

XBI Program Waiting Time of Embedded Flash Controller


0x040B EFCPWT 7 RSV Reserved

0x06 6~0 R/W Setting for Program Waiting Time by 256us time unit

Note that Default is 1.5ms, but need to be set to 0x07 (About 1.8ms [+13%/-5%])

when issuing Program Bulk Command.

XBI EFC Status


0x040C EFCST 7~1 RSV Reserved 0x00

0 R/W1C Error Pending Flag of EFC

The pending flash will be asserted if there is a writing action to EFCMD

(0x102C) Register while embedded flash controller is in busy state.

Flash Mapping Windows Control/Status


0x040D FMWCSR 7 R/W Enable the function of flash mapping window 0: Disable(default) 1: Enable

0x00

6~2 RSV Reserved

1~0 R/W Base Address [9:8] setting for Flash Mapping Windows

Flash Mapping Windows Base Address


0x040E FMWBA 7~0 R/W Base Address [7:0] setting for Flash Mapping Windows

Note: Only [2:0] 3bits are valid if embedded flash is selected

0x00

XBI Embedded Flash Protection Control Status

Note: This register will be protected and cannot write one to clear if lock bit of any set is enable


0x040F EFPCSR 7-6 RSV Reserved 0x00

5 R/W1C Write protection violation pending flag of EFP Register Set 2

4 R/W1C Read protection violation pending flag of EFP Register Set 2





XBI Embedded Flash Protection Start Address Register 0

Note: The content of this register will be loaded by H/W after embedded flash calibration


0x0410 EFPSA0 7~0 R/W Start address setting for protection area 0, by 128B alignment 0x00

XBI Embedded Flash Protection End Address Register 0



0x0411 EFPEA0 7~0 R/W End address setting for protection area 0, by 128B alignment 0x00

17

XBI Embedded Flash Protection Access Control Register 0



0x0412 EPFAC0 7 RSV Reserved 0x00

6 R/W Lock Enable Switch(this bit be unlocked at the WP# de-asserted)

0: Lock Disable(Default)

1:Lock Enable to effect the below protection A.EFPSA0/EFPEA0/EFPAC0 will be read only

B.Content of special row 2 will be masked.

4 RSV Reserved

3 R/W Enable write protection for area 0 from EDI

2 R/W Enable read protection for area 0 from EDI

1 R/W Enable write protection to area 0 from 8051

0 R/W Enable read protection of 8051 from bus access for area 0













6 R/W Lock Enable Switch (this bit be unlocked at the WP# de-asserted)


1:Lock Enable and there are following protections: A.EFPSA1/EFPEA1/EFPAC1 will be read only

5~4 RSV Reserved

















6 R/W Lock Enable Switch (this bit be unlocked at the WP# de-asserted)


1:Lock Enable and there are following protections:

18

A.EFPSA2/EFPEA2/EFPAC2 will be read only

5~4 R/W Reserved





XBI Flash Macro Trimming Register 0 Address Name Bit Type Description Default

0x0420 XBIFMTR0 7~4 R/W PDACP[3:0]

DAC for independent control of VPOS pump level when Program operation in

flash macro

0xDD

3~0 R/W PDACE[3:0] DAC for independent control of VPOS pump level when Erase operation in flash

macro


0x0421 XBIFMTR1 7~4 R/W NDACP[3:0]

DAC for independent control of VNEG pump level when Program operation in

flash macro

0xAA

3~0 R/W NDACE[3:0]

DAC for independent control of VNEG pump level when Erase operation in flash

macro


0x0422 XBIFMTR2 7~6 RSV Reserved 0x01

5~0 R/W ITIM[5:0]

Trim DAC for read and write optimized performanc

XBI BGE Macro Trimming Register 0 Address Name Bit Type Description Default

0x0423 XBIBMTR0 7~3 RSV Reserved 0x01

2~0 R/W TCTRIM[2:0]

Trimming bits for temperature coefficient of Vref

XBI BGE Macro Trimming Register 1


0x0424 XBIBMTR1 7~5 RSV Reserved 0x10

4~0 R/W ABSTRIM[4:0]

Trimming bits for absolute value of Vref

LDO11 Macro Trimming Register Address Name Bit Type Description Default

0x0425 LDO11TR 7 RSV Reserved 0x4A

6~4 R/W V11TRIM[2:0]

Trimming bits for Output Voltage of LDO11

3~2 R/W VIHTRIM[1:0] Trimming bits for Input High Voltage (VIH) of BMC IO

1~0 R/W VILTRIM[1:0]

Trimming bits for Input Low Voltage (VIL) of BMC IO

BMC IO Falling Slew Rate Trimming Register


0x0426 DNSRTR 7~4 R/W SRFDNTRIM[3:0]

Trimming bits for Faster Falling Slew Rate of BMC IO 0x88

3~0 R/W SRSDNTRIM[3:0]

Trimming bits for Slower Falling Slew Rate of BMC IO

19

BMC IO Rising Slew Rate Trimming Register


0x0427 UPSRTR 7~4 R/W SRFUPTRIM[3:0]

Trimming bits for Faster Rising Slew Rate of BMC IO 0x88

3~0 R/W SRSUPTRIM[3:0]

Trimming bits for Slower Rising Slew Rate of BMC IO

BMC IO Falling Slew Rate Driving Control High Byte Register Address Name Bit Type Description Default

0x042A DNTCH 7~0 R/W DNTCH[7:0] High-byte Timing Control bits for Falling Slew Rate of BMC IO

1: Faster Falling Slew Rate Trim bits is used in BMC IO 0: Slower Falling Slew Rate Trim bits is used in BMC IO

0x01

BMC IO Falling Slew Rate Driving Control Low Byte Register Address Name Bit Type Description Default

0x042B DNTCL 7~0 R/W DNTCL[7:0] Low-byte Timing Control bits for Falling Slew Rate of BMC IO 1: Faster Falling Slew Rate Trim bits is used in BMC IO

0: Slower Falling Slew Rate Trim bits is used in BMC IO

0x80

Notes: The bits of {DNTCH[7:0], DNTCL[7:0]} will be shifted out sequentially per 1 cycle of 16MHz, and the MSB is shifted firstly, to switch

between Slower and Faster trim bits inside BMC IO, once the Falling edge of data output is started.

BMC IO Rising Slew Rate Driving Control High Byte Register Address Name Bit Type Description Default

0x042C UPTCH 7~0 R/W UPTCH[7:0] High-byte Timing Control bits for Rising Slew Rate of BMC IO 1: Faster Rising Slew Rate Trim bits is used in BMC IO

0: Slower Rising Slew Rate Trim bits is used in BMC IO

0x01

BMC IO Rising Slew Rate Driving Control Low Byte Register Address Name Bit Type Description Default

0x042D UPTCL 7~0 R/W UPTCL[7:0] Low-byte Timing Control bits for Rising Slew Rate of BMC IO

1: Faster Rising Slew Rate Trim bits is used in BMC IO

0: Slower Rising Slew Rate Trim bits is used in BMC IO

0x80

Notes: The bits of {UPTCH[7:0], UPTCL[7:0]} will be shifted out sequentially per 1 cycle of 16MHz, and the MSB is shifted firstly, to switch between Slower and Faster trim bits inside BMC IO, once the Rising edge of data output is started.

BMC IO Configuration Register Address Name Bit Type Description Default

0x0432 CFG 7~4 R/W Full on timer The time = (n+1)*T

Where T = 1/16M = 62.5ns and n = CFG[7:4] = 0~15

0x50

3~1 RSV Reserved

0 R/W Control mode If 0, timing control

If 1, voltage control (70/30%)

20

A.6.2 Embedded Flash Protection The embedded flash can be divided into three independent regions with arbitrary size and each region can be

configured to be Read or Write protected against access cycles initiated from EC’s CPU, the LPC master(chipset) or the

EDI debug utility. For Read protected region, the data return will be 0xFF. For Write-protected regions, the data written

will be disregarded. The three independent flash regions can be configured in registers EFPSAx, EFPEAx and EFPACx

(where x=0,1,2).

XBI/SPI

Flash

Controller

8KB

Embedded

Flash

8KB Flash Space

0x00000 ~ 0x1FFFF

Protect Region 2

Protect Region 1

Protect Region 0

EDI

PortMCU

StartAddr_2

EndAddr_1

EndAddr_2

StartAddr_1

EndAddr_0

StartAddr_0

EFPSA2EFPEA2

EFPSAx: Protect Region_x Start Address (1KB Aligned, x=0,1,2)

EFPEAx: Protect Region_x End Address (1KB Aligned, x=0,1,2)

EFPACx: Protect Region_x Read/Write Protect Enable corresponding to MCU, EDI respectively

R/W

Protect

R/W

Protect

EFPAC2

Region_2_REG

EFPAC0[6]

WP#

EFPAC1[6]

EFPAC2[6]

Region_1_REG

EFPSA1EFPEA1EFPAC1

Region_0_REG

EFPSA0EFPEA0EFPAC0

MPU

Embedded

Flash

Controller

Embedded Flash Protection Scheme

Each of the protection regions can be locked by hardware signal (WP#) in conjunction with register lock bits. Once

being locked, the respective registers including the lock bit itself can not be altered unless the hardware protection input

signals become deasserted or upon power-on reset occurs.

For Embedded flash Protection Region x (where x=0,1,2):

HW lock by the WP# pin

Locked Registers HW Lock Input Signal Lock Bit

Protection Setting Registers Note1

EFPSAx[7:0]

EFPEAx[7:0]

EFPACx[7:0]

WP# pin attribute related register bits Note2

WP# EFPACx[6]

RW (unlock) x 0

RW (unlock) High x

RO (Locked) Low 1

Note 1: After power-on all the protection registers including the lock bits are cleared to 0x00 (unlocked)

Note 2: The pin attribute register bits including Input Enable, Output Enable, Function Selection, Open-Drain Enable,

Pull-Up Enable, LV- Threshold, Input Data Port, Output data port.

21

A.7 BMC Registers Description

A.7.1 BMC Function Description

A.8.2 BMC Registers Description

BMC Configuration


0x0600 BMCCFG 7~6 RSV Reserved 0x03 or

0x05

Ra

5 R/W Enable SOP Message detect

4 R/W Enable SOP’’_Debug Message detect

3 R/W Enable SOP’_Debug Message detect

2 R/W Enable SOP’’ Message detect

1 R/W Enable SOP’ Message detect

0 R/W Enable BMC Control (When disable don’t driven it)

Preamble SOP* Header Data Object 0~6 CRC EOP

Transmit/ ReceiveMessageInterrupt

BMC Interrupt Enable Address Name Bit Type Description Default

0x0601 BMCIE 7~6 RSV Reserved 0x00

5 R/W Good CRC massage timeout interrupt enable

4 R/W Receive Good CRC massage interrupt enable

3 R/W Hard reset message interrupt enable

2 R/W Cable reset message interrupt enable

1 R/W Transmit message interrupt enable

0 R/W Receive massage interrupt enable

BMC Interrupt Pending Flag Address Name Bit Type Description Default

0x0602 BMCPF 7~6 RSV Reserved 0x00

5 R/W1C Good CRC massage timeout interrupt flag

4 R/W1C Receive Good CRC massage interrupt flag

3 R/W1C Hard reset message event pending flag

2 R/W1C Cable reset message event pending flag

1 R/W1C Transmit message event pending flag

0 R/W1C Receive massage event pending flag

BMC Status Address Name Bit Type Description Default

0x0603 BMCSTS 7 RSV Reserved 0x00

6 R/W1C Rx Bit Error (Over tolerance setting )

5 RO BIST Carrier Mode 2

4 RO BIST Test Data

3 R/W1C Rx length Error

2 R/W1C K-code Error

1 RO Transmitting Good CRC

0 RO CC Bus busy

22

BMC Reset Address Name Bit Type Description Default

0x0604 BMCRST 7~1 RSV Reserved 0x00

0 R/W Reset Tx

BMC Line Filter Address Name Bit Type Description Default

0x0605 BMCLF 7~1 RSV Reserved 0x05

2~0 R/W Line filter timing 0~7 T (T = 1/16MHz)

BMC Tolerance Address Name Bit Type Description Default

0x0606 BMCT 7~3 RSV Reserved 0x03

0~2 R/W Tolerance ±(10+N)%, N= 0, 2, 4, 6, 8, 10 depending on bits[2:0]:

000: N=0. 001: N=2.

010: N=4.

011: N=6 (Default).

100: N=8.

101~111: N=10.

BMC Good CRC Control Message Header Setting Address Name Bit Type Description Default

0x0607 BMCGC 7~4 RSV Reserved 0x05

3 R/W Port Data Role

2 R/W SOP only: Port Power Role

R/W SOP’/SOP’’: Cable Plug

1~0 R/W Specification Revision

BMC Tx Data Count Byte Address Name Bit Type Description Default

0x0610 BMCTXB 7 RSV Reserved 0x00

6~4 R/W Tx message Type 000 : SOP’

001 : SOP”

010 : SOP’_Debug 011 : SOP”_Debug

100: SOP

101: Cable reset 110: Hard reset

1~3 RSV Reserved

0 R/W Start transfer data (Counter byte include in Header bit[14:12] )

BMC TX HEADER High Byte Buffer Address Name Bit Type Description Default

0x0612 BMCTXHH 7~0 R/W BMC TX Header High Byte Buffer

Header[15:8] 0x00

BMC TX HEADER Low Byte Buffer Address Name Bit Type Description Default

0x0613 BMCTXHL 7~0 R/W BMC TX Header Low Byte Buffer Header[7:0]

0x00

BMC TX Data Object 0 Address Name Bit Type Description Default

0x0614 BMCTXD0_3124 7~0 R/W BMC TX Data object 0 bit[31:24] 0x00





23



0x061A BMCTXD1_1508 7~0 R/W BMC TX Data object 1 bit[15:08] 0x00

0x061B BMCTXD1_0700 7~0 R/W BMC TX Data object 1 bit[07:00] 0x00


0x061C BMCTXD2_3124 7~0 R/W BMC TX Data object 2 bit[31:24] 0x00

0x061D BMCTXD2_2316 7~0 R/W BMC TX Data object 2 bit[23:16] 0x00

0x061E BMCTXD2_1508 7~0 R/W BMC TX Data object 2 bit[15:08] 0x00

0x061F BMCTXD2_0700 7~0 R/W BMC TX Data object 2 bit[07:00] 0x00














0x062A BMCTXD5_1508 7~0 R/W BMC TX Data object 5 bit[15:08] 0x00

0x062B BMCTXD5_0700 7~0 R/W BMC TX Data object 5 bit[07:00] 0x00


0x062C BMCTXD6_3124 7~0 R/W BMC TX Data object 6 bit[31:24] 0x00

0x062D BMCTXD6_2316 7~0 R/W BMC TX Data object 6 bit[23:16] 0x00

0x062E BMCTXD6_1508 7~0 R/W BMC TX Data object 6 bit[15:08] 0x00

0x062F BMCTXD6_0700 7~0 R/W BMC TX Data object 6 bit[07:00] 0x00

BMC Rx Data Count Byte Address Name Bit Type Description Default

0x0630 BMCRXB 7 RSV Reserved 0x00

6~4 RO Rx message Type 000 : SOP’

001 : SOP”

010 : SOP’_Debug 011 : SOP”_Debug

100: SOP

101: Cable reset 110: Hard reset

3 RSV Reserved

2~0 RO Rx data counter (unit 32 bit)

BMC RX HEADER High Byte Buffer Address Name Bit Type Description Default

0x0632 BMCRXHH 7~0 R/W BMC RX Header High Byte Buffer

Header[15:8] 0x00

24

BMC RX HEADER Low Byte Buffer Address Name Bit Type Description Default

0x0633 BMCRXHL 7~0 RO BMC RX Header Low Byte Buffer

Header[7:0] 0x00

BMC RX Data Object 0 Address Name Bit Type Description Default

0x0634 BMCRXD0_3124 7~0 RO BMC RX Data object 0 bit[31:24] 0x00







0x063A BMCRXD1_1508 7~0 RO BMC RX Data object 1 bit[15:08] 0x00

0x063B BMCRXD1_0700 7~0 RO BMC RX Data object 1 bit[07:00] 0x00


0x063C BMCRXD2_3124 7~0 RO BMC RX Data object 2 bit[31:24] 0x00

0x063D BMCRXD2_2316 7~0 RO BMC RX Data object 2 bit[23:16] 0x00

0x063E BMCRXD2_1508 7~0 RO BMC RX Data object 2 bit[15:08] 0x00

0x063F BMCRXD2_0700 7~0 RO BMC RX Data object 2 bit[07:00] 0x00














0x064A BMCRXD5_1508 7~0 RO BMC RX Data object 5 bit[15:08] 0x00

0x064B BMCRXD5_0700 7~0 RO BMC RX Data object 5 bit[07:00] 0x00


0x064C BMCRXD6_3124 7~0 RO BMC RX Data object 6 bit[31:24] 0x00



0x064F BMCRXD6_0700 7~0 RO BMC RX Data object 6 bit[07:00] 0x00

BMC RX GoodCRC HEADER High Byte Buffer Address Name Bit Type Description Default

25

0x0650 BMCRXGCHH 7~0 RO BMC RX GoodCRC Header High Byte Buffer

Header[15:8] 0x00

BMC RX GoodCRC HEADER Low Byte Buffer Address Name Bit Type Description Default

0x0651 BMCRXGCHL 7~0 RO BMC RX GoodCRC Header Low Byte Buffer

Header[7:0] 0x00

26

A.8 MISC Registers Description

Hardware Revision


0x0500 HWVER 7-0 RO Hardware version 0xAF

Firmware Revision Address Name Bit Type Description Default

0x0501 FWVER 7-0 R/W Firmware version 0x00

PMU Control/Configuration Address Name Bit Type Description Default


0x0502 PMUCFG 7 WO Write “1” to enter STOP mode. 0x07

6 WO Write “1” to enter Idle mode.

5 RSV Reserved

4 R/W Reset 8051 in STOP mode.

3 RSV Reserved

2 R/W WDT wakeup system from STOP mode.

1 R/W GPWU wakeup system from STOP mode.

0 R/W Interrupt wakeup system from Idle mode.

EC Clock Configuration Address Name Bit Type Description Default

0x0503 CLKCFG 7-5 RSV Reserved 0x00

4 R/W ADCO enters into low power state while in STOP mode. 0: Disable 1: Enable

3-0 RSV Reserved

ADCO Initial value High Byte Configuration Address Name Bit Type Description Default

0x0504 ADCOIHB 7-2 RSV Reserved

1-0 R/W ADCO initial value. (High 2-bit)

Note the programming sequence must be programming the ADCOIHB

first, and then followed by programming the ADCOILB

0x00

ADCO Initial value Low Byte Configuration Address Name Bit Type Description Default

0x0505 ADCOILB 7-0 R/W ADCO initial value. (Low 8-bit)

Note the programming sequence must be programming the ADCOIHB first, and then followed by programming the ADCOILB

0x40

Clock Configuration2 Address Name Bit Type Description Default

0x0506 CLKCFG2 7-0 R/W (ADCO Freq)/( CLKCFG2+1) to generate 1μs

Eg: ADCO outputs 16MHz (by default), to generate 1μs, the CLKCFG2 should be 0x0F.(CLKCFG2 =0x0F).

0x0F

EC 8051 On-Chip Control Address Name Bit Type Description Default

0x0507 PXCFG 7-5 RSV Reserved 0x00

0 R/W 8051 program counter control 0: program counter starts to execute.

1: 8051 reset and PC=0

PC will keep 0 (reset vector) until this bit is written to “0”

CHIP ID High byte


0x0508 CHIPIDH 7-0 RO CHIPID high byte. 0x03

CHIP ID Low byte


0x0509 CHIPIDL 7-0 RO CHIPID low byte. 0x62

Embedded Debug Verison ID Address Name Bit Type Description Default

0x050A EDIID 7-0 RO EDI version 0x09

27

Embedded Debug Interface I2C Feature Register


0x050B EDI2C 7 RW EDI I2C Slave function enable 0:Disable 1: Enable (Default)

0x80

6~0 RO Error Code

04h: EDI_SPI active

02h: CMD Error

01h: Protocol Error.

The Expected Data is not equal to Actual Data. 00h: No Error

Embedded Debug Interface I2C Slave Address


0x050C EDI2CADR 7-0 R/W EDI I2C Slave Address Bit0 is ignored

0xC8

*(EDII2C always can wakeup)

*(EDIBMC always can wakeup)

8051 Serial Port Data Logging for Debug


0x050D SEDI 7 R/W1C 8051 serial port data logging FIFO full pending flag 0: no event 1: event occurs

0x00

6~2 RSV Reserved

1 R/W Action to take when FIFO Full condition occurs

When the data logging FIFO is full, either the 8051 serial port can be

suspended from writting into the FIFO or the FIFO can be overwritten

circularly with new data 0: Suspend the 8051 1: Overwrite FIFO

0 R/W Enable serial port data logging function


*New Serial port Tx

POF Debounce Time Address Name Bit Type Description Default

0x050E POFDT 7~4 RSV Reserved 0x07

3~0 R/W POF debounce time

1xxx: 0us

0111: 2us

0110: 6us

0100: 14us

0000: 30us

Macro Standby Configuration Address Name Bit Type Description Default

0x050F MARSTC 7~1 RSV Reserved 0x00

0 R/W LDO standby enable

Trade-off for leakage current and LDO, about 26uA

Ra Pin Status Address Name Bit Type Description Default

0x0510 RAPS 7-2 RSV Reserved 0x00

1 RO VCONNB Ra Pin Status

0 RO VCONNA Ra Pin Status

Trap Status Address Name Bit Type Description Default

0x0511 TRAPSTA 7-0 RO 0x00

Serial Port Tx Enhance Mode Control Address Name Bit Type Description Default

0x0512 SPTXEMC 7-2 RSV Reserved 0x00

1 R/W Holding FIFO (holding read pointer)

0: Disable 1: Enable (FIFO will not be changed)

0 R/W Tx enhance mode enable 0: Disable 1: Enable

28

Serial Port Tx /Rx Status Address Name Bit Type Description Default

0x0513 SPTXRXS 7-4 RSV Reserved 0x00

3 RO Rx busy flag 0: Idle 1: Busy

2 RO Tx busy flag

0: Idle 1: Busy

1 W1C Tx FIFO overwrite event flag 0: No event 1: Event

0 RO Tx FIFO status

0: No full 1: Full

29

CHIP ID

CHIP ID High byte Address Name Bit Type Description Default

0x4000 CHIPIDH 7-0 RO CHIPID high byte. Note the programming sequence must be programming the CHIPIDL

first, and then followed by programming the CHIPIDH

0x03

CHIP ID Low byte


0x4001 CHIPIDL 7-0 RO CHIPID low byte. Note the programming sequence must be programming the CHIPIDL

first, and then followed by programming the CHIPIDH

0x62

30

A.10 8051 Microprocessor

8051 Microprocessor Function Description The Microprocessor embedded is an industrial compatible i8051. The 8051 features 128bytes Special Function

Register (SFR), Serial port, two 16-bit Timers and three I/O ports with interrupt capability. T The following figure gives

an illustration of the 8051 architecture. Except the standard 128bytes SFR, 8051 is designed with overall 256 bytes

internal memory.

8051 Microprocessor Instruction The instruction set of 8051 microprocessor is fully compatible with industrial i8051as listed in the following table,

where:

OpCode: in Hexadecimal format and \ (b) means Binary.

Byte: stands for byte number of the instruction.

Cycle: stands for number of cycle needed to complete the instruction.

Arithmetic

Mnemonic OP code Byte Cycle Description

ADD A, #data 24 2 2 Add immediate data to Accumulator

ADD A, direct 25 2 2 Add direct byte to Accumulator

ADD A, @ RN 26~27 1 2 Add indirect RAM to Accumulator (@R0~R1, OP 0x26~0x27)

ADD A, RN 28~2F 1 2 Add register to Accumulator (R0~R7, OP 0x28~0x2F)

ADDC A, #data 34 2 2 Add immediate data to Accumulator with Carry

ADDC A, direct 35 2 2 Add direct byte to Accumulator with Carry

ADDC A, @ RN 36~37 1 2 Add indirect RAM to Accumulator with Carry (@R0~R1, OP 0x26~0x27)

ADDC A, RN 38~3F 1 2 Add register to Accumulator with Carry (R0~R7, OP 0x38~0x3F)

SUBB A, #data 94 2 2 Subtract immediate data from ACC with Borrow

SUBB A, direct 95 2 2 Subtract direct byte from ACC with Borrow

SUBB A, @ RN 96~97 1 2 Subtract indirect RAM from ACC with Borrow (R0~R1, OP 0x96~0x97)

SUBB A, RN 98~9F 1 2 Subtract register from Accumulator with Borrow (R0~R7, OP 0x98~0x9F)

INC A 04 1 2 Increment Accumulator

INC direct 05 2 2 Increment direct byte

INC @ RN 06~07 1 2 Increment indirect RAM (R0~R1, OP 0x06~0x07)

INC RN 08~0F 1 2 Increment Register (R0~R7, OP 0x08~0x0F)

DEC A 14 1 2 Decrement Accumulator

DEC direct 15 2 2 Decrement direct byte

DEC @ RN 16~17 1 2 Decrement indirect RAM (R0~R1, OP 0x16~0x17)

DEC RN 18~1F 1 2 Decrement Register (R0~R7, OP 0x18~0x1F)

INC DPTR A3 1 2 Increment Data Pointer

MUL AB A4 1 2 Multiply A & B

DIV AB 84 1 2 Divide A by B

DA A D4 1 2 Decimal Adjust Accumulator

Logic & Byte Operation


ANL direct, A 52 2 2 AND Accumulator to direct byte

ANL direct, #data 53 3 2 AND immediate data to direct byte

ANL A, #data 54 2 2 AND immediate data to Accumulator

ANL A, direct 55 2 2 AND direct byte to Accumulator

ANL A, @ RN 56~57 1 2 AND indirect RAM to Accumulator (R0~R1, OP 0x56~0x57)

31

ANL A, RN 58~58 1 2 AND Register to Accumulator (R0~R7, OP 0x58~0x5F)

ORL direct, A 42 2 2 OR Accumulator to direct byte

ORL direct, #data 43 3 2 OR immediate data to direct byte

ORL A, #data 44 2 2 OR immediate data to Accumulator

ORL A, direct 45 2 2 OR direct byte to Accumulator

ORL A, @ RN 46~47 1 2 OR indirect RAM to Accumulator (R0~R1, OP 0x46~0x47)

ORL A, RN 48~4F 1 2 OR Register to Accumulator (R0~R7, OP 0x48~0x4F)

XRL direct, A 62 2 2 XOR Accumulator to direct byte

XRL direct, #data 63 3 2 XOR immediate data to direct byte

XRL A, #data 64 2 2 XOR immediate data to Accumulator

XRL A, direct 65 2 2 XOR direct byte to Accumulator

XRL A, @ RN 66~67 1 2 XOR indirect RAM to Accumulator (R0~R1, OP 0x66~0x67)

XRL A, RN 68~6F 1 2 XOR Register to Accumulator (R0~R7, OP 0x68~0x6F)

CLR A E4 1 2 Clear Accumulator

CPL A F4 1 2 Complement Accumulator

RL A 2 3 1 2 Left rotate Accumulator

RLC A 3 3 1 2 Left rotate Accumulator through Carry

RR A 0 3 1 2 Right rotate Accumulator

RRC A 1 3 1 2 Right rotate Accumulator through Carry

SWAP A C 4 1 2 Swap Accumulator Nibbles

Data Movement


MOV A, RN E8~EF 1 2 Move Register to Accumulator (R0~R7, OP 0xE8~0xEF)

MOV A, direct E5 2 2 Move direct byte to Accumulator

MOV A, @ RN E6~E7 1 2 Move indirect RAM to Accumulator (R0~R1, OP 0xE6~0xE7)

MOV A, #data 74 2 2 Move immediate data to Accumulator

MOV RN, A F8~FF 1 2 Move Accumulator to Register (R0~R7, OP 0xF8~0xFF)

MOV RN, direct A8~AF 2 2 Move direct byte to Register (R0~R7, OP 0xA8~0xAF)

MOV RN, #data 78~7F 2 2 Move immediate data to Register (R0~R7, OP 0x78~0x7F)

MOV direct, A F5 2 2 Move Accumulator to direct byte

MOV direct, @ RN 86~87 2 2 Move indirect RAM to direct byte (R0~R1, OP 0x86~0x87)

MOV direct, RN 88~8F 2 2 Move Register to direct byte (R0~R7, OP 0x88~0x8F)

MOV direct, #data 75 3 2 Move immediate data to direct byte

MOV direct, direct 85 3 2 Move direct byte to direct byte

MOV @ RN, direct A6~A7 2 2 Move direct byte to indirect RAM (R0~R1, OP 0xA6~0xA7)

MOV @ RN, A F6~F7 1 2 Move Accumulator to indirect RAM (R0~R1, OP 0xF6~0xF7)

MOV @ RN, #data 76~77 2 2 Move immediate to indirect RAM (R0~R1, OP 0x76~0x77)

MOV DPTR,#data16 90 3 2 Load Data Pointer with a 16bit constant

MOVC A,@ A+PC 83 1 >33 Move Code byte relative to PC to Accumulator

MOVC A,@ A+DPTR 93 1 >33 Move Code byte relative to DPTR to Accumulator

MOVX A, @ DPTR E0 1 >=5 Move External RAM to Accumulator

MOVX A, @ RN E2~E3 1 >=5 Move External RAM to Accumulator (R0~R1, OP 0xE2~0xE3)

MOVX @ DPTR, A F0 1 >=4 Move Accumulator to External RAM

MOVX @ RN, A F2~F3 1 >=4 Move Accumulator to External RAM (R0~R1, OP 0xF2~0xF3)

POP direct D0 2 2 POP direct byte from Stack

PUSH direct C0 2 2 Push direct byte to Stack

XCH A, direct C 5 2 2 Exchange direct byte with Accumulator

XCH A, @ RN C6~C7 1 2 Exchange indirect RAM with Accumulator (R0~R1, OP 0xC6~0xC7)

XCH A, RN C8~CF 1 2 Exchange Register with Accumulator (R0~R7, OP 0xC8~0xCF)

XCHD A, @ RN D6~D7 1 2 Exchange low order nibble of indirect RAM with Accumulator (R0~R1, OP 0xD6~0xD7)

Bit Operation


SETB bit D2 2 2 Set direct bit

SETB C D3 1 2 Set Carry

CLR bit C2 2 2 Clear direct bit

CLR C C3 1 2 Clear Carry

CPL bit B2 2 2 Complement direct bit

CPL C B3 1 2 Complement Carry

ANL C, bit 82 2 2 AND direct bit to Carry

ANL C, /bit B0 2 2 AND complement of direct bit to Carry

ORL C, bit 72 2 2 OR direct bit to Carry

ORL C, /bit A0 2 2 OR complement of direct bit to Carry

MOV C, bit 92 2 2 Move direct bit to Carry

MOV bit, C A2 2 2 Move Carry to direct bit

JC relative 4 0 2 2 Jump if Carry is set

JNC relative 5 0 2 2 Jump if Carry is NOT set

JB bit, relative 2 0 3 2 Jump if direct bit is set

JBC bit, relative 1 0 3 2 Jump if direct bit is set & clear bit

32

JNB bit, relative 3 0 3 2 Jump if direct bit is NOT set

Program Branching


ACALL address11 bbb1 0001 2 3 Absolute sub-routine call

AJMP address11 bbb0 0001 2 2 Absolute jump

LCALL address16 12 3 3 Long sub-routine call

LJMP address16 02 3 2 Long jump

SJMP relative 80 2 2 Short jump (relative address)

JMP @ A+DPTR 73 1 2 Jump indirect relative to the DPTR

JNZ relative 70 2 2 Jump if Accumulator is NOT zero

JZ relative 60 2 2 Jump if Accumulator is zero

CJNE A, #data, relative B4 3 2 Compare immediate to Accumulator and Jump if NOT equal

CJNE A, direct, relative B5 3 2 Compare direct byte to Accumulator and Jump if NOT equal

CJNE @ RN, #data, relative

B6~B7 3 2 Compare immediate to indirect and Jump if NOT equal (R0~R1, OP 0xB6~0xB7)

CJNE RN, #data, relative B8~BF 3 2 Compare immediate to Register and Jump if NOT equal

(R0~R7, OP 0xB8~0xBF)

DJNZ direct, relative D5 3 2 Decrement direct byte and Jump if NOT zero

DJNZ RN, relative D8~DF 2 2 Decrement register and Jump if NOT zero (R0~R7, OP 0xD8~0xDF)

RET 22 1 3 Return from sub-routine

RETI 32 1 3 Return form interrupt

Special Instruction


NOP 00 1 2 No Operation

8051 Interrupt Controller In order to support more applications, the 8051 in IO362 extends interrupt channel to 24 for internal peripherals.

Consequently, I/O port P0, P1 and P3 are with interrupt capability in IO362. The interrupt priority for each channel is

fixed and no nested interrupt is supported. Please refer to the following table for summary of the implementation of

interrupt controller.

Int. Source Vector Address Applications Priority

IE0 0x0003 8051 external interrupt 0 0(Highest)

TF0 0x000B 8051 Timer 0 1

IE1 0x0013 8051 external interrupt 1 2

TF1 0x001B 8051 Timer 1 3

RI & TI 0x0023 8051 Serial Port interrupt 4

P0I[0] 0x0043 WDT 5

P0I[1] 0x004B BMC 6

P0I[2] 0x0053 FSMBus 7

P0I[3] 0x005B GPIO0x 8

8051 Special Function Register (SFR) The 128-byte Special Function Registers (SFR) are located in the internal RAM of 8051ranging from 0x80 to 0xFF.

The SFRs are compatible with industry standard with some additional new features as described below:

P3IE, P1IE, P0IE in the original industry standard 8051 are 8-bit I/O port registers. For the embedded 8051 in EC,

they are used as Interrupt Enable (IE) registers corresponding to their respective inputs where a valid interupt being a

rising-edge pulse with one clock width. The overall interrupt events are 24.

P3IF, P1IF, P0IF are Interrupt Flag (IF) corresponding to the 24 interrupt inputs. The three IFs are set by external

interrupt event (a rising-edge pulse with one clock width) and are cleared by software upon the completion of exeution of

the IRET instruction at the end of the interrupt service routine. For details, please refer to SFR register description.

PCL, PCH, INST1, INST2 INST3 are used by the ENE EDI tool to identify the current program counter values

and instructions being processed.

PCL and PCH are Program Counter value. PCL is the low-byte and PCH is the high-byte. INST1, INST2 and

INST3 are Instruction bytes. For One-byte instruction, only INST1 is valid. For two-byte instruction, only [INST2:

INST1] are valid. For three-byte instruction, [INST3:INST2:INST1] are valid.

33

80 P0IE SP DPL DPH IVHA PCON2 PCON 87

88 TCON TMOD TL0 TL1 TH0 TH1 PCL PCH 8F

90 P1IE 97

98 SCON SBUF SCON2 SCON3 SCON4 INST1 INST2 INST3 9F

A0 P2 A7

A8 IE AF

B0 P3IE B7

B8 IP BF

C0 SHA1_CTRL C7

C8 CF

D0 PSW D7

D8 P0IF DF

E0 ACC E7

E8 P1IF EF

F0 B F7

F8 P3IF FF

★

1. The SFRs in blue color are new additions which are not in the industry-standard ones

2. The SFRs in green color are new additions which are not in the industry-standard ones

3. The registers listed in the column with ★mark are all bit addressable.

8051 Microprocessor Register Description

The SFR registers are located at internal RAM 0x80 ~ 0xFF.

P0 Interrupt Enable Register Address Name Bit Type Description Default

0x80 P0IE 7-0 R/W P0 interrupt enable. Bit0~7 for P0[0]~P0[7] respectively.


0x00

Stack Pointer Address Name Bit Type Description Default

0x81 SP 7-0 R/W 8051 stack pointer register 0x07

Data Pointer Low Byte Address Name Bit Type Description Default

0x82 DPL 7-0 R/W Low byte of DPTR 0x00

Data Pointer High Byte Address Name Bit Type Description Default

0x83 DPH 7-0 R/W High byte of DPTR 0x00

Interrupt Vector High Address Address Name Bit Type Description Default

0x85 IVHA 7-3 R/W Interrupt Vector High Address Setting:

Interrupt Vector = { IVHA, 3’b0 } + Original_Vector_Address

0x00

2-0 RSV Reserved

Processor Control Register 2 Address Name Bit Type Description Default

0x86 PCON2 7 R/W This bit must be “0”. 0x30

6 R/W Timer0/Timer1 test mode enable. 0: Disable 1: Enable

5 R/W This bit must be “1”

4 R/W KBC modules write control.

Once this bit set, 8051 could issue write access to external modules. 0: Disable 1: Enable(default)

3 R/W0C Same interrupt source pending flag.

If the 8051 is handling some interrupt event and the same source is asserting the interrupt again at the same time, this flag will be set. If this flag set, the

8051 will re-enter ISR again once executing IRET. Write “0” to clear this

flag.

2 RSV Reserved

1 R/W E51 Timer select 1us

0 RSV Reserved

34

Processor Control Register


0x87 PCON 7 RSV Reserved 0x00

6 RSV Reserved

5 RSV Reserved

4 RSV Reserved

3 R/W General purpose flag 1

0: no event 1: event occurs

2 R/W General purpose flag 2


1 WO Stop mode enable.

All clock stop except the external 32.768K OSC and PCICLK. 1: Enable (write “0” no work)

0 WO Idle mode enable.

The clock of 8051 stops. 1: Enable (write “0” no work)

Timer/Counter Control Register


0x88 TCON 7 R/W0C TF1, Timer1 overflow flag 0: no event 1: event occurs

0x00

6 R/W TR1, Timer1 start control.

0: stop to count 1: start to count

5 R/W0C TF0, Timer0 overflow flag 0: no event 1: event occurs

4 R/W TR0, Timer0 start control.

0: stop to count 1: start to count

3 R/O IE1, External interrupt 1 flag 0: no event 1: event occurs

2 R/W IT1, External interrupt 1 trigger selection

0: low level trigger 1: falling edge trigger

1 R/O IE0, External interrupt 0 flag 0: no event 1: event occurs

0 R/W IT0, External interrupt 0 trigger selection

0: low level trigger 1: falling edge trigger

Timer Mode Register Address Name Bit Type Description Default

0x89 TMOD 7 R/W GATE1, this bit is the gate control of TR1 and INT1


0x00

6 R/W CT1, Timer1 timer/counter selection

0: Timer 1: Counter

5-4 R/W TM1, Timer1 mode selection 0: 13-bit timer 1: 16-bit timer

2: 8-bit auto reload timer 3: Timer 1 stops.

3 R/W GATE0, this bit is the gate control of TR0 and INT0


2 R/W CT0, Timer0 timer/counter selection

0: Timer 1: Counter

1-0 R/W TM0, Timer0 mode selection 0: 13-bit timer 1: 16-bit timer

2: 8-bit auto reload timer 3: TL0 and TH0 are two 8-bit timers.

Timer 0 Low Byte Address Name Bit Type Description Default

0x8A TL0 7-0 R/W Low byte of timer 0 0x00

Timer 1 Low Byte Address Name Bit Type Description Default

0x8B TL1 7-0 R/W Low byte of timer 1. 0x00

Timer 0 High Byte


0x8C TH0 7-0 R/W High byte of timer 0 0x00

Timer 1 High Byte Address Name Bit Type Description Default

0x8D TH1 7-0 R/W High byte of timer 1 0x00

35

Port1 Interrupt Enable Register Address Name Bit Type Description Default

0x90 P1IE 7-0 R/W Port 1 interrupt enable. Bit0~7 for P1[0]~P1[7] respectively 0: Disable 1: Enable

0x00

Serial Port Control Register Address Name Bit Type Description Default

0x98 SCON 7-6 R/W SM1,SM0, serial port mode

00: 8-bit shift register, E51RX will be the shift clock of E51CLK. 01: 8-bit serial port (variable)

10: 9-bit serial port (variable)

11: 9-bit serial port (variable)

0x50

5 RSV Reserved

4 R/W REN, serial port receive function enable.


3 R/W TB8, The 9th bit of transmitted data in mode2 and mode3.

2 R/W RB8, The 9th bit of receive data

1 R/W0C TI, TX interrupt flag


0 R/W0C RI, RX interrupt flag 0: no event 1: event occurs

Serial Port Data Buffer Register Address Name Bit Type Description Default

0x99 SBUF 7-0 R/W Serial port data buffer 0x00

Serial Port Control Register 2 Address Name Bit Type Description Default

0x9A SCON2 7-0 R/W High byte of 16-bit counter for baud rate (Based on 16MHz clock) 0x00


0x9B SCON3 7-0 R/W Low byte of 16-bit counter for baud rate (Based on 16MHz clock) 0x00


0x9C SCON4 7-2 RSV Reserved 0x00

1~0 R/W Serial Port mode 0 baud- rate setting

00: 8MHz 01: 4MHz 10: 2MHz 11: 1MHz

Port 2 Register Address Name Bit Type Description Default

0xA0 P2 7-0 R/W Port 2 register 0x00

Interrupt Enable Register Address Name Bit Type Description Default


0xA8 IE 7 R/W EA, all interrupts enable. 0: Disable 1: Enable

0x40

6 R/W EP, Change P0IF, P1IF, P3IF Interrupt event trigger flag to Interrupt event

pending flag

5 RSV Reserved

4 R/W ES, serial port interrupt enable

3 R/W ET1, timer1 overflow interrupt enable

2 R/W EX1, external interrupt 1 enable.

1 R/W ET0, timer0 overflow interrupt enable

0 R/W EX0, external interrupt 0 enable.

Interrupt Enable Register


0xB0 P3IE 7-0 R/W Port 3 interrupt enable. Bit0~7 for P3[0]~P3[7] respectively


0x00

Interrupt Priority Register Address Name Bit Type Description Default

0xB8 IP 7-5 RSV Reserved 0x00

4 R/W Serial port interrupt priority

36

0: Low 1: High

3 R/W Timer1 interrupt priority

0: Low 1: High

2 R/W External interrupt 1 priority

0: Low 1: High

1 R/W Timer 0 interrupt priority

0: Low 1: High

0 R/W External interrupt 0 priority

0: Low 1: High

Processor Status Word Register Address Name Bit Type Description Default

0xD0 PSW 7 R/W CY, carry flag 0x00

6 R/W AC, auxiliary carry flag.

5 R/W F0, for user general purpose.

4 R/W RS1, register bank selector 1.

3 R/W RS0, register bank selector 0.

2 R/W OV, overflow flag

1 R/W F1, flag 1 for user general purpose

0 R/W P, parity flag

Port0 Interrupt Flag Register Address Name Bit Type Description Default

0xD8 P0IF 7-0 R/W Port 0 interrupt flag. 0x00

Accumulator, ACC Address Name Bit Type Description Default

0xE0 ACC 7-0 R/W Accumulator 0x00


0xE8 P1IF 7-0 R/W Port 1 interrupt flag. 0x00

B Register Address Name Bit Type Description Default

0xF0 B 7-0 R/W B register, for MUL and DIV instructions. 0x00


0xF8 P3IF 7-0 R/W Port 3 interrupt flag. 0x00

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