INTRODUCTION TO IO BUFFERS (PADS) DESIGN IN

IC COMMUNICATIONS

VENKATA REDDY KOLAGATLA Senior Technical Officer , CDAC Bangalore

Topics going to be covered • Basic Block diagram of IO communication & Introduction to IOs

• Buffered Vs Unbuffered

• Basics RC Circuits

• Drive Strength Requirements

• Output buffer/Driver/Transmitter design

• Signal Integrity Analysis – Transmission Lines

• Basic input buffer/Receiver design

• A new project design methodology

• Further study on IOs

• Questions/References/Appendix

Basic block diagram of IO Communication & Introduction to IOs

Generic Diagram of IO communication (IC to IC Communication)

Printed Wiring Board

Buffers

pack

age

pack

age

Receiver

Data

genera

tor

CMOS IC1 CMOS IC2

Introduction to IOs • Input/Output (IO) circuits enable a chip to communicate with the

external world.

• They are placed at the periphery of a chip and provide an interface between the chip and the external world.

• As the internal circuitry grows in speed and efficiency, it processes data faster.

• Matching IO circuits, in terms of speed and bandwidth, are critical to make sure that the processing power and efficiency of the internal circuitry or the core circuitry is best used.

• The electrical signal outside the chip is unknown and possibly unsafe for the internal circuitry.

• IOs help isolate the chip from such an environment and helps convert the external signal to a form where the internal circuit can process it.

Why I/O Buffers • The term ‘buffer’ is used alternately for “IO”, since IOs does not

perform any logic operation on the signals!!

• Properly drive different loads

• Get clean (less noisy) signal from incoming noisy signal

• Provide proper interface between ICs with different signal levels

• Isolate internal circuit from external effects

• Translate incoming/outgoing signal level to the required internal/external signal level

Types of IOs

• Depending on the type of application or direction of data flow, IOs can be classified into different types.

• Input

• Output (2 states or 3 states)

• Bi – directional

Input Buffer

• The input buffer passes external data to the core.

• It performs the level conversion from the external voltage to the core voltage level.

• It helps improve the signal by performing some kind of signal conditioning.

• ESD diodes associated with the input buffer help protect Integrated circuit (IC) chips from damage due to ESD events.

VCC

VSS

PAD To Internal

circuitry

Output Buffer

• The output buffer passes data from the core to the external world which is usually another component on the Printed Circuit Board (PCB) through a track.

• It performs level conversion from the core level voltage to the IO level output voltage (the motherboard voltage level).

• Output buffers can be either 2-state or 3-state depending on the application. For a 3-state buffer, the three states are logic low, logic high and high impedance.

• A 3-state buffer will have an enable signal which facilitates achieving high impedance (Hi-Z) at the PAD

• ESD diodes associated with the output buffer also help protect ICs from damage due to ESD events.

VCC

VSS

PAD

From Internal

circuitry

From Internal

circuitry

Bi-directional Buffer

• A bi-directional buffer functions as both an input and an output buffer.

• The enable signal which comes from the core determines if the buffer needs to be configured as an input buffer or an output buffer.

• It is designed such that when enabled as an input buffer, the PAD is at a high impedance state.

• There can be designs where both an input and an output buffer have separate enable signals.

PAD

From Internal

circuitry

From Internal

circuitry

VCC

VSS

To Internal

circuitry

Buffered Vs Unbuffered

Buffered Vs Unbuffered

Characteristics Buffered Unbuffered

Propagation Delay High Low

Noise Immunity/Margin Excellent Good

Output Impedance Constant Variable

Output transition time Constant Variable

Output oscillation for slow inputs Yes No

Input Capacitance Low High

Basics of RC circuits

Low Pass RC – Circuit : Square Wave Input

If T >>RC If T = RC If T << RC

RC Charging Table – Low Pass RC

Time Constant RC Value % of maximum

Voltage Current

0.5 time constant 0.5T = 0.5RC 39.30% 60.70%

0.7 time constant 0.7T = 0.7RC 50.30% 49.70%

1.0 time constant 1T = 1RC 63.20% 36.80%

2.0 time constants 2.0T = 2.0RC 86.50% 13.50%

2.2 time constants 2.2T = 2.2RC 90% 10.30%

3.0 time constants 3.0T = 3.0RC 95.00% 5.00%

4.0 time constants 4.0T = 4.0RC 98.20% 1.80%

5.0 time constants 5.0T = 5.0RC 99.30% 0.70%

If Period = 10RC

If Period = 16RC

If Period = 4RC

Output Buffer/Driver/Transmitter Design

Progressive Sizing – Pre Driver requirement

• We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter

• The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.

• So this results in slow rise or fall times .

• A unit inverter can drive approximately an inverter that's 4 times bigger in size.

• So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap.

• This is the prime reason behind going for progressive sizing.

Drive Strength Calculations

• Let us say 1.2v, with 1Gbps to drive 5pF load

• Assume that a minimum of 25ohm drive strength is required

• So, (*** R , Idrive , R α 1/width of the transistor α 1/Idrive )

𝐼 =𝑉𝑐𝑐𝑞−𝑉𝑐𝑐𝑞/2

𝑅 =

1.2/2

25 = 24mA

• Let us say per micron width of a pmos transistor Idrive = 48uA, and per micron width of a nmos transistor Idrive = 24uA, total of 500u is required in pull up and 250u required in pull down to achieve 25ohm drive strength.

• According to GDR(Geometric Design Rules), a transistor should not exceed a 10u(assume) width in a particular technology.

• So we have to connect such type of transistors in parallel as many needed accordingly, in order to get the specified drive strength.

Typical Driver Design

VCC

VSS

PAD

From Internal

circuitry

From Internal

circuitry

500u

250u

Typically length would depend on the technology node – It is better to have maximum length such that it should have less leakage. Now -> tri-state control? -> PVT control ? -> Design of diff. types of drive strengths? -> drive strength calculated at Vcc/2, why? - Due to dynamic variations of MOS transistor ON resistance

Signal Integrity Analysis – Transmission Lines

Signal Integrity Definitions

• How the electrical properties of the interconnects could distort the beautiful, pristine signals from the chips

• Purpose of an interconnect: “to transport a signal from one point to another with an acceptable level of distortion”

• Signal integrity problems occur when the interconnects are no longer electrically transparent.

Signal integrity problems

• Signal quality of one net: reflections and distortions from impedance discontinuities in the signal or return path

• Cross talk between multiple nets: mutual C and mutual L coupling

• Power integrity: noise in the power distribution system (PDS): voltage drop across impedance in the pwr/gnd network

• EMI from a component or the system

Basic Definitions

• A transmission line consists of

• A signal line which carries the signal current

• A signal return line (mostly ground) which carries a return current of the same magnitude.

• Any DC interconnect between the GND terminals of the two circuits(e.g. safety earth) will not provide a signal return path according to the transmission line theory!!

• The area between signal line and return lines determines the capability of the circuit to radiate and also its immunity against EMI.

Waveforms with transmission lines and capacitive loads

Consideration of t - line

• The transmission line theory has to be applied, when the rise time of the signal is shorter than twice the propagation time.

• Example 1 : Twisted pair cable; τ = 5 ns/m ; tr = 2 ns

• Example 2 : Bus Line; t = 20 ns/m ; tr = 2 ns

• Max. lengths calculated below for which the length considered as lumped model only. If it crosses the calculated length we must consider it as a distributed mode.

• With shorter signal lines all line reflections occur during the rise/fall time of the signal. In this case it is allowed to use the simplified capacitive load line model.

Signals launch on t - line

• Consider the simple circuit that contains source voltage VS, source

resistance RS, and resistive load RL.

• The output voltage, VL is easily calculated from the source amplitude

and the values of the two series resistors.

RS

RL VS VL

RS

RL

RL

VS

VL

+ =

Transmission Lines - Reflections

Analysis of line reflections

• Signal on a transmission line can be analyzed by keeping track of and adding reflections and transmissions from the “bumps” (discontinuities)

• Characteristic impedance is the ratio of the voltage and current waves at any one position on the transmission line

I

VZ 0

Reflection coefficient definitions

r

1+r Incident

Reflected

Transmitted

Special Cases to Remember

1 +

-

Zo

Zo r

0 +

-

Zo Zo

Zo Zo r

1 0

0 -

+

-

Zo

Zo r

Vs

Zs Zo Zo

A: Terminated in Zo

Vs

Zs Zo

B: Short Circuit

Vs

Zs Zo

C: Open Circuit

Terminations

Termination definitions

• Now the question is how to reduce the voltage/current reflections

• Line reflections are eliminated by correct line terminations

• Properly terminating the trace will reduce voltage reflections.

• There are two general strategies for transmission line termination:

• Match the load impedance to the line impedance (Far End Termination)

• Match the source impedance to the line impedance (Near End Termination)

• From a systems design perspective, the first strategy is preferred, since it eliminates any reflections travelling back to the source, thus resulting in less noise and electromagnetic interference (EMI).

• from a practical standpoint, either of the two techniques can be used, depending on the system under design.

Termination Techniques • There are three basic types of terminations:

• Series Termination (Near End)

• Pull-up/Pull-down Termination (Far End)

• Parallel AC Termination (Far End)

• Parallel AC termination is usually not recommended for clock generators, since it degrades the rise time of the output clock.

• However, parallel AC termination can be used with series termination to reduce EMI.

• Except for series termination, the termination network should be attached to the input (load) that is electrically the greatest distance from the source.

• Component leads should be as short as possible to prevent reflections due to lead inductance.

All Termination Circuits

Input Buffer/Receiver Design

Definitions • Good receiver circuits (input buffers) in CMOS chips are required in

any high-speed, board-level design to change the distorted signals transmitted between chips (because of the imperfections in the interconnecting signal paths) into well-defined digital signals with the correct pulse widths and amplitudes.

• Input buffers are circuits that take a chip's input signal, with imperfections such as slow rise and fall times, and convert it into a clean digital signal for use on-chip.

• If the buffer doesn't "slice" the data in the correct position, timing errors can occur.

• If the input signal is sliced too high or too low, the output signal's width is incorrect.

• In high-speed systems this reduces the timing budget in the system and can result in errors.

Basic Requirements • The ‘switching point’ voltage is defined as the voltage at which the input and

the output transitions from logic high to logic low or vice versa

• If the switching point is too high, the output data has good low noise margin

• If the switching point is too low, the output data has high noise margin

• If the buffer doesn’t slice the data at the correct time instants, timing errors can occur i.e., the bits of data at the output of the buffer gets distorted.

Signal Noise and Removal Possibilities

• Noise can be removed from a signal with a circuit who has different switching points for low-high and high-low transition.

Hysteresis

Schmitt – Trigger Circuit

• The CMOS inverter circuit can be easily modified to obtain an inverting Schmitt-trigger circuit to reduce input-signal noise.

For Ex.. • Design and simulate a Schmitt trigger using the short-channel

CMOS process with VSPL = 400 mV and VSPH = 700 mV

• W1L2/W2L1 = ((1-0.7)/(0.7-0.25))^2 = 0.444, Assume L1=L2=1u W1 = 10u and W2 = 22.5u

• W5L6/W6L5 = ((0.4)/(1-0.4-0.25))^2 = 1.3, Assume L5=L6=1u W6 = 20u and W5 = 26u

• M3 and M4, we can set to 10/1 and 20/1(β3 ≥ β1 or β2/ β4 ≥ β5 or β6)

This figure reveals the benefit of using a Schmitt trigger, namely, it allows slow moving inputs to be made into good solid logic high and low values.

Applications of Schmitt Trigger

• A pulse with ringing is a common voltage waveform encountered in buses or lines interconnecting systems.

• If this voltage is applied directly to a logic gate or inverter input with a VSP of 0.5 V, the output of the gate will vary with the period of the ringing on top of the pulse.

• Using a Schmitt trigger with properly designed switching points can eliminate this problem.

A New Project Design Methodology

A New Project Design Methodology

• Understand the root cause of all problems (signal-integrity, power-integrity, IO pad area requirements, slew-rates, pad cap etc..) and the general guidelines to minimize these problems.

• Translate the general guidelines into specific design rules for each specific custom product.

• Predict performance early in the design cycle by creating equivalent electrical circuit models for each component, critical net, and the entire system and by performing local and system-level simulation.

• Optimize the performance of the design for cost, schedule, and risk by modeling and simulating at every step of the design cycle, especially at the beginning.

• Use characterization measurements throughout the design cycle to reduce the risk and increase confidence of the quality of the predictions.

FURTHER STUDY ON IOs

Further study on IOs • Study on different other input buffers (requirements of LVDS, CML

..), scope of improvement

• Study of driver on PVT controls and implementation

• ESD basics and their scope of improvement

• Terminations – reflections on PCB and their elimination (Transmission line theory Extensions)

• SI/PI Analysis

REFERENCES

References • https://uta-ir.tdl.org/uta-

ir/bitstream/handle/10106/24772/Abraham_uta_2502M_12777.pdf?sequence=1

• http://www.rnbs.hiroshima-u.ac.jp/RCNS/lecture/pdf/HJM_H20/OHP_CMOS_4(H20-5-2).pdf

• http://download.intel.com/education/highered/signal/ELCT762/Class17_18_IBIS_io_buffer_class.ppt

• https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4005e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__3rd_Edition.pdf

• http://www.ti.com/lit/an/scha004/scha004.pdf

• http://www.oldfriend.url.tw/article/SI_PI_book/Signal%20and%20Power%20Integrity%20-%20Simplified_2nd_Eric%20Bogatin_Prentice%20Hall%20PTR_2010.pdf

• https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwiLjfqX0KjUAhVMvo8KHQ1SBisQFgghMAA&url=http%3A%2F%2Fdownload.intel.com%2Feducation%2Fhighered%2Fsignal%2FELCT762%2FClass07_Using_Transmission_lines.ppt&usg=AFQjCNHaQAuOtX5kbH6C0T6qIs6dvyHJig

• http://www.physics.ohio-state.edu/~hughes/cdf_osu/xft/documents/layout.pdf

• http://www.electronics-tutorials.ws/filter/filter_2.html

• http://www.electronics-tutorials.ws/rc/rc_3.html

Most of the slides deleted, please go through all the references mentioned