invited paper mitigation of noise coupling in multilayer ... · 1678 ieice trans. commun.,...

1678IEICE TRANS. COMMUN., VOL.E93–B, NO.7 JULY 2010

INVITED PAPER Special Section on Advanced Electromagnetic Compatibility Technology in Conjunction with Main Topics of EMC’09/Kyoto

Mitigation of Noise Coupling in Multilayer High-Speed PCB: Stateof the Art Modeling Methodology and EBG Technology

Tzong-Lin WU†a), Member, Jun FAN††, Francesco de PAULIS†††, Chuen-De WANG†,Antonio Ciccomancini SCOGNA††††, and Antonio ORLANDI†††, Nonmembers

SUMMARY Noise coupling on the power distribution networks (PDN)or between PDN and signal traces is becoming one of the main challengesin designing above GHz high-speed digital circuits. Developing an effi-cient and accurate modeling method is essential to understand the noisecoupling mechanism and then solve the problem afterwards. In addition,development of new noise mitigation technology is also important for fu-ture high-speed circuit systems. In this invited paper, a novel modelingmethodology that is based on the physics-based equivalent circuit modelwill be introduced, and an example of multiple layer PCB circuits will bemodeled and validated with good accuracy. Based on the periodic struc-ture concept, several new electromagnetic bandgap structures (EBG), suchas coplanar EBG, photonic crystal power layer (PCPL), and ground sur-face perturbation lattice (GSPL), will be introduced for the mitigation ofpower/ground noise. The trade/offs of all these structures will be discussed.key words: multilayer high-speed PCB modeling, PDN, ground bouncenoise, EBG, PCPL, GSPL

1. Introduction

When the data rates and circuit densities in modern high-speed digital circuits constantly increase, noise mitigationbecomes a critical part of multilayer printed circuit board(PCB) design. Significant signal/power integrity and EMCissues due to noise could occur, causing system malfunction,performance degradation, as well as high electromagneticemissions exceeding regulatory limits.

Many noise mechanisms could exist in a multilayerhigh-speed digital PCB. For example, simultaneous switch-ing noise (SSN) from active devices due to noise switch-ing not only provides a challenge for maintaining effectivevoltage supply [1], but also propagates in the power distri-bution network (PDN), resulting in potential signal degrada-tions [2] and noise radiation [3], [4]. Crosstalk among traces

Manuscript received February 1, 2010.Manuscript revised March 10, 2010.†The authors are with the Department of Electrical of Engi-

neering and Graduate Institute of Communication Engineering,National Taiwan University, Taipei, Taiwan 10617, Republic ofChina.††The author is with the Department of Electrical and Computer

Engineering, Electromagnetic Compatibility Laboratory, MissouriUniversity of Science and Technology, formerly University ofMissouri-Rolla, USA.†††The authors are with the UAq EMC Laboratory, Dept. of

Electrical Engineering, University of L’Aquila, I-67040, L’Aquila,Italy.††††The author is with CST of America, 492 Old Connecticut

path, suite505, Framingham, MA, 01701, USA.a) E-mail: [email protected]

DOI: 10.1587/transcom.E93.B.1678

and vias can significantly affect high-speed data communi-cations [5], and it is a potential EMI issue when the noise iscoupled to an I/O net [6]. Switching power supplies can gen-erate a wide frequency range of noise due to the switchingnature of the circuits. It is a potential source for EMI [7], butalso can be coupled to sensitive signal nets and cause signalintegrity issues [8], [9].

PCB geometry, especially discontinuities, is the rootcause of many noise coupling issues in high-speed digitalcircuit designs. Large planes, or area fills, are commonlyused for power supply and ground reference. These paral-lel planes can form electromagnetic resonant cavities wherehigh-frequency noise can propagate easily [10]. Further, inmodern designs with multiple logic levels, it is not uncom-mon to have overlapping power/ground planes, where noisecan be coupled from one cavity to another through edgecoupling and therefore fringing fields [11]. Vias are nec-essary in multilayer PCBs to transit signals from one layerto another or to connect the power and ground pins of activedevices to the power and ground planes. Vias themselvespresent impedance discontinuities for high-speed signals,resulting in reflections, loss, and mode conversions [12].When vias penetrate a parallel plane pair, they can also ex-cite the parallel-plane waves in the resonant cavity, causingthe noise coupling between power and signal nets as wellas electromagnetic emissions from the edges of the board[13], [14]. It has been found that vias can also effectivelycouple noise from one resonant cavity to another [15]. Slotsor gaps in a reference plane may be necessary in some PCBdesigns. Traces passing through a slot can excite uninten-tional electromagnetic waves propagating in the slot and theparallel-plane cavities, resulting in serious signal integrityand EMI issues [16]–[18]. The slots or apertures betweentwo parallel-plane cavities can effectively couple noise be-tween them [19], [20].

Much effort has been put on the modeling of multilayerPCB geometries to understand the fundamental noise cou-pling mechanisms, provide design solutions, as well as todevelop engineering guidelines. In this paper, a physics-based equivalent circuit modeling approach is introduced inSect. 2, which provides a systematic while efficient solutionfor the analysis and modeling of complex high-speed multi-layer PCBs.

Power distribution network plays a critical role in thenoise coupling issues in high-speed multilayer PCBs, asbriefly discussed earlier. Several solutions to maintain the

Copyright c© 2010 The Institute of Electronics, Information and Communication Engineers

WU et al.: MITIGATION OF NOISE COUPLING IN MULTILAYER HIGH-SPEED PCB1679

power integrity on high-speed multilayer PCBs has beenoverviewed in [21]. In particular, the electromagnetic bandgap (EBG) technology provides a promising solution to sig-nificantly reduce the noise propagation through power dis-tribution network. An overview of the EBG structures andfuture research directions is presented in Sect. 3. Finally inSect. 4 some concluding remarks are highlighted.

2. Modeling Noise Coupling in Multilayer High-SpeedPCBs

As a typical structure in high-speed PCBs, parallel-planepair has been extensively studied using full-wave methodssuch as finite element method (FEM) [22], finite differencetime domain (FDTD) [23], and method of moments (MoM)[24]. However, in practical multilayer PCBs, board thick-ness is so small that modeling of parallel-plane pair is a two-dimensional problem and general 3D full-wave solutions arenot efficient. Simple networks of RLC components or trans-mission line segments have shown unique advantages in thisapplication [25]–[27]. Another popular method employs acavity model [28]–[30]. Analytical expressions are readilyavailable for simple geometries, and fast algorithms havebeen developed [31], [32]. Combined with the segmentationtechnique [33], [34], the cavity model can be used to modelarbitrarily-shaped parallel-plane cavities.

For multiple overlapping plane structures, a multilayerfinite-difference method (MFDM) [35] has been proposed,and demonstrated to be effective in modeling noise couplingbetween planes. However, it is difficult to combine the ap-proach with SPICE elements for system-level simulations.Further, the approach cannot be easily extended for morecomplex geometries including multiple vias and traces. Thecavity model has also been adopted in the modeling of mul-tiple overlapping plane structures [11], [15]. Horizontal andvertical connections are necessary to connect resonant cavi-ties for complex geometries.

When vias penetrate a parallel-plane pair, they cannotbe modeled as simple lumped circuits as those used in [36],[37]. They excite parallel-plane modes in the plane pair, andthe planes are usually electrically large in practical cases.To characterize the coupling between vias and planes due tovia transitioning, two fast methods have been proposed inaddition to the conventional full-wave solutions. A multiplescattering method has been introduced to obtain an admit-tance matrix for multiple vias in a parallel-plane pair [38]–[40]. In this efficient method, the boundary conditions atvia barrels are rigorously satisfied, but the plane pair is re-stricted to either infinite or finite circular shapes [39]. Avery different approach has been proposed to combine thelumped circuit of vias with the impedance of plane pairbased on intuitive physical understanding [41], [42]. In thisapproach, the boundary conditions at the edges of the planepair are satisfied and the plane pair can be arbitrarily-shaped,although the combination of the lumped via circuits and thedistributed plane pair model is less rigorous.

For complex multilayer structures, the second approach

presents some unique advantages. When the plane pairimpedances are obtained using the cavity model and the seg-mentation technique mentioned earlier, the via-plane pairmodel developed for one plane pair cavity can be easilyextended to handle complex PCB geometries with multipleoverlapping (i.e., mutually coupled) planes. Further, traces,circuit components, as well as apertures/slots can be inte-grated for typical noise coupling simulations in practicalhigh-speed designs. Therefore, the details of the approachare herein discussed. It’s worth mentioning that full-wavemethods can become infeasible for investigating noise cou-pling issues in complex PCB structures due to their effi-ciency, simulation speed, as well as available computer re-sources.

2.1 Divide and Conquer Strategy

Although the PCB geometries for the modeling of typicalnoise coupling mechanisms are quite complex, they are es-sentially layered structures. Further, the planes and largearea fills that are common in the geometries provide bound-aries to implement a divide-and-conquer strategy. An exam-ple is shown in Fig. 1 to illustrate the approach for a typicalPCB geometry with multiple overlapping planes, vias, andtraces.

The multiple blocks are vertically connected throughthe ports defined in the via antipad regions, and horizontallyconnected through the ports defined at the interface surfacesbetween the cavities. A portion of a via penetrating twoplanes is illustrated in Fig. 2 with two defined coaxial ports.Antipad void regions are often used to isolate via from cop-per planes. In the two antipad regions in Fig. 2, the coax-ial TEM mode dominates in the frequency range of interest(below 100 GHz); therefore voltages and currents are well

Fig. 1 Divide and conquer: a multilayer PCB geometry can be dividedinto multiple blocks.

Fig. 2 The coaxial TEM mode dominates in the antipad regions wherethe radial electric field lines are between the via and the plane and the mag-netic field lines circulate the via.


Fig. 3 An example geometry to illustrate the block connectionprocedure, (a) top view; and (b) side view where i = 1, 2, and 3.

defined. The fact that the transverse fields dominate in theantipad regions is the underlying reason that the divide-and-conquer strategy works for the layered geometries. In Fig. 1,blocks 2, 3, and 4 are connected horizontally with block 5through the auxiliary ports defined at the interface surfacebetween them. It will be shown later that voltages and cur-rents are also well defined at these ports for most practicalcases.

By dividing a complex geometry into small individualblocks, modeling becomes efficient since each individualblock can be well characterized using suitable fast methodsand the connection of blocks can be relatively easily imple-mented in a circuit simulator. The validity and accuracy ofthe modeling are mainly determined by the way of geometrysegmentation and then network re-connection.

2.2 Plane Pair Modeling and Connection

For the blocks with a parallel plane pair, such as blocks 2,3, 4, and 5 in Fig. 1, the cavity model with the segmenta-tion technique are applied for each individual block first. Asa result, blocks are modelled as corresponding impedancematrices. In each block, there are ports at the locations ofthe vias that exist in the block for later connections with thelumped circuit models of the vias. There are also auxiliaryports defined at the boundaries of the block that connect toa neighboring block. These auxiliary ports are necessary toconnect the impedance matrices to achieve the connectionsof the blocks.

To illustrate the procedure, an example geometryshown in Fig. 3 is used. The top and bottom layers are solidrectangular copper planes, while the second and third layersonly have copper planes at the left half of the layers. Thus,the geometry can be divided into four parallel-plane cavi-

Fig. 4 Connection of cavities by enforcing voltage and current continu-ities at the auxiliary ports. Port group i is illustrated where i = 1, 2, and3.

ties as shown in Fig. 3(b). Ports P1 and P2 represent twothrough-hole vias. Since the via at P1 penetrates multipleparallel-plane cavities, a port between two parallel planesis defined at each cavity at the same x and y locations. Inother words, P1 represents a group of three ports verticallyaligned as shown in Fig. 3(b). To further connect the cavi-ties, a number of auxiliary port groups (illustrated as B1, B2,and B3 in Fig. 3(a) are specified along the interface betweenthe cavities. Each group includes an auxiliary port in eachparallel-plane cavity, defined between two parallel planes inthe z direction and located in the same x and y coordinates.The number of the auxiliary port groups is determined by thehighest frequency of interest and the length of the interfacesurface. The maximum spacing between two adjacent portgroups (in the x direction in this example) should be smallerthan 1/8 of the smallest wavelength. Perfect magnetic con-ductor (PMC) boundary condition is assumed at this inter-face surface. Then, each parallel-plane cavity is simulatedusing the cavity model and an impedance matrix is obtainedfor each cavity among the defined via and auxiliary ports.In practical PCB designs, the spacing between the parallelplanes is usually small enough so that the TMz0 modes dom-inate in every parallel-plane cavity. In other words, the elec-tric field inside a parallel-plane cavity is along the z directiononly. And it is constant along the z direction. Thus, at anelectrically small port between the two planes, voltage andcurrent can be well defined. This is the underlying reasonthat auxiliary ports can be used for cavity connections.

After the impedance matrices are obtained for all thecavities, those who have a common interface need to beconnected. This can be achieved by enforcing current andvoltage continuities at the auxiliary ports. For the exam-ple geometry shown in Fig. 3, cavities 2, 3, 4, and 5 needto be connected. To achieve this, as shown in Fig. 4 whereonly port group i is illustrated, the voltages and currents atthe auxiliary ports shall satisfy V4

i = V1i + V2

i + V3i and

I1i = I2

i = I3i = −I4

i , where i = 1, 2, and 3. By enforcingthe voltage and current relationships, the impedance matri-ces associated with cavities 2, 3, 4, and 5 are then combinedinto a single matrix and the auxiliary ports are eliminated.


Fig. 5 Lumped circuit model of a via portion between two parallelplanes. The via barrel is connected to: (a) neither plane; (b) top plane;(c) bottom plane; and (d) both planes.

2.3 Including Vias

Vias are then incorporated in the cavity model at the loca-tions of P1 and P2. As mentioned earlier, the via at P1 pen-etrates three cavities, thus it is divided into three portionswith one in each cavity. The via at P2 remains as one portionsince it only penetrates one parallel-plane cavity. Each viaportion is usually modelled as a lumped π-circuit [43], withvia-pad capacitances at the two coaxial ports and a parallel-plane port to be connected to the cavity model, as shownin Fig. 5. In the case where the via portion is connected toa plane, the corresponding coaxial port vanishes, and thecorresponding via-plane capacitance is replaced by a shortcircuit. The value of the via-plane capacitances can be ob-tained using an analytical formula developed in [44].

The parallel-plane port of each via portion is then con-nected to one of the P1 and P2 ports in the cavity model ofthe plane pairs. And the via portions that belong to the samevia (such as the via at the location of P1) are further con-nected at the neighbouring coaxial ports. All these connec-tions are again achieved by enforcing voltage and currentcontinuities. Following the procedure, all kinds of via ge-ometries in complex PCB designs can be incorporated intothe model with planes and area fills.

2.4 Traces, Components, and Slots

Microstrip traces can be included in the model as transmis-sion lines, neglecting the non-ideal behaviors at the trace-via connections. For striplines, a modal decomposition ap-proach has been proposed [45], [46]. Using this approach,the orthogonal parallel-plane and stripline modes are mod-elled independently, and then the modal behaviors are com-bined at the ends of the striplines.

Circuit elements such as decoupling capacitors, resis-tors, typical SPICE components, can be systematically in-cluded into the model at the coaxial ports of the vias [47].

For the slots or apertures in the exterior planes, they canbe modelled as a coupled transmission line or a co-planar

Fig. 6 Geometry of a real-world example: (a) top view; and (b) sideview.

slot line, and then connected to the cavity model [48]–[50].For the slots or apertures in the interior planes between twocavities, an extended cavity model method using the mag-netic current and “magnetic voltage” definitions has beenproposed in [20], which can be easily combined with thestandard cavity model.

2.5 A Modeling Example

Using the divide and conquer strategy, complex PCB ge-ometries can be modeled efficiently and effectively using theprocedures discussed earlier. Various geometrical featuresthat are critical for PCB-level noise coupling can be studied,including planes, area fills, vias, traces, components, slotsand apertures, and so on. A real-world example is used hereto demonstrate the flexibility and the robustness of the mod-eling approach.

The PCB geometry studied in this example is shownin Fig. 6. The dimensions of the PCB are approximately15200×9080 mils. Six layers in the board stackup as shownin Fig. 6(b) are studied for a noise coupling issue that wasobserved during hardware testing. The top layer is a signallayer where two nets, VLDT CPU1 and 12 V, are modeledin this example. Two solid rectangular ground planes arelocated in the second and third layers. The power planes inthe fourth and fifth layers have complex shapes. The sixthlayer is another signal layer where only the VLDT CPU1net is modeled, which is connected to the VLDT CPU1 netin the top layer through a via. In addition, a power via isalso included in the model, which connects the 12 V net inthe top layer to the 12 V net in the fourth layer.

Two ports are defined and the noise coupling betweenthem is simulated. Port 1 is defined between the 12 V net in


Fig. 7 Comparisons of the modeled results using the proposed approachand the FEM full-wave method: (a) magnitude of Z21; and, (b) phase ofZ21.

the top layer and the ground plane in the second layer. Port2 is defined between the VLDT CPU1 net in the top layerand the ground plane in the second layer.

The plane/area fill shapes in the signal and power lay-ers are very complicated, resulting in multiple regions withoverlapping planes. As a result, a total of 54 rectangular ortriangular cavities are defined from the geometry. They aremodeled and connected using the modeling method intro-duced earlier.

The simulated results of the transfer impedance, Z21,between ports 1 and 2 are compared with the full-wave sim-ulations using HFSS (a commercial FEM tool) in Fig. 7. Itcan be seen that the agreements between the two methodsare very good, only with some small discrepancies at lowfrequencies in phase. It took approximately 12 minutes tofinish the modeling using the proposed method, in compari-son with 49 minutes required in the HFSS simulations. Withadditional vias included in the geometry under study, thespeed difference between the two methods is more signifi-cant.

3. EBG for Noise Mitigation

3.1 Coplanar EBG

The power integrity requirements in multilayer PCBs andpackages are met in the low frequency range (up to hundredsof MHz) employing decoupling capacitors. A huge efforthas been done in recent years for finding layout techniques

Fig. 8 Transfer function |S 21 | in the solid plane cavity (solid blues curve)and in the EBG-solid plane cavity (green dashed curve).

able to go beyond these limits. Electromagnetic bandgap(EBG) structures are mainly employed for achieving sig-nificant noise reduction and thus efficient power integrityperformances in the GHz range. These kinds of structures,indeed, are able to achieve filtering effects in a wide band.The planar type is preferred to the mushroom like structure[51] because it does not require another layer besides thepower/ground layer.

The basic geometry of a planar EBG power/groundlayer modifies the typical layout of a solid power plane inthe PCB stack-up. The constructed EBG power plane ismade by square or rectangular patches connected by nar-row bridges. The EBG power layer generates a cavity withan adjacent solid ground layer.

Straight narrow bridges are the simplest layout tech-nique for connecting two adjacent patches [52], [53], butmore recent works have shown more complex bridge ge-ometries for achieving a large filtering band [54]. The ba-sic principles regulating the electromagnetic behavior of anyplanar EBG are presented in this section.

A square patch with dimensions 13.7 mm by 13.7 mmis chosen for giving the overview of the planar EBG behav-ior. The straight bridge is 1.3 mm long and 0.4 mm wide andit is attached at the center of the patch edge. A regular pat-tern is obtained by replicating this unit cell geometry on theEBG plane realizing a matrix of patches. A simple 3-by-2matrix structure is investigated, that is the basic geometryconsidered in [55]–[57].

Three regions in the frequency spectrum can be mainlyidentified in the transfer function of the cavity made by thepatterned power layer and a solid ground plane. Each re-gion has its specific phenomena. The first one is charac-terized by the distributed resonances of the whole structure,related to the outer dimensions of the cavity formed by thepower/ground layer. The resonances of an ideal solid planecavity are shifted to lower frequency due to the additionalinductance introduced by the bridges, as shown in Fig. 8.A bigger bridge inductance (given by a narrower or longerbridge) corresponds to a larger shift [57], and thus to a widerbandgap. The E-field component (vertical) normal to theplanes related to the first resonant mode is shown in Fig. 9(a)


Fig. 9 Pattern of the E-field normal component. (a). Case of ideal solidplane cavity. (b). Case of EBG-solid plane cavity.

and Fig. 9(b) for the ideal case of solid power/ground planecavity, and the case of the EBG power/ground plane cav-ity, respectively. The field distribution is altered by the dis-continuity at the gaps, thus the same resonant mode is ex-cited at 1.6 GHz and at 1 GHz for the ideal cavity and theEBG cavity, respectively. The middle frequency region isthe bandgap where the signal (noise) propagation is inhib-ited. The third region is characterized by the distributed res-onances of the single patch cavity, thus the noise can prop-agate inside the cavity from the patch to patch coupling ob-tained by the bridges.

A stack-up layer, devoted to ensure the quality and in-tegrity of the power delivery network through the use ofplanar EBG structure, can still be used for power deliverypurposes. In the case of EBG layer associated to a powervoltage level, the narrow connecting bridges can limit theamount of current carried by the whole plane. However anaccurate pre-layout analysis based on the knowledge of themaximum current to be carried to the active integrated cir-cuits, and based on the maximum allowed temperature rise,can be done to accurately sizing the plane thickness and thebridge width [57]. This analysis step helps ensuring both thepower integrity performances and the correct power deliveryrequirements.

Most of the research work related to planar EBG struc-tures, focused on widening the bandgap or specific filter-ing applications, always consider the EBG layer as an outerstack-up layer. However, the typical filtering behavior ofthe planar EBG embedded as an inner layer is not ensuredif some layout adjustments are not applied. A typical con-figuration as burying the EBG layer in the stack-up is con-sisted of the patterned EBG layer embedded between twosolid ground planes. The upper (solid plane-EBG plane) aswell as the lower cavity (EBG plane-solid plane) related tothis geometry does not provide the desired bandgap. Theresonant modes of the two solid planes cavity appear withinthe designed bandgap, due to the noise coupling betweenthe two cavities through the gaps of the EBG layer. Thefiltering properties related to the upper and to the lower cav-ities can be restored by inhibiting the resonances of the twosolid planes cavity. This effect can be achieved by stitchingtogether the two solid ground planes by vias. The isola-tion at the EBG layer is needed between the vias and thepatches, and it is achieved by etching circular ring aroundthe vias. A detailed procedure on how the number of vias

Fig. 10 Transfer function |S 21 | in the lower cavity of the embedded EBGgeometry. Cases with 13, 25, and 41 shorting vias.

and their location need to be chosen for achieving the de-sired bandgap is given in [58]. The embedded EBG cav-ity presents the same cavity resonances below the bandgap,as the outer EBG counterpart, thus the bandgap lower limitcan be designed as shown in [59], [60]. The bandgap upperlimit ( fhigh) is strictly dependent by the distance betweenadjacent shorting vias. Closer vias move this limit to higherfrequency, but the fhigh cannot be extended beyond the max-imum upper limit given by the first resonant mode of thesingle patch cavity in the unit cell.

An example for clarifying the role of the shorting viasis given. The EBG layer layout introduced in [55] is con-sidered, whereas the properties and details of the embeddedgeometry are given in [58]. Three test boards are built regu-larly placing 13, 25, and 41 vias for shorting the top and thebottom solid planes. Figure 10 shows the transfer function,the |S 21| between two ports (from the bottom solid planeto the EBG plane) of the lower cavity. The upper bandgaplimit varies and it moves up for larger number of vias. Thevia-to-via distance decreases when placing more vias, andthe coupling between the two test ports can occur just whenenergy is able to pass across two adjacent vias. Thereforethe fhigh is related to the distance between two adjacent vias[58]. The case with 41 vias is characterized by a first res-onance of the two solid planes cavity at 6.8 GHz, but thebandgap can be considered to end at the first resonant modeof the single patch cavity in the unit cell occurring at around4.8 GHz (resonance obtained also in the other two cases).

The drawback of using non-solid planes for buildingthe planar EBG structure is related to the integrity of thesignal transmission. The patterned plane causes the inter-connect transfer function to be affected by broken referenceplane. The signal energy can couple to the EBG-solid planecavity through the gaps between adjacent patches. Thisphenomenon occurs at the frequencies corresponding to theEBG-solid plane cavity resonances [55]. The use of differ-ential interconnects avoid this problems ensuring a correctsignal transmission. The differential insertion loss of a bal-anced trace pair will be affected only by the dielectric andconductor losses, as the ideal case [56].


Fig. 11 Schematic diagram of photonic crystal power/ground layer.

Fig. 12 The GBN suppression performance of PCPL.

3.2 Photonic Crystal Power/Ground Layer

Another approach that can keep both good power and sig-nal integrity has then proposed based on the photonic crys-tal power layer (PCPL) concept. Without etching power orground metal planes, the bandgap is formed by an artificialsubstrate with periodic dielectric constant contrast [61].

The two dimensional photonic crystal is formed whenthe different dielectric constants distribute periodically intwo dimensional spaces. The higher dielectric constant rodsare located periodically in x- and y- direction within thelower dielectric constant substrate, then the bandgaps willappear to suppress the propagation of the TM parallel-platemodes, which are considered as power/ground bounce noise(GBN).

It was proven that the bandgap can be formed both bysquare lattice and triangular lattice PCPL [61]. We will takethe square lattice as an example to investigate the designconcepts of PCPL. Figure 11 shows the design of PCPL.The dimension of the substrate is 62.5 mm by 100 mm with0.8 mm thickness. It is embedded 40 (8 by 5) high-DK rods.The dielectric constant of the substrate and the high dielec-tric constant rods is 2.33 and 102, respectively. The radiusof the circular rod and the period between adjacent rods aredenoted as r and a, respectively. The normalized radius, r/a,is designed as 0.16 and it is noted that the filling ratio Ar,defined as the total area of the all embedded rods to the areaof the substrate, is only about 8%.

The capability for GBN suppression for the PCPLcan be analyzed by the dispersion diagram of the unit cellshown in Fig. 12. There are two bandgaps in the frequencyrange from 2.8 GHz to 5 GHz and from 5.6 GHz to 6.5 GHz.Within these stopbands, the eigenmodes at any propaga-tion direction can’t exist inside the PCPL, i.e., the reso-

Fig. 13 (a) The design concept of the hybrid PCPL. (b) Two sets of gapmap for r = 2.0 mm (solid line) and r = 1.45 mm (dashed line) (c) Simu-lated and measured |S 21 | of hybrid PCPL and reference board.

nant modes caused by the GBN can be omni-directionallysuppressed in the PCPL. Besides the good performance forGBN suppression, the PCPL structure can also improvesthe performance of signal integrity and mitigates the elec-tromagnetic interference as discussed in [61].

To enhance the stopband bandwidth of the PCPL, thehybrid PCPL structure [62], which combines two differentlattice structures, is proposed and shown in Fig. 13(a). Thebroaden stopband can be synthesized by employing the gapmap of the photonic crystal lattice. The dependence of thereal frequency distributions on the normalized radius (r/a)of the high dielectric constant rods for the first two bandsare presented in a gap map. Figure 13(b) shows the gap mapwith the dielectric constant of the substrate and the high-DK rod being 2.2 and 92. It is obtained by calculating thedispersion diagrams for the unit cell with the fixed radius ofthe high dielectric constant rod and different period. Fromthe gap map, it is shown that the second bandgap will appearby choosing appropriate period. For example, the solid linein Fig. 13(b) shows that the stopbands formed by the PCPLwith 2 mm radius rods are in the frequency range from 3 to5.4 GHz and from 6.2 to 8.2 GHz at r/a = 0.2. It is worthnoting that there is a passband between the first and secondbandgap from 7.4 to 8.2 GHz for all the different period of


the unit cell. It implies that the passband always exists andthe continuously broad stopband cannot be achieved if weemploy the hybrid technique with fixed rod radius but variedperiod.

To cover the passband existing in the gap map of onerod radius, other hybrid technique with fixed period but var-ied rod radius is used. The gap map with two different radiiof rods is also shown in Fig. 13(b). It is observed that thepassband of one radius can be easily compensated by thebandgap of the other rod radius. Take an example to demon-strate how to enhance the bandwidth by using this hybridtechnique. The fist rod radius r = r1 = 2 mm is chosenwith the normalized radius r/a = 0.22. The stopband is from3.1 GHz to 5.3 GHz and from 6.2 GHz to 8.6 GHz, as shownin Fig. 13(a). There is a passband from 5.3 GHz to 6.2 GHz,but, it can be compensated by choosing the second rod ra-dius as r = r2 = 1.45 mm with the normalized radius r/a =0.159. The choice of the normalized radius for the secondrod is based on the assumption of keeping the same periodof a = 9.09 mm for the two different rods. The stopbandfor the second rod is from 3.9 to 7.3 GHz and from 8.3 to9.6 GHz. To combine these stopbands formed by the hy-brid PCPL, we can get a continuous stopband from 3.1 GHzup to 9.6 GHz with the bandwidth of 6.5 GHz. The simula-tion and measurement results of hybrid PCPL and referenceboard are shown in Fig. 13(c). It is observed that the propa-gated noise is mitigated by more than 30 dB in the frequencyrange from 3.2 to 9.5 GHz. It shows good agreement withthe results predicted by the gap map as we mentioned.

Although the PCPL shows good performance for main-taining the power integrity, signal integrity, and electromag-netic compatibility, the fabrication and cost issues of thehigh-DK rods are two challenges for widely using the PCPLconcept. Some research recently proposed to improve thedrawback of the PCPL. In [63], the optimization design ofPCPL achieves broadband and high efficient noise suppres-sion while minimizing the number of the high-DK rods andthe cost of the structure. On the other hand, the high dielec-tric constant rods can be considered as SMT-like compo-nents and ring-shaped soldering pads with through-hole-viaconnecting to power/ground planes on the PCB or packagesubstrate. It can solve how to implement of PCPL in a stan-dard PCB or package fabrication process, and keep the per-formance of PCPL [62].

3.3 Ground Surface Perturbation Lattice

The design idea of the ground surface perturbation lattice(GSPL) structure is similar to the PCPL, consisted in highdielectric constant material rods embedded between powerand ground layer. In contrast to the PCPL structure, theGSPL structure is composed of metal pads and conductivevias which can be manufactured in a standard PCB/packagefabrication process.

The test vehicle used to investigate the performanceof the GSPL is illustrated in Fig. 14. It is a circular metalpad between power and ground layer with four vias sym-

Fig. 14 GSPL, (a) related unit cell model and (b) top view of the testvehicle.

Fig. 15 S-parameter results for the GSPL structure.

metrically connected only to the ground layer. As shown inFig. 14(a), the geometrical parameters of a GSPL unit cellare: the side length of square unit cell a, the thickness be-tween power and ground layer h, the radius of the pad rpad

and of the vias rvia, and finally the parameter x, the positionof the 4 vias with respect to the edge of the pad. For the spe-cific case considered in this section, the parameters of GSPLare (a, h, rvia, εr) = (20 mm, 0.8 mm, 0.15 mm, 4.4). Threetest ports shown in Fig. 14(b) are set to represent the noisecoupling in the power/ground layer. The port location is:port 1 is at x = 2 mm and y = 2 mm, port 2 is at x = 40 mm,y = 57 mm and port 3 at x = 57 mm, y = 20 mm.

The GSPL structure embedded into power and groundlayer can provide an additional capacitance, and it act asthe high-DK rods in PCPL. The bandgap is formed andused to reduce parallel-plate noise or GBN propagating inpower/ground layers.

The two GSPL structures are studied by means of threedimensional (3D) full wave field simulator based on the Fi-nite Integration Technique [65] and the simulations are val-idated by comparison with other numerical methods (e.g.FEM) and reference to previous geometries already existentin literature [61], [63], [64].

Figure 15 depicts the S-parameters between port 1 andport 2 (noise coupling) for different values of x and rpad.Looking at the results predicted by the simulation, it canbe seen how the lower side cut off frequency of GSPL (thestarting frequency of the bandgap) is shifted towards lowerfrequencies when the radius of the pad (rpad) is increasedwhile keeping the parameter x constant (x = 2 mm). A shift


Fig. 16 Voltage variation in time domain at port 2 for differentconfigurations.

of more than 1 GHz (from 2.2 GHz to 1.1 GHz) is achieved ifa figure of merit of −40 dB is considered as sufficient valuefor noise isolation level. Similar considerations can be re-peated for the different value of x (x = 0) which is also re-ported in the same figure. In this case a shift from 2.5 GHzto 1.5 GHz is detected. The lower cut off frequency is in-versely related to the equivalent capacitance between powerplane and the GSPL structure, in fact when increasing theradius of the metal pad (rpad) the capacitance is increasedand hence the lower cut off frequency is decreased.

Another interesting point is that the lower side cutofffrequency is slightly increased as x is decreased from 2 to0 mm for the cases with the same rpad. Changing x from2 mm to 0 mm, the position of the four vias connecting thecircular pad to the ground plane will change their anchorposition to the edge of the circular pad. This means thatthe equivalent via inductance decreases because their mutualinductance is reduced due to farer distance. As the conven-tional mushroom structure, the lower side cutoff frequencyis also inversely related to this effective via inductance. Itshould be mentioned that the same considerations can be ap-plied to the other output port (port 3) and here not reportedfor sack of brevity.

To further validate the results obtained in the frequencydomain, Fig. 16 illustratates the voltage variation at port 2 inthe time domain when port 1 is excited with a gaussian pulsenoise with 1 V amplitude. It can be observed how the maxi-mum value of voltage variation for the GSPL structure is at-tenuated of more than 50% with respect to a reference struc-ture where the GSPL is removed and a simple power/groundplane pair is instead considered. The GSPL structure of x =2 mm and rpad = 9 mm is used in this simulation. The rsultsare obtained by the 3D full wave simulation tool, CST [65].

From the results presented in this section, it can be de-duced how the stopband of the GSPL can be properly de-signed by considering the two parameters, rpad and x. Inparticular it is possible to both lower the cut off frequencyand extend the bandwidth of bandgap with respect to thestandard PCPL [61]. In addition to this, because of the stan-dard PCB/package fabrication process, the GSPL is lowercost if compared with a standard PCPL, therefore more suit-able for real world applications.

The absence of etches in the layers (typical in planarEBG structures) also avoids possible signal integrity prob-lems such as degradation in the performance (revealed byboth insertion loss and eye diagrams) and large impedancevariations and/or bumps in the TDR profile.

Further studies will include the sensitivity analysis withrespect to both the number of vias connecting the circularpatch with the bottom layer as well as the shape of the patch(e.g. circular, triangular and square). Some investigationson the unit-cell miniaturization and bandwidth enhancementwere done by combining of the coplanar EBG structure withthe GSPL concept [66]–[68], but more research is requiredfor avoiding the corresponding signal integrity problem dueto the etched power planes.

4. Conclusions

Based on the noise control point of view, two state of theart technologies for the mitigation of the noise coupling inhigh-speed digital circuits are introduced. The first one isa new modeling methodology that is based on the physics-based equivalent circuit model. It can accurately and ef-ficiently model the complicated PCB with considering theplanar PDN, vias, and slot effects. The second one is theEBG technology that can efficiently suppress the above GHznoise. Several EBG structures and their trade/offs have beendiscussed.

Acknowledgments

This work was supported in part by the National ScienceCouncil, Taiwan, R.O.C., under Grand NSC 96–2628-E-002-001-MY3, and partly by Excellent Research Projectsof National Taiwan University under Grand 98R0062-03.

References

[1] M. Swaminathan and E. Engin, Power Integrity Modeling and De-sign for Semiconductors and Systems, Prentice Hall, 2008.

[2] J. Fan, M. Cocchini, B. Archambeault, J.L. Knighten, J.L. Drewniak,and S. Conner, “Noise coupling between signal and power/groundnets due to signal vias transitioning through power/ground planepair,” IEEE International Symposium on Electromagnetic Compati-bility, Detroit, MI, Aug. 2008.

[3] H. Shim, Y. Fu, and T. Hubing, “Radiated emissions from popu-lated printed circuit boards due to power bus noise,” IEEE Interna-tional Symposium on Electromagnetic Compatibility, Santa Clara,CA, Aug. 2004.

[4] T.-L. Wu, S.-T. Chen, J.-N. Huang, and Y.-H. Lin, “Numericaland experimental investigation of radiation caused by the switchingnoise on the partitioned DC reference planes of high speed digitalPCB,” IEEE Trans. Electromagn. Compat., vol.46, no.1, pp.33–45,Feb. 2004.

[5] B. Young, Digital Signal Integrity: Modeling and Simulation withInterconnects and Packages, Prentice Hall, 2000.

[6] H. Shim, T. Hubing, T. Van Doren, R. DuBroff, J. Drewniak, D.Pommerenke, and R. Kaires, “Expert system algorithms for identi-fying radiated emission problems in printed circuit boards,” IEEEInternational Symposium on Electromagnetic Compatibility, SantaClara, CA, Aug. 2004.

[7] K. Kam, D. Pommerenke, C. Lam, and R. Steinfeld, “EMI analysis


methods for synchronous buck converter EMI root cause analysis,”IEEE International Symposium on Electromagnetic Compatibility,Detroit, MI, Aug. 2008.

[8] H. Shi, “Perturbation based modeling strategy for weakly coupledinterconnects,” EPEP 2009, Portland, OR, Oct. 2009.

[9] A. Luoh, G. Garrison, and J. Powell, “Switching voltage regulatornoise coupling analysis for printed circuit board systems,” Design-Con 2009, Santa Clara, CA, Feb. 2009.

[10] J. Fan, J.L. Drewniak, H. Shi, and J.L. Knighten, “DC power-busmodeling and design with a mixed-potential integral equation for-mulation and circuit extraction,” IEEE Trans. Electromagn. Com-pat., vol.43, no.4, pp.426–436, Nov. 2001.

[11] G. Feng, G. Selli, K. Chand, M. Lai, L. Xue, and J.L. Drewniak,“Analysis of noise coupling result from overlapping power areaswithin power delivery networks,” Proc. 2006 IEEE lnt. Symp. Elec-tromagn. Compat., vol.2, pp.304–309, Portland, Oregon, Aug. 2006.

[12] X. Gu, A. Ruehli, and M. Ritter, “Impedance design for multi-layered vias,” 2008 Electrical Performance of Electronic Packaging,Santa Clara, CA, Oct. 2008.

[13] S. Wu, X. Chang, C. Schuster, X. Gu, and J. Fan, “Eliminating via-plane coupling using ground vias for high-speed signal transitions,”17th Conference on Electrical Performance of Electronic Packaging,San Jose, CA, Oct. 2008.

[14] J.-N. Hwang and T.-L. Wu, “Coupling of the ground bounce noise tothe signal trace with via transition in partitioned power bus of PCB,”2002 IEEE EMC Symposium, vol.2, pp.733–736, Minnesota, USA,Aug. 2002.

[15] G. Feng and J. Fan, “Analysis of SSN noise coupling in multilayerpower/ground planes with segmentation method and cavity model,”accepted to be published in the IEEE Trans. Electromagn. Compat.

[16] D.S. Britt, D. Hockanson, F. Sha, J. Drewniak, T. Hubing, and T.Van Doren, “Effects of gapped ground planes and guard traces onradiated EMI,” IEEE International Symposium on ElectromagneticCompatibility, Austin, TX, Aug. 1997.

[17] W. Pan, S. Connor, and B. Archambeault, “Predicting noise voltagefrom trace crossing split planes on printed circuit boards,” IEEE In-ternational Symposium on Electromagnetic Compatibility, Austin,TX, Aug. 2009.

[18] Y.-H. Lin and T.-L. Wu, “Analysis of radiation caused by SSNand transmission line by combining the equivalent circuits of activeIC into FDTD,” 2004 IEEE EMC Symposium, pp.277–282, SantaClara, USA, Aug. 2004.

[19] J. Lee, M.D. Rotaru, M.K. Iyer, H. Kim, and J. Kim, “Analysis andsuppression of SSN noise coupling between power/ground planecavities through cutouts in multilayer packages and PCBs,” IEEETrans. Adv. Packag., vol.28, no.2, pp.298–309, May 2005.

[20] G. Feng and J. Fan, “An extended cavity method to analyze slot cou-pling between PCB cavities,” accepted to be published in the IEEETrans. Electromagn. Compat.

[21] T.-L. Wu, H.-H. Chuang, and T.-K. Wang, “Overview of power in-tegrity solutions on package and PCB: Decoupling and EBG isola-tion,” IEEE Trans. Electromagn. Compat., vol.52, no.2, pp.346–356,May 2010.

[22] C. Guo and T.H. Hubing, “Circuit models for power bus structureson printed circuit boards using a hybrid FEM-SPICE method,” IEEETrans. Adv. Packag., vol.29, no.3, pp.441–447, Aug. 2006.

[23] X. Ye, D.M. Hockanson, M. Li, Y. Ren, W. Cui, J.L. Drewniak, andR.E. DuBroff, “EMI mitigation with multilayer power-bus stacksand via stitching of reference planes,” IEEE Trans. Electromagn.Compat., vol.43, pp.538–548, Nov. 2001.

[24] Y. Ji and T.H. Hubing, “On the modeling of a gapped power-busstructure using a hybrid FEM/MoM approach,” IEEE Trans. Elec-tromagn. Compat., vol.44, no.4, pp.566–569, Nov. 2002.

[25] L. Smith, T. Roy, and R. Anderson, “Power plane SPICE models andsimulated performance for materials and geometries,” IEEE Trans.Adv. Packag., vol.24, no.3, pp.227–287, Aug. 2001.

[26] W.J.R. Hoefer, “The transmission-line matrix method: Theory and

applications,” IEEE Trans. Microw. Theory Tech., vol.MTT-33,no.10, pp.882–893, Oct. 1985.

[27] K. Lee and A. Barber, “Modeling and analysis of multichip mod-ule power supply planes,” IEEE Trans. Adv. Packag., vol.18, no.4,pp.628–639, Nov. 1995.

[28] T. Okoshi, Planar Circuits for Microwaves and Lightwaves,Springer-Verlag, Berlin, Germany, 1985.

[29] Y.T. Lo, D. Solomon, and W.F. Richards, “Theory and experimenton microstrip antennas,” IEEE Trans. Antennas Propag., vol.AP-27,no.2, pp.137–145, March 1979.

[30] G.T. Lei, R.W. Techentin, and B.K. Gilbert, “High-frequency char-acterization of power/ground-plane structures,” IEEE Trans. Mi-crow. Theory Tech., vol.47, no.2, pp.562–569, May 1999.

[31] Z.L. Wang, O. Wada, Y. Toyota, and R. Koga, “Convergence accel-eration and accuracy improvement in power bus impedance calcula-tion with a fast algorithm using cavity model,” IEEE Trans. Electro-magn. Compat., vol.47, no.1, pp.2–9, Feb. 2005.

[32] C. Wang, J. Mao, G. Selli, S. Luan, L. Zhang, J. Fan, D.J.Pommerenke, R.E. Dubroff, and J.L. Drewniak, “An efficient ap-proach for power delivery network design with closed-form ex-pressions for parasitic interconnect inductance,” IEEE Trans. Adv.Packag., vol.29, no.2, pp.320–334, May 2006.

[33] T. Okoshi, “The segmentation method — An approach to the anal-ysis of microwave planar circuits,” IEEE Trans. Microw. TheoryTech., vol.MTT-24, no.10, pp.662–668, Oct. 1976.

[34] R. Chadha and K.C. Gupta, “Segmentation method using impedancematrices for analysis of planar microwave circuits,” IEEE Trans. Mi-crow. Theory Tech., vol.MTT-29, no.1, pp.71–74, Jan. 1981.

[35] A.E. Engin, K. Bharath, and M. Swaminathan, “Multilayered finite-difference method (MFDM) for modeling of package and printedcircuit board planes,” IEEE Trans. Electromagn. Compat., vol.49,no.2, pp.441–447, May 2007.

[36] T. Wang, R.F. Harington, and J.R. Mautz, “Quasi-static analysis ofa microstrip via through a hole in a ground plane,” IEEE Trans. Mi-crow. Theory Tech., vol.36, no.6, pp.1008–1013, June 1988.

[37] P.A. Kok and D.D. Zutter, “Prediction of the excess capacitanceof a via-hole through a multilayered board including the effect ofconnecting microstrips or striplines,” IEEE Trans. Microw. TheoryTech., vol.42, no.12, pp.2270–2276, Dec. 1994.

[38] H. Chen, Q. Lin, L. Tsang, C.-C. Huang, and V. Jandhyala, “Anal-ysis of a large number of vias and differential signaling in multilay-ered structures,” IEEE Trans. Microw. Theory Tech., vol.51, no.3,pp.818–829, March 2003.

[39] L. Tsang and D. Miller, “Coupling of vias in electronic packagingand printed circuit board structures with finite ground plane,” IEEETrans. Adv. Packag., vol.26, no.4, pp.375–384, Nov. 2003.

[40] X. Gu and M.B. Ritter, “Application of Foldy-Lax multiple scatter-ing method to via analysis in multi-layered printed circuit board,”DesignCon 2008, Santa Clara, CA, Feb. 2008.

[41] C. Schuster, Y. Kwark, G. Selli, and P. Muthana, “Developing a‘physical’ model for vias,” DesignCon 2006, Santa Clara, CA, Feb.2006.

[42] G. Selli, C. Schuster, Y.H. Kwark, M.B. Ritter, and J.L. Drewniak,“Developing a physical via model for vias — Part II: Coupled andground return vias,” DesignCon 2007, Santa Clara, CA, Jan.–Feb.2007.

[43] G. Selli, C. Schuster, Y.H. Kwark, M.B. Ritter, and J.L. Drewniak,“Model-to-hardware correlation of physics based via models withthe parallel-plate impedance included,” Proc. IEEE Symposium onElectromagnetic Compatibility, pp.781–785, Portland, OR, Aug.2006.

[44] Y. Zhang, J. Fan, G. Selli, M. Cocchini, and F. de Paulis, “Analyti-cal evaluation of via-plate capacitance for multilayer printed circuitboards and packages,” IEEE Trans. Microw. Theory Tech., vol.56,no.9, pp.2118–2128, Sept. 2008.

[45] A.E. Engin, W. John, G. Sommer, W. Mathis, and H. Reichl, “Mod-eling of striplines between a power and a ground plane,” IEEE Trans.


Adv. Packag., vol.29, no.3, pp.415–426, Aug. 2006.[46] R. Rimolo-Donadio, X. Gu, Y.H. Kwark, M.B. Ritter, B.

Archambeault, F. de Paulis, Y. Zhang, J. Fan, H. Bruns, and C.Schuster, “Physics-based via and trace models for efficient link sim-ulation on multilayer structures up to 40 GHz,” IEEE Trans. Microw.Theory Tech., vol.57, no.8, pp.2072–2083, Aug. 2009.

[47] X. Gu, R. Rimolo-Donadio, Z. Yu, F. de Paulis, Y.H. Kwark, M.Cocchini, M.B. Ritter, B. Archambeault, A. Ruehli, J. Fan, and C.Schuster, “Fast physics-based via and trace models for signal andpower integrity co-analysis,” DesignCon 2010, Santa Clara, CA,Feb. 2010.

[48] L. Zhang, B. Archambeault, S. Conner, J.L. Knighten, J. Fan, N.W.Smith, R. Alexander, R.E. DuBroff, and J.L. Drewniak, “A circuitapproach to model narrow slot structures in a power bus,” Proc.IEEE Int. Symp. Electromagn. Compat., pp.401–406, Aug. 2004.

[49] Z.L. Wang, O. Wada, Y. Toyota, and R. Koga, “Modeling of gappedpower bus structures for isolation using cavity modes and segmenta-tion,” IEEE Trans. Electromagn. Compat., vol.47, no.2, pp.210–218,May 2005.

[50] A.E. Engin, K. Bharath, M. Swaminathan, K. Uriu, and T. Yamada,“Efficient modeling of package power delivery networks with fring-ing fields and gap coupling in mixed signal systems,” 2006 IEEE,Electrical Performance of Electronic Packaging, pp.59–62, Oct.2006.

[51] T. Kamgaing and O.M. Ramahi, “Design and modeling of highimpedance electromagnetic surfaces for switching noise suppressionin power planes,” IEEE Trans. Electromagn. Compat., vol.47, no.3,pp.479–489, Aug. 2005.

[52] T.-L. Wu, Y.-H. Lin, and S.-T. Chen, “A novel power planes with lowradiation and broadband suppression of ground bounce noise usingphotonic bandgap structures,” IEEE Microw. Wireless Componen.Lett., vol.14, no.7, pp.337–339, July 2004.

[53] T.-L. Wu, Y.-H. Lin, T.-K. Wang, C.-C. Wang, and S.-T. Chen,“Electromagnetic bandgap power/ground planes for wideband sup-pression of ground bounce noise and radiated emission in high-speedcircuits,” IEEE Trans. Microw. Theory Tech., vol.53, no.9, pp.2935–2942, Sept. 2005.

[54] T.-L. Wu, C.-C. Wang, Y.-H. Lin, T.-K. Wang, and G. Chang,“A novel power plane with super-wideband elimination of groundbounce noise on high speed circuits,” IEEE Microw. Wireless Com-ponen. Lett., vol.15, no.3, pp.174–176, March 2005.

[55] F. de Paulis, A. Orlandi, L. Raimondo, and G. Antonini, “Fun-damental mechanisms of coupling between planar electromagneticbandgap structures and interconnects in high-speed digital circuits,Part I — Microstrip lines,” Proc. EMC Europe Workshop 2009,Athens, Greece, June 2009.

[56] F. de Paulis and A. Orlandi, “Signal integrity analysis of single-ended and differential striplines in presence of EBG planar struc-tures,” IEEE Microw. Wireless Componen. Lett., vol.19, no.9,pp.554–557, Sept. 2009.

[57] F. de Paulis, L. Raimondo, and A. Orlandi, “IR-DROP analysis andthermal assessment of planar electromagnetic bandgap structures forpower integrity applications,” IEEE Trans. Adv. Packag., to be pub-lished.

[58] F. de Paulis, L. Raimondo, and A. Orlandi, “Incorporating embed-ded planar electromagnetic band-gap structures within multilayerprinted circuit boards,” submitted at IEEE Trans. Microw. TheoryTech.

[59] T.H. Kim, D. Chung, E. Engin, W. Yun, Y. Toyota, and M.Swaminathan, “A novel synthesis method for designing electromag-netic band gap (EBG) structures, in packaged mixed signal systems,”Proc. EPEP 2007, Atlanta, USA.

[60] F. de Paulis, L. Raimondo, A. Orlandi, L. Ren, and J. Fan, “Equiva-lent circuit models for evaluation of bandgap limits for planar elec-tromagnetic bandgap structures,” submitted at IEEE InternationalSymposium on EMC, Ft. Lauderdale, July 2010.

[61] T.-L. Wu and S.-T. Chen, “A photonic crystal power/ground layer

for eliminating simultaneously switching noise in high-speed cir-cuit,” IEEE Trans. Microw. Theory Tech., vol.54, no.8, pp.3398–3406, Sept. 2006.

[62] G.-Z. Wu, Y.-C. Chen, and T.-L. Wu, “Design and implementationof a novel hybrid photonic crystal power/ground layer for broadbandpower noise suppression,” IEEE Trans. Adv. Packag., vol.33, no.1,pp.206–211, Feb. 2010.

[63] A.C. Scogna, T.-L. Wu, and A. Orlandi, “Noise coupling mitigationin PWR/GND plane pair by means of photonic crystal fence: Sensi-tivity analysis and design parameters extraction,” IEEE Trans. Adv.Packag., to be published.

[64] A.C. Scogna, C.-D. Wang, A. Orlandi, and T.-L. Wu, “Parallel-platenoise suppression using a ground surface perturbation lattice (GSPL)structure,” submitted to APEMC 2010, Beijing, China.

[65] CST STUDIO SUITE 2010TM- www.cst.com[66] T.-K. Wang, T.-W. Han, and T.-L. Wu, “A novel power/ground

layer using artificial substrate EBG for simultaneously switchingnoise suppression,” IEEE Trans. Microw. Theory Tech., vol.56, no.5,pp.1164–1171, May 2008.

[67] T.-K. Wang, C.-Y. Hsieh, H.-H. Chuang, and T.-L. Wu, “Design andmodeling of a stopband-enhanced EBG structure using ground sur-face perturbation lattice for power/ground noise suppression,” IEEETrans. Microw. Theory Tech., vol.57, no.8, pp.2047–2054, Aug.2009.

[68] C.-Y. Hsieh, C.-D. Wang, and T.-L. Wu, “A power bus with mul-tiple via ground surface perturbation lattices for broadband noiseisolation: Modeling and application in RF-SiP,” IEEE Trans. Adv.Packag., to be published.

Tzong-Lin Wu received the B.S.E.E.and Ph.D. degrees from National Taiwan Uni-versity (NTU), Taipei, Taiwan, in 1991 and1995, respectively. From 1995 to 1996, he wasa senior Engineer at the Microelectronics Tech-nology, Inc., Hsinchu, Taiwan. From 1996 to1998, he joined the Central Research Institute,Tatung Company, Taipei, Taiwan, where he wasinvolved with the analysis and measurement ofEMC/EMI problems of high-speed digital sys-tems. From 1998 to 2005, he was with the Elec-

trical Engineering Department of National Sun Yat-sen University. He iscurrently a professor with the Department of Electrical Engineering andGraduate Institute of Communication Engineering, NTU, Taiwan. He wasthe visiting professor at the Electrical Engineering Department of Univer-sity of California at Los Angeles (UCLA) in the summer of 2008. Hisresearch interests include EMC/EMI and signal/power integrity design forhigh-speed digital/optical systems. Dr. Wu received the Excellent ResearchAward and Excellent Advisor Award from NSYSU in 2000 and 2003, re-spectively, Outstanding Young Engineers Award from the Chinese Insti-tute of Electrical Engineers (CIEE) in 2002, Wu Ta-You Memorial Awardfrom National Science Council (NSC) in 2005, and Technical AchievementAward from IEEE EMC Society in 2009. Dr. Wu serves as the Treasurerof Taipei Section, IEEE in 2007–2008, and Chair of the Taipei Section, In-stitute of Electronics, Information and Communication Engineers (IEICE)from 2007 to 2011. He also serves as the Board of Directors (BoD) of IEEETaipei Section in 2009–2010. He is elected as a Distinguished Lecturer ofIEEE EMC society for the term of 2008 to 2009. Dr. Wu is the co-chair of2007 IEEE EDAPS workshop and the chair of 2008 International workshopon EMC. He served as the associate editor of the International Journal ofElectrical Engineering (IJEE) since 2006. Dr. Wu is a senior member ofIEEE and a member of CIEE.


Jun Fan (S’97-M’00-SM’06) received hisB.S. and M.S. degrees in Electrical Engineer-ing from Tsinghua University, Beijing, China,in 1994 and 1997, respectively. He receivedhis Ph.D. degree in Electrical Engineering fromthe University of Missouri-Rolla in 2000. From2000 to 2007, he worked for NCR Corporation,San Diego, CA, as a Consultant Engineer. InJuly 2007, he joined the Missouri University ofScience and Technology (formerly University ofMissouri-Rolla), and is currently an Assistant

Professor with the Missouri S&T EMC Laboratory. His research interestsinclude signal integrity and EMI designs in high-speed digital systems, dcpower-bus modeling, intra-system EMI and RF interference, PCB noise re-duction, differential signaling, and cable/connector designs. Dr. Fan servedas the Chair of the IEEE EMC Society TC-9 Computational Electromag-netics Committee from 2006 to 2008, and was a Distinguished Lecturerof the IEEE EMC Society in 2007 and 2008. He currently serves as theVice Chair of the Technical Advisory Committee of the IEEE EMC Soci-ety. Dr. Fan received an IEEE EMC Society Technical Achievement Awardin August 2009.

Francesco de Paulis (S’08) was born inL’Aquila, Italy in 1981. He received the Lau-rea degree and the Specialistic degree (summacum laude) in Electronic Engineering from Uni-versity of L’Aquila, L’Aquila, Italy, in 2003 and2006, respectively. In August 2006 he joinedthe EMC Laboratory at the Missouri Universityof Science and Technology (formerly Universityof Missouri-Rolla), USA, where he received theM.S. degree in Electrical Engineering in May2008. He is currently enrolled in Ph.D. program

at the University of L’Aquila, L’Aquila, Italy. He was involved in the re-search activities of the UAq EMC Laboratory from August 2004 to August2006. From June 2004 to June 2005 he had an internship at Selex Com-munications s.p.a. within the layout/SI/PI design group. He is currently aResearch Assistant at the UAq EMC Laboratory, University of L’Aquila,Italy. His main research interests are in developing fast and efficient analy-sis tool for SI/PI and design of high speed signal on PCB, RF interference inmixed-signal system, EMI problem investigation on PCBs. Mr. de Paulisreceived the Best Paper Award at the IEEE International Symposium onEMC in 2009.

Chuen-De Wang was born in Pingtung,Taiwan, R.O.C., in 1983. He received the B.S.degree in electrical engineering from NationalCentral University, Taoyuan, Taiwan, R.O.C., in2006, and is currently working toward the Ph.D.degree at the Graduate Institute of Communi-cation Engineering, National Taiwan Univer-sity. His current research interest is the power-integrity design in high-speed package and PCB.

Antonio Ciccomancini Scogna (Student’03-M’05- SM’09) received the Laurea degreeand the PhD degree in Electrical Engineeringfrom University of L’Aquila, Italy respectivelyin 2001 and 2005. Currently he is Principal En-gineer at Computer Simulation Technology ofAmerica (CST), Framingham, MA. His researchof interest is the field of numerical modeling,printed and integrated circuits, electromagneticpackaging effects, signal integrity and power in-tegrity analysis in high speed digital systems and

Electromagnetic Bandgap structures. In 2004 he received the CST Uni-versity Publication Award for the use of the Finite Integration Techniquein Signal Integrity applications. He is the recipient of DesignCon final-ist Best Paper Award in 2007 and DesignCon Best Paper Award in 2008.Dr. Ciccomancini is author of more than 50 publications in IEEE JournalTransactions, International Conference Proceedings and Electronic DesignAutomation (EDA) magazines. He is a member of IEEE, ACES, IEC, EMCTC-9 and TC-10 Committees.

Antonio Orlandi (M’90-SM’97-F’07) wasborn in Milan, Italy in 1963. He received theLaurea degree in Electrical Engineering fromthe University of Rome “La Sapienza,” Italy, in1988. He was with the Department of ElectricalEngineering, University of Rome “La Sapienza”from 1988 to 1990. Since 1990 he has beenwith the Department of Electrical Engineeringof the University of L’Aquila where he is cur-rently Full Professor and Chair of the UAq EMCLaboratory. Author of more than 200 technical

papers, he has published in the field of electromagnetic compatibility inlightning protection systems and power drive systems. Current researchinterests are in the field of numerical methods and modeling techniquesto approach signal/power integrity, EMC/EMI issues in high speed digitalsystems. Dr. Orlandi received the IEEE Transactions on ElectromagneticCompatibility Best Paper Award in 1997, the IEEE EMC Society Tech-nical Achievement Award in 2003, the IBM Shared University ResearchAward in 2004, 2005 and 2006, the CST University Award in 2004 and TheIEEE International Symposium on EMC Best Paper Award in 2009. He iscurrently Associate Editor of the IEEE Transactions on ElectromagneticCompatibility, member of the “Education,” TC-9 “Computational Electro-magnetics” and Chairman of the TC-10 “Signal Integrity” Committees ofthe IEEE EMC Society. From 1996 to 2000 has been Associate Editorof the IEEE Transactions on Electromagnetic Compatibility, from 2001 to2006 served as Associate Editor of the IEEE Transactions on Mobile Com-puting and from 1999 to the end of the Symposium was Chairman of theTC-5 “Signal Integrity” Technical Committee of the International ZurichSymposium and Technical Exhibition on EMC.

invited paper mitigation of noise coupling in multilayer ... · 1678 ieice trans. commun.,...

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