investigation of the novel attributes of a single-halo double gate soi mosfet: 2d simulation study

8/14/2019 Investigation of the Novel Attributes of a Single-Halo Double Gate SOI MOSFET: 2D Simulation Study

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Investigation of the Novel Attributes of a Single-Halo Double Gate SOI MOSFET: 2D Simulation Study

G. Venkateshwar Reddy and M. Jagadesh Kumar1

Department of Electrical Engineering,

Indian Institute of Technology, Delhi,

Hauz Khas, New Delhi 110 016, INDIA.

Email: [email protected] Fax: 91-11-2658 1264

1Author for Correspondence

G.Venkateshwar Reddy and M. Jagadesh Kumar, "Investigation of the Novel Attributes of aSingle-Halo Double Gate SOI MOSFET: 2D Simulation Study," Microelectronics Journal,Vol.35, pp.761-765, September2004


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Abstract

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI

MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI

MOSFET. The two-dimensional (2-D) numerical simulation studies demonstrate that the

application of single halo to the double gate structure results in threshold voltage roll-up,

reduced DIBL, high drain output resistance, kink free output characteristics and increase in

the breakdown voltage when compared with a conventional DG structure. For the first time

we show that the presence of single halo on the source side results in a step function in the

surface potential which screens the source side of the structure from the drain voltage

variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices

over conventional DG MOSFET and provides an incentive for further experimental

exploration.

Index Terms: Silicon-on-insulator (SOI), Double Gate (DG) SOI MOSFET, channel

engineering, single halo (SH).


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1. Introduction

CMOS technology has seen excellent high-speed performance achieved through improved

design, use of high quality materials and processing innovations over the past decade. One

such innovation, Double-Gate (DG) SOI MOSFET using lightly doped ultra thin layers,

seems to be a very promising option for ultimate scaling of CMOS technology [1-2].

Excellent short-channel effect immunity, high transconductance and ideal subthreshold factor

have been reported by many theoretical and experimental studies on this device [3-7]. In

particular, asymmetrical DG SOI MOSFETs (front gate p+ poly and back gate n+ poly) are

becoming popular since this type of structure provides a desirable threshold voltage (not too

high or too low) unlike the symmetrical DG SOI MOSFETs.

However for channel lengths less than 100nm, DG MOSFETs also show considerable

threshold voltage roll-off and increasing effort is focused to circumvent the undesirable short-

channel effects (SCE). The reduction of threshold voltage with decreasing channel length and

increasing drain voltage is widely used as an indicator of the short-channel effect in

evaluating CMOS technologies. This adverse threshold voltage roll-offeffect is perhaps the

most daunting road block in future MOSFET design. The minimum acceptable channel

length is primarily determined by this roll-off. The threshold voltage roll-off can be reduced

or even reversed, i.e., the threshold voltage increases with decreasing channel length, by

locally raising the channel doping next to the drain or drain/source junctions. In the past few

years, the local high doping concentration in the channel near source/drain junctions has been

implemented via lateral channel engineering, e.g., halo [8] orpocket implants [9]. Single

halo MOSFET structures have been introduced for bulk [10] as well as for SOI MOSFETs

[11] to adjust the threshold voltage and improve the device SCEs. Halo implantation devices

show excellent output characteristics with low DIBL, no kink, higher drive currents, flatter

saturation characteristics, and slightly higher breakdown voltages compared to the


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conventional MOSFET. However, no such attempt has been reported on DG MOSFET. In

this paper, for the first time we have investigated the performance of the DG structure with

halo implantation using 2-D numerical simulations. The unique features of the double gate

single halo (DG-SH) device are explored and compared with those of a conventional DG

structure in terms of threshold voltage (Vth) variation with channel length and film thickness,

drain-induced barrier lowering (DIBL), on-current (Ion), off-current (Ioff), and the ratio of

transconductance to drain conductance (gm/gd) with an intention to explore the potential

benefits of the DG-SH structure over its counterpart.

2. DG-SH structure and its parameters

Schematic cross-sectional views of DG and DG-SH n-channelMOSFET implemented

in the 2-D device simulator MEDICI [12] are shown in Fig. 1. The doping in the p-type body

and n+ source/drain regions is kept at 1x1015cm-3 and 5x10

19cm-3 respectively. Pocket

implantation, NAP, on the source side of the DG-SH MOSFET is kept at 8x1017cm-3 while the

length of the pocket, Lp, is fixed at 4nm. The front-gate oxide thickness (tf) and back-gate

oxide thickness (tb) is taken as 2.5nm while the thin-film thickness (tsi) is kept at 20nm. The

values of different parameters used in our simulation are summarized in Table 1.

3. Simulation Results and Discussion

Simulations are performed to explore the characteristics of DG-SH SOI MOSFET with

conventional DG structure. Comparisons between the two structures are out on the basis of

threshold voltage variation with channel length, DIBL, saturation current (Ion), off-state

leakage current (Ioff), transconductance and drain conductance. The DIBL is measured as the

difference between the linear threshold (Vth,lin) voltage and the saturation threshold voltage

(Vth,sat). The linear threshold voltage is based on the maximum transconductance (gm)method

(linear extrapolation ofIDVDS to zero) at VDS= 50mV. The saturation threshold voltage is

based on a modified constant-current method at VDS= 0.75V [13]. The saturation current (Ion)


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is the drain current at VDS= 0.75V. The leakage current (Ioff) is the drain current at VGS= 0V

and VDS= 0.75V (orVDS= 0.05V, as stated). The transconductance, gm, is extracted from the

slope ofID- VGSat VGS= VDS= 0.75 V. The drain conductance (gd) is extracted from the slope

ofID- VDS between VDS= 0.5V and 0.75V at VGS= 1.0V.

Output characteristics of the DG and DG-SH SOI devices are compared for the same

channel length,L = 0.1m in Fig. 2 from which it is evident that the drive capability of DG-

SH is slightly less when compared with conventional DG structure. This is because of the

increase in the threshold voltage of DG-SH when compared to the DG structure. It can be

easily interpreted that while the transconductance is almost same for both the structures, the

drain conductance is much less in the case of DG-SH MOSFET, which leads to an increased

voltage gain. The other advantages of DG-SH MOSFET are the absence of kink in the drain

characteristics and a slight increase in the breakdown voltage when compared to the DG

MOSFET.

To gain an insight into the physical mechanism responsible for the improved

performance of the DG-SH structure, the surface potential profile is plotted at the interface of

the front-gate oxide and the thin film. Fig. 3 shows the surface potential plots for both DG

and DG-SH MOSFETs for channel lengths 0.1m and 0.2m. As can be observed from the

figure, a small step on the source side occurs in the surface potential profile in the case of

DG-SH structure due to the higher doping near the source end. There is no such step profile

in the surface potential if channel is larger than 0.1m for the both structures. Because of this

step in the surface potential profile, there is almost a zero shift in the minimum surface

potential [14] which leads to a reduced DIBL and an extended threshold voltage roll-off is

observed.

Fig. 4 shows the threshold voltage variation with channel length for DG and DG-SH

down to 80nm for a fixed film thickness, tsi = 20nm. The so called reverse short channel


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effect [15-18] is clearly seen here as the threshold voltage slightly increases with a decrease

in the channel length for DG-SH MOSFET. This is because of the screening of the drain

voltage as the channel length decreases due to the step function in the surface potential

profile and the surface potential minima is essentially least effected. On the other hand, the

threshold voltage rolls-off at a fast pace for DG MOSFET. In the case of DG structure, as the

channel length decreases, the drain bias shifts the surface potential minimum which leads to

the roll-off in threshold voltage. It can also be noted that the threshold voltage of the DG-SH

structure is slightly higher than that of DG structure due to the increase in the doping at the

source end in the former. Fig. 5 shows the threshold voltage variation with film thickness, tsi,

for a fixed channel length, L = 100nm. Due to the presence of the reverse short channel

effect, it can be observed that the threshold voltage dependence on film thickness in DG-SH

MOSFET is much less compared to the DG structure. Another important short channel effect

is the DIBL. Fig. 6 shows the DIBL parameter for both DG and DG-SH MOSFETs for

channel lengths down to 80nm. This figure demonstrates that the DIBL is far less in DG-SH

structure when the channel length is reduced below 120nm than in the case of DG structure.

Fig. 7 shows the subthreshold slope of the DG and DG-SH MOSFETs. It is clear from

the figure that the presence of single halo has not affected the the subthreshold behavior DG-

SH MOSFET and that both the structures have almost identical subthreshold slope of

around 60mV/dec. The subthreshold slope of the DG-SH is expected to degrade because of

the increase in the doping near the source end but as can be seen the increase is very small.

Due to the screening of the drain bias by the step function in the surface potential profile, any

increase in the leakage current is suppressed in the DG-SH structure and the off-state leakage

current is in fact less than that of the DG MOSFET as can be observed in Fig. 8. Fig. 8(a)

shows the saturation current (Ion) and the off-state leakage current (Ioff) for both the

configurations. It demonstrates that the saturation current of the DG-SH MOSFET is slightly


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lower than that of the DG MOSFET which is due to the increased threshold voltage of the

former structure. It can also be observed that the off-state leakage current in DG-SH structure

is much less and there is nearly an order of magnitude difference in this current for a drain

voltage, VDS= 0.75V, when the channel length is in the sub 100nm regime for the two

structures. In other words the on-off current ratio (Ion/Ioff) of DG-SH MOSFET is large

compared to that of a DG MOSFET. This can be clearly observed from Fig. 8(b), where the

Ion/Ioff ratio of both DG and DG-SH is shown.

Fig. 9 shows the transconductance (gm) and drain conductance (gd) of DG and DG-SH

MOSFETs. This figure clearly demonstrates that while the transconductance of both the

structures is identical, the drain conductance is much less in the case of DG-SH MOSFET.

This is primarily due to the reverse short channel effect and reduced DIBL in the case of DG-

SH MOSFET. Fig. 10 shows the voltage gain of both the structures. Because of the drastic

improvement in the drain conductance, a considerable increase in the voltage gain (gm/gd) can

be observed for the DG-SH MOSFET when compared with the DG-MOSFET making the

DG-SH structure more suitable for analog applications.

4. Conclusions

The concept of channel engineering has been applied for the first time to an

asymmetrical double gate (DG) SOI MOSFET. The features of the resulting double gate

single halo (DG-SH) SOI MOSFET have been studied in the context of its potential

integration in the current CMOS technology and a comparison has been drawn out with the

conventional asymmetric DG SOI structure. The unique features of the DG-SH that are not

easily available in the conventional asymmetric DG SOI devices include: threshold voltage

roll-up, reduced DIBL, kink free output characteristics and an increase in the drain

breakdown voltage.


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References

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SOI MOSFETs for Improved Reliability: A Review, IEEE Trans. Device and

Materials Reliability, 4 (3) (2004) 99-109.

[2] D.J. Frank, R.H. Dennard, E. Nowak, D.M. Solomon, Y. Taur, H. Wong, Device

scaling limits of Si MOSFETs and their application dependencies, Proc. IEEE, 89 (3)

(2001) 259-288.

[3] H. Horie, S. Ando, T. Tanaka, M. Imai, Y. Arimoto, S. Hijiya, Fabrication of double-

gate thin-film SOI MOSFETs using wafer bonding and polishing, SSDM, (1991) 165-

167.

[4] T. Tanaka, H. Horie, S. Ando, S. Hijiya, Analysis of p+ double-gate thin film SOI

MOSFETs, IEDM, (1991) 683-686.

[5] S. Venkatesan, G.W. Neudeck, R.F. Pierret, Dual gate operation and volume inversion

in n-channel SOI MOSFETs, IEEEElectron Device Lett., 13 (1) (1992) 44-46.

[6] K. Suzuki, Y. Tosaka, T. Tanaka, H. Horie, Y. Arimoto, Scaling theory of double-gate

SOI MOSFETs, IEEE Trans. Electron Devices, 40 (12) (1993) 2326-2329.

[7] T. Tosaka, K. Suzuki, H. Horie, T. Sugii, Scaling-parameter-dependent model for

subthreshold swing S in double-gate SOI MOSFETs, IEEE Electron Device Lett., 15

(11) (1994) 466-468.

[8] C.F. Codella, S. Ogura, Halo doping effects in submicron DI-LDD device design,

IEDM, (1985), 230231.

[9] T. Hori, A 0.1-m CMOS technology with tilt-implanted punchthrough stopper (TIPS),

IEDM, (1994), 7578.

[10] S. Odanaka, A. Hiroki, Potential Design and Transport Property of 0.1 m MOSFET

with Asymmetric Channel Profile, IEEE Trans. Electron Devices, 44 (4) (1997) 595-


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600.

[11] B. Cheng, V. Ramgopal Rao, J. C. S. Woo, Sub 0.18 m SOI MOSFETs using lateral

symmetric channel profile and Ge pre-amorphization salicide technology, Proc.IEEE

(1998) 113-114.

[12] MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto, CA, (1997).

[13] X. Zhou, K.Y. Lim, D. Lim, A simple and unambiguous definition of threshold voltage

and its implications in deep-submicron MOS device modeling, IEEE Trans. Electron

Devices, 46 (4) (1999) 807-809.

[14]

[15]

M. J. Kumar and A. Chaudhry, Two-Dimensional Analytical Modeling of Fully

Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Diminished

Short-Channel Effects, IEEE Tran. Electron Devices, 51 (4) (2004) 569-574.

H.I. Hanafi, W.P. Noble, R.S. Bass, K. Varahramyan, Y. Lii, A.J. Dally, A model for

anomalous short-channel behavior in submicron MOSFETs, IEEE Electron Device

Lett., 14 (12) (1993) 575-577.

[16] J. Tanaka, T. Toyabe, H. Matsuo, S. Ihara, H. Masuda, F. Otsuka, Reverse short-

channel effect of threshold voltage in LOCOS parasitic MOSFETs, Solid State

Electron., 38 (3) (1995) 567-572.

[17] S.T. Hsu, I.H. Kalish, K. Suzuki, R. Kawabata, H. Shibayama, Physical mechanism of

the reverse short-channel effect in MOS transistors, Solid State Electron., 34 (6) (1991)

605-608.

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submicrometer MOSFETs, IEEE Electron Device Lett., 13 (2) (1992) 92-94.

Figure Captions


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Fig.1 Cross-sectional view of (a) DG-SOI MOSFET (b) DG-SH SOI MOSFET

Fig. 2 ID-VDS characteristics of the DG-SH and DG-SOI MOSFETs for a channel length

L = 0.1m with a film thickness of 20 nm.

Fig. 3 Surface potential profiles of DG-SH and DG-SOI MOSFETs for channel lengths

0.2 m and 0.1 mwith a film thickness of 20 nm.

Fig. 4 Threshold voltage of DG-SH and DG SOI MOSFETs is plotted for different

channel lengths for a film thickness of 20 nm.

Fig. 5 Threshold voltage of DG-SH and DG SOI MOSFETs is plotted for different film

thicknesses for a fixed channel length 0.1 m.

Fig. 6 DIBL of DG-SH and DG SOI MOSFETs is plotted for different channel lengths

for a film thickness of 20 nm.

Fig. 7 Subthreshold slope of DG-SH and DG SOI MOSFETs is plotted for different

channel lengths for a film thickness of 20 nm.

Fig. 8(a) Variation ofIoff andIon with channel length for DG-SH and DG SOI MOSFET for

a film thickness of 20 nm.

Fig. 8(b) Ratio ofIon and Ioff with channel length for DG-SH and DG SOI MOSFET for a

film thickness of 20 nm at VDS= 0.75V.

Fig. 9 Variation of gm, gd with different channel lengths for DG-SH and DG SOI

MOSFETs.

Fig. 10 Variation of voltage gain with different channel lengths DG-SH and DG SOI

MOSFETs.


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Table 1 Simulation parameters

Parameter Value

Front gate oxide, tf 2.5 nm

Back gate oxide, tb 2.5 nm

Film thickness, tsi 20 nm

Body doping, NA 1015 cm-3

Source/drain doping, ND 51019 cm-3

Halo doping, NAP 81017 cm-3

Length of halo implantation,LP 4 nm

Work function p+ poly 5.25 eV

Work function n+ poly 4.17 eV


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Fig. 1

Si Polysilicon SiO2 Metal

p n+n+

DS

n

+

p+

tftsitb

L

(a)

G

tbp n+n+

DS

n+

p+

tftsiL

(b)

G

p+

LP


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0.0 0.5 1.0 1.5 2.00.0

0.51.0

1.5

2.0

2.5

3.0

DG

DG-SHDrainCurrent,ID(mA/m)

Drain Voltage, VDS(V)

VGS=1.5V

VGS=1.0V

VGS=0.5V

0.0 0.5 1.0 1.5 2.00.0

0.51.0

1.5

2.0

2.5

3.0

DG

DG-SHDrainCurrent,ID(mA/m)

Drain Voltage, VDS(V)

VGS=1.5V

VGS=1.0V

VGS=0.5V

Fig. 2


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0.00 0.04 0.08 0.12 0.16 0.200.0

0.4

0.8

1.2

1.6

2.0

DG

DG-SH

SurfaceP

otential(V)

Position along the channel (m)

VGS

= 0.25V

VDS

= 0.75V

0.00 0.04 0.08 0.12 0.16 0.200.0

0.4

0.8

1.2

1.6

2.0

DG

DG-SH

SurfaceP

otential(V)

Position along the channel (m)

VGS

= 0.25V

VDS

= 0.75V

Fig. 3


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VDS = 50mV

0.09 0.12 0.15 0.18 0.21

0.00

0.05

0.10

0.15

0.20

0.25

DG

DG-SHThresholdVo

ltage,

Vth

(V)

Channel length (m)

tsi = 20nm

VDS = 50mV

0.09 0.12 0.15 0.18 0.21

0.00

0.05

0.10

0.15

0.20

0.25

DG

DG-SHThresholdVo

ltage,

Vth

(V)

Channel length (m)

tsi = 20nm

Fig. 4


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L= 0.1m

VDS = 50mV

10 15 20 250.00

0.05

0.10

0.15

0.20

0.25

0.30

DG

DG-SHThresholdvoltage,

Vth

(V)

Film thickness, tsi(nm)

L= 0.1m

VDS = 50mV

10 15 20 250.00

0.05

0.10

0.15

0.20

0.25

0.30

DG

DG-SHThresholdvoltage,

Vth

(V)

Film thickness, tsi(nm)

Fig. 5


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0.09 0.12 0.15 0.18 0.210

5

10

15

20

25

30

DG

DG-SH

DIBL,

Vth,l

in-V

th,sat(mV)

Channel length (m)

0.09 0.12 0.15 0.18 0.210

5

10

15

20

25

30

DG

DG-SH

DIBL,

Vth,l

in-V

th,sat(mV)

Channel length (m)

Fig. 6


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VDS = 50mV

0.08 0.12 0.16 0.2060

61

62

63

64

DG

DG-SH

Subthresholdslope,

S(mV/dec)

Channel length (m)

VDS = 50mV

0.08 0.12 0.16 0.2060

61

62

63

64

DG

DG-SH

Subthresholdslope,

S(mV/dec)

Channel length (m)

Fig. 7


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0.08 0.12 0.16 0.20

210-8

Channel length (m)

DG

DG-SH

0.0

0.3

0.6

0.9

1.2

1.5

Saturationcurrent,Io

n(mA

/m)

OffstateLeakagecurrent,Ioff

(A/m)

410-8

610-8

810-8

10-7

0

VDS = 0.75V

VDS= 50mV

0.08 0.12 0.16 0.20

210-8

Channel length (m)

DG

DG-SH

0.0

0.3

0.6

0.9

1.2

1.5


n(mA

/m)


n(mA

/m)

OffstateLeakagecurrent,Ioff

(A/m)

410-8

610-8

810-8

10-7

0

VDS = 0.75V

VDS= 50mV

Fig. 8 (a)

0.08 0.12 0.16 0.200

6104

1.2 105

1.8 105

2.4 105

3.0 105

DG

DG-SH

Channel length (m)

Ion

/Ioff

VDS= 50mV

0.08 0.12 0.16 0.200

6104

1.2 105

1.8 105

2.4 105

3.0 105

DG

DG-SH

Channel length (m)

Ion

/Ioff

VDS= 50mV

Fig. 8(b)


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0.08 0.12 0.16 0.200.0

0.5

1.0

1.5

2.0

2.5

3.0

DG

DG-SH

gm,

gd

(mS/m)

Channel length (m)

gm

gd

0.08 0.12 0.16 0.200.0

0.5

1.0

1.5

2.0

2.5

3.0

DG

DG-SH

gm,

gd

(mS/m)

Channel length (m)

gm

gd

Fig. 9


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0.08 0.12 0.16 0.200

2

4

6

8

10

DG

DG-SH

Volta

gegain,gm

/gd

Channel length (m)

0.08 0.12 0.16 0.200

2

4

6

8

10

DG

DG-SH

Volta

gegain,gm

/gd

Channel length (m)

Fig. 10

investigation of the novel attributes of a single-halo double gate soi mosfet: 2d simulation study

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