Introductory project

Development systems• Design Entry

– Foundation ISE– Third party tools

• Mentor Graphics: FPGA Advantage

• Celoxica: DK Design Suite• Design Synthesis

– XST: Xilinx Synthesis Technology

– Mentor: Leonardo Spectrum– Synplicity: Synplify Pro

– Celoxica: DK Design Suite

• Simulation– Mentor: Modelsim

– Aldec: Active-HDL

– Celoxica: DK Design Suite

Design Flow

• Design Entry– Schematic

– Hardware description language (VHDL, Verilog)

– Intellectual Property IP blocks

– Xilinx CoreGen

• Design Synthesis– High level description ->

Circuit

Design Flow

• Design Verification– Behavioral Simulation

• Checking high level description of the circuit

– Functional Simulation• Checking synthesized

circuit– Timing Simulation– Static Timing Analysis

• Searching critical paths– In-Circuit Verification

Design Flow

• Optimization (NGDBuild)– Merge multiple design

files into a single netlist

• Mapping (MAP)– Group logical symbols

from the netlist (gates) into physical components (slices and IOBs)

Design Flow

• Place & Route (PAR):– Place components onto

the chip, connect the components, and extract timing data into reports

• Bitstream Generation (BitGen)– Create configuration file

Create new project• Select: File -> New Project• Choose project directory and name (myand2)• Set top-level source type to HDL

Set Device PropertiesSelect:• Family: Spartan3E• Device: XC3S500E• Package: FG320• Speed -5

• Synthesis tool: XST• Simulator: Modelsim-SE Mixed• Preferred Language: VHDL

Create new source

• Click New Source…• Select VHDL Module

from the list

• Choose File name (myand2)

Define Module

• Set two inputs (a,b) and one output (c)

Project Navigator

• Source files• Built-in editor / Report

summary• Processes / Utilities• Console

Simple VHDL source

Create Testbench• Right click

myand2 - behavioral

in the sources window and select New Source

• Select VHDL Test Bench from the list

• Choose File name (myand2_tb)

Associate testbench

Find testbench files

• From the Sources for: list select Behavioral Simulation

• Open myand2_tb

Create stimulus

Simulation

• In the Processes for Source window open ModelSim Simulator

• Right click Simulate Behavioral Model and select Properties…

Set Simulation Properties• Set Simulation

Resolution to 1ns

The user interface of the ModelSim VHDL simulator

• Compile, Compile All, Simulate, Break

• Restart, Run length, Run, Continue Run,

• Run –All, Step, Step Over, Profiling

• Insert Cursor, Delete Cursor

• Previous Transition, Next Transition

• Zoom In/Out, Zoom Full

• Zoom to Active Cursor

Design Synthesis

• Set Sources for to Implementation

• Select myand2 - Behavioral

• In the Processes for window double click Synthesize - XST

View RTL Schematic

View Technology Schematic

Create Implementation Constraints

• Right click

myand2 - behavioral

in the sources window and select New Source

• Select VHDL Test Bench from the list

• Choose File name (myand2)

Assign Package Pins• In the Processes

window open User Constraints

• Select Floorplan I/O – Pre-Synthesis

Assign Package Pins

• Set Loc– a: H18– b: G18– c: J14

Implement Design

• In the Processes for window double click Implement Design

• Check Place and Route Report for LOCed IBUFs/IOBs

Set Programming File Properties

• Right click Generate Programming File in the Processes for window and select Properties…

• Set Startup Options / FPGA Start-Up Clock to JTAG Clock

• Double click Generate Programming File

Configuring the device• Attach and Turn On

Nexys2 board• Start Digilent / Adept /

ExPort

• Click Initialize Chain• Bypass configuration

ROM

Configuring the device• Browse to the project

directory• Select myand2.bit

• Click Program Chain• Test your first circuit

implemented on FPGA