introduction_5

8/7/2019 INTRODUCTION_5

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ACKNOWLEDGEMENT

We take this opportunity to thank all those who have helped us through the course of our

seminar4 bit microprosessor by vhdl

We are deeply indebted to our guide Mrs. K.G.Bhuva. It is his immense devotion of time,

invaluable knowledge and compassionate behavior which has enabled us to complete the task

and the reach the shores. We are especially grateful to him for allowing us the independence

and the flexibility to working way through problems, but yet at the same time making us see

missed perspectives and guiding our thought process in a manner laid down by the next

tradition of free scientific inquiry. We feel honored to have done our seminar 4 bit

microprosessor by vhdl under his guidance.

We are indebted to Mr. M.P.Patel and all the faculty members of Department of

Electronics & Tele-communication Engineering for their constructive suggestions and

encouragement.

The Acknowledgement would never be completed if we do not acknowledge the immense

help we received from our Institute, GOVERNMENT ENGINEERING COLLEGE,

BHARUCH in the form of internet ,library and project lab facilities whenever required .We

thank our faculty members for constructive criticism of our ideas. We thank each other in the

team for the initial conflicts that lead us to better results. It was really a wonderful journey

with the team. We also thank all our friends for their moral support. We thank all those whose

name do not appear here but have helped us directly or indirectly, all the way.

With Regards,

Pranav Mehta


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CONTENT

1) ABSTRACT..32)INTRODUCTION..33)Hardware Description Lang. (HDL)..4

History of VHDL5

4) INTRODUCTION TO HDL..6Entity7

Architecture8

Library9

5) Software mannual..106)Entity-Architecture Pair..117)INTRODUCTION TO 4-BIT MICROPROCESSOR ..128)FUNCTIONS OD DIFFERENT PARTS OF P..13

ACCUMULATOR

ARITHMATIC UNIT

INPUT PORT

OUTPUT PORT

9) PHASE COUNTER..1810) PROCESS OF EXECUTION1911) TABLE FOR CONTROLLING SIGNAL GENERATES BY

MICROINSTRUCTION..24


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ABSTRACT

Now a days the chip design is vary specialism and have wide network. That have two

main parts like embaded and vlsi. Now the embedded have the most all have the knowledge and

usage but the other vlsi have small area that have not more easy and available .

Now the india have the introduce the vlsi by vhdl.the front end is vhdl that have to made

up by out of country. And that was not widely varylog and vhdlis most widely up to 80% usage area.

INTRODUCTION

VHDL is an acronym for VHSIC (very high speed integrated circuit) Hardware

Description Language.

VHDL is used to model a digital system at many levels of abstraction ranging from

the algorithmic level to the gate level.


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Hardware Description Lang. (HDL)

A software programming language that is used to model a piece of hardware.

Other than VHDL different hdls are Verilog, ABEL, PALASM, System C ,CUPL,

and etc .but VHDL and Verilog are the most widely used HDLs.

The major difference between hardware description programming languages and

others is the integration of time.

VHDL(VHSIC HDL)

1980 USA Department of Defense 1987 IEEE Standard 1076 Verilog HDL 1981 Gateway Design Automation 1995 IEEE Standard 1364


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Summary: History of VHDL

1981 Initiated by US DoD to address hardware life-cycle crisis .

1983-85 Development of baseline language by Intermetrics, IBM and TI .

1986 All rights transferred to IEEE .

1987 Publication of IEEE Standard .

1994 Revised standard (named VHDL 1076-1993) .

2000 Revised standard (named VHDL 1076 2000, Edition). 2002 Revised standard

(named VHDL 1076-2002) .

2007 VHDL Procedural Language Application Interface standard (VHDL 1076c-

2007) .

2009 Revised Standard (named VHDL 1076-2008) .


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INTRODUCTION TO HDL

HDL refers to Hardware Description Language

Use to model any Digital system or Electric behavior of any system.

It can describe circuits operation, its design, and test to verify its operation.

HDL provides features allowing concurrent (parallel) events to be Describe

In hardware events are concurrent, so a software language cannot be used for describing

and simulating hardware.

This language can be further classified into two subcategories-

(a) VHDL

(b) Verilog HDL

Classified stages of VHDL

Entity

Architecture

Configuration

Package

Library


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ENTITY

A designs interface signals to the external circuitry.

ENTITY PORTS

Entity port is a signal with a specified data flow direction which provides an interconnection

between the component and its environment.

Modes of ports

i. IN : input Value can be read but not assignedii. OUT : output Value can be assigned but not read

iii. INOUT : bi-directional Value can be read and assignediv. BUFFER : out port with read capability.It is an output port

The assignment of hardware I/O buffers to the ports (push-pull, tri-state , differential output,

etc.) depends on the implementation and the target technology .

(Use of buffer ports is not recommended.)


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ARCHITECTURE

An architecture specifies the behavior ,function ,interconnections and the relationship

between the inputs and the outputs of an entity.

An entity can have more than one architecture .

There can be no architecture without an entity .

Each architecture is bound to an entity using the configuration statement .VHDL

architectures can be classified as

Behavioral

Defines a sequentially described functioning of the design.

Structural

Defines interconnections between previously defined components.

Dataflow or Mixed

A combination of structural and behavioral architectures .


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LIBRARY

Library is a collection of compiled VHDL design units .

WORK and STD are the default libraries provided by the language. They need not

be explicitly declared.

All the compiled designs are put into WORK by default unless specified otherwise.

Commonly used functions, procedures and user data types can be compiled into a

user defined library for use in all designs.

Comments --File name, Author name, etc

Library LIBRARY ieee

Use clause & USE ieee.std_logic_1164.ALL Package

Entity Declaration Entity IS

PORT (a: IN bit;

b; OUT bit);

END ;


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Software mannual.


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Entity-Architecture Pair


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INTRODUCTION TO 4-BIT MICROPROCESSOR (VSM)

The very simple microprocessor introduces the basic concept of microprocessor architecture in

the simplest possible way.


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FUNCTION OF ACCUMULATOR- A

The accumulator A stores the intermediate results computed by the microprocessor.

Accumulator A is a 4 bit register depend upon enable A. The accumulator result is placed on

internal bus. It is bidirectional with the bus. And it sends the data to the arithmetic unit for

operation.

BLOCK DIAGRAM OF ACCUMULATOR A


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BLOCK DIAGRAM OF ACCUMULATOR B

The accumulator B stores the intermediate results computed by the microprocessor.

Accumulator B is a 4 bit register depend upon enable B. The accumulator result is placed on

internal bus. It is bidirectional with the bus. And it sends the data to the arithmetic unit for

operation.


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FUNCTION OF INPUT REGISTER

The input register give the opportunity to transfer the data from the outside world inside

the microprocessor. That means it transferred the data from the key pad to the

microprocessor in binary format. This is dependent on enable-in pin and it transfers the data

directly that means parallel in and parallel out.

BLOCK DIAGRAM OF INPUT REGISTER


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FUNCTION OF OUTPUT REGISTER

The output register transfer the contents of the internal bus to the outside world. It

is mainly used to display the final result on the screen. That means it transfers the

binary signals at the output of system which will operate the display and provide

output.

BLOCK DIAGRAM OF OUTPUT REGISTER


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SIGNAL GENERATION FOR PHASE COUNTER


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PROCESS OF EXECUTION

Phase Name Description

Phase-1 Address state The contents of the memory is loaded by the instruction

registers.

Phase-2 Increment state The program counter address is incremented. The register

provide the microinstruction decoder with the instruction.

Phase-3 Execute step-1 Depending on the instruction the microprocessor make the first

step of the execution phase.

Phase-4 Execute step-2 The microprocessor makes the second step of the execution

phase.


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USE OF PHASE-1 COUNTER IN VSM


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TABLE FOR CONTROLLING SIGNAL GENERATES BY

MICROINSTRUCTION

Now the above table shows that the all that data had read is just to be shown

which concern with eachother are as per they needed. As per one xample the

read mem. Is all have the same value and load a have not connected with one.

And add_sub select have just connected with sub line that is defined. All the

data is drown to that above.


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BLOCK DIAGRAM FOR VSM

I. Release the main resetII. Activate the main clock

III. See the 4 phasesIV. Follow the current inst.V. Monitoring the memory

VI. Monitoring the internal busVII. Interact with the processor

VIII. Output is processed by the microprocessor


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ADVANTAGE OF HDL Cont..

Supports multiple level of abstraction.

Well suited for synthesis and verification .

Shorter time to market.

Design reused is enabled.

Produce better design.

EDA Tool independent

Technology independent

introduction_5

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