introduction to vlsi degital design ~...

2499-4

International Training Workshop on FPGA Design for Scientific Instrumentation and Computing

Sandro BONACINI

11 - 22 November 2013

CERN, Geneva Switzerland

Introduction to VLSI Degital Design Transistors

Sandro Bonacini Transistors 1

Outline

• Introduction• Transistors

– DC behaviour– MOSFET capacitances

• The CMOS inverter• Technology• Scaling• Gates• Sequential circuits• Storage elements

Many slides are a courtesy of Paulo Moreira


“Making Logic”

• Logic circuit “ingredients”:– Power source– Switches– Inversion– Power gain (for multiple

stages)• Power always comes from

some form of external generator.

• NMOS and PMOS transistors:– Can perform the last three

functions– They are the building blocks

of CMOS technologies!


Silicon switches: the NMOS

Boron

Arsenic&

Phosphorous


Silicon switches: the NMOS

Above silicon:• Thin oxide (SiO2) under the gate areas;• Thick oxide everywhere else;

Channel doping:• 0.13 m technology• ~1017 atoms/cm3


Silicon switches: the PMOSImportant geometry parameters- W (width)- L (length)


MOSFET equations• Cut-off region:

• Linear region:

• Saturation:

• Oxide capacitance

• Process “transconductance”

Ids Vgs VT 0 0 for

Ids CoxW

LVgs VT Vds

Vds Vds Vds Vgs VT

2

21 0 for

IdsCox W

LVgs VT Vds Vds Vgs VT

22

1 for

Coxox

tox

F / m2

Coxox

tox A / V2

0.25m process

tox = 5 nm (~10 atomic layers)

Cox = 5.6 fF/m2

(1)

(2)

(3)

65 nm process

tox = 2.4 nm (~5 atomic layers)

Cox = 15 fF/m2

g

d

s

b


MOS output characteristics

• Linear region:Vds<Vgs-VT

– Voltage controlled resistor

• Saturation region:Vds>Vgs-VT

– Voltage controlled current source

• Curves deviate from the ideal current source behavior due to:– Channel modulation

effects

• (Vgs0 is the maximum Vgs, Ids0 is the maximum Ids)

Sandro Bonacini

MOS output characteristics

0

50

100

150

200

250

0 0.5 1 1.5 2 2.5

Ids

[uA]

Vds [V]

L = 240nm, W = 480nm

Vgs = 0.7V (< Vt)Vgs = 1.3VVgs = 1.9VVgs = 2.5V

L = 24um, W = 48um

0

50

100

150

200

250

300

350

400

0 0.5 1 1.5 2 2.5

Vds [V]

Ids

[uA

]

Vgs = 0.7V (<Vt)Vgs = 1.3VVgs = 1.9VVgs = 2.5V

– Channel modulation effects

– Visible in small devices


Is the quadratic law valid?Ids - Vgs (Vds = 2.5V, Vbs = 0V)

0

100

200

300

400

500

600

0 0.5 1 1.5 2 2.5Vgs [V]

Ids

[uA

]

L = 24um, W = 48um

L = 2.4um, W = 4.8um

L = 240nm, W = 480nm

Quadratic law “valid” for long channel devices only!

– Velocity saturation(from transverse field)

10

Temperature dependence

• Transistor characteristics are influenced by temperature (T)

– VT decreases linearly with T– μ decreases with T– Ileakage increases with T

• Circuit performances are worst at high temperature

Id (uA)

-50.0

0.0

0.0 .25 .5 .75 1.0 1.25Vd (V)

50.0

200.0

100.0

150.0

Vg temp .0.7 -500.7 250.7 1250.95 -500.95 250.95 1251.2 -501.2 251.2 125

125 oC

-50 oC

NMOS W=240nm L=60nm

50.0

200.0

-50.0

150.0

0.0 .25 .5 .75 1.0 1.25dc (V)

0.0

I (uA)

100.0

/M/M/M

Vdtemp

1.2 -501.2 251.2 125

Id (uA)

Vg(V)

μ dec.

VT decrease

μ dec.


Bulk effect• The threshold depends on:

– Gate oxide thickness– Doping levels– Source-to-bulk voltage

• If Vsb > 0 the threshold voltage is higher than Vsb = 0

n+ n+p+

V>0 V>VT0

n+ n+p+

V=0 V=VT0

0

100

200

300

400

500

600

0 0.5 1 1.5 2 2.5

Vgs [V]

Ids

[uA

]

L = 24um, W = 48um, Vbs = 1L = 24um, W = 48um, Vbs = -1V

W = 24m

L = 48m

Vsb = 0V

Vsb = 1 V

Transistors 12

Weak inversion• Is Id=0 when Vgs<VT?• For Vgs<VT the drain current

depends exponentially on Vgs

• Weak inversion is when:

• In weak inversion and saturation (Vds > ~150mV):

where

• Used in very low power designs• Highest gm/Id

• Slow operation(n is the slope factor)

nkTqV

dd

gs

eIL

WI 0

nkTqV

d

T

eq

kTnI

2

0 2

SToxd Iq

kTLWCnI

2

2 IST

IST

2

00 22

11

Tg VVn


Gain & Inversion• Gain:

– Signal regeneration at every logic operation

– “Static” flip-flops• -> clock can be turned off

– “Static” RW memory cells• Inversion:

– Intrinsic to the common-source configuration

• The gain cell load can be:– Resistor– Current source– Another gain device (PMOS)


Outline

• Introduction• Transistors

– DC behaviour– MOSFET capacitances– MOSFET model

• The CMOS Inverter• Technology Scaling• Gates• Sequential circuits• Storage elements


What causes delay?

• In MOS circuits capacitive loading is the main cause of delay.

• Capacitance loading is due to:– Device capacitance– Interconnect capacitance

(RC delay in the interconnects will be addressed later)

Assuming VT = 0

VIN

0

Vdd

t

VOUT

0

Vdd

t

50% leveldelay

CVINVGS

I (VGS-VT)2

Ideal MOS d

ss

g


MOSFET capacitances

• MOS capacitances have three origins:– The basic MOS structure– The channel charge– The pn-junctions depletion regions

Source Drain

Gate

CSB CDB

CGB

Bulk

CGS CGD


MOS Structure Capacitances

• Source/drain diffusion extend below the gate oxide by:xd - the lateral diffusion

• This gives origin to the source/drain overlap capacitances:

• Gate-bulk overlap capacitance:

C C C WC

gso gdo o

o

(F / m)

C C L Cgbo o o ' ', (F / m)

L

Source Drain

Gate-bulkoverlap

Gate

W

xd xd

Leff

tox

Cgso CgdoG/S overlap G/D overlap

Source/Drain

Overlap OverlapCgbo/2

Weff


MOS Structure Capacitances

0.24 m process

NMOSL(drawn) = 0.24 mL(effective) = 0.18 mW(drawn) = 2 mCo (s, d, b) = 0.36 fF/mCox = 5.6 fF/m2

Cgso = Cgdo = 0.72 fFCgbo = 0.086 fF

Cg = 2.02 fF


Channel Capacitance

Operation region Cgb Cgs Cgd

Cutoff Cox W L 0 0

Linear 0 (1/2) Cox W L (1/2) Cox W L

Saturation 0 (2/3) Cox W L 0

• The channel capacitance is nonlinear

• Its value depends on the operation region

• Its formed of three components:Cgb - gate-to-bulk capacitanceCgs - gate-to-source capacitanceCgd - gate-to-drain capacitance

Cg = Weff Leff Cox

Cg + Cgbo

2/3 Cg + Cgso

Gate-to-bulk

1/2 Cg + Cgbo

Cgdo , Cgso

Cg

bo

Gate-to-source

Gate-to-drain

Off Saturated Linear


Junction capacitances

• Csb and Cdb are diffusion capacitances composed of:– Bottom-plate capacitance:

– Side-wall capacitance:C C W Lbottom j s

C C L Wsw jsw s 2

Side wall Bottom plate

Xj

W

Channel

Channel-stopimplant

Ls


Junction capacitances

0.24 m process

NMOSL(drawn) = 0.24 mL(effective) = 0.18 mW(drawn) = 2 mLs = 0.8 mCj (s, d) = 1.05 fF/m2

Cjsw = 0.09 fF/m

Cbottom = 1.68 fFCsw = 0.32 fF

Cg = 2.02 fF


Source/drain resistance

• Scaled down devices higher source/drain resistance:

• In sub- processes silicidation is used to reduce the source, drain and gate parasitic resistance

RLW

R Rs ds d

sq c,,

Sourcecontact

Draincontact

Ld Ls

0.24 m process

R (P+) = 4 /sqR (N-) = 4 /sq

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