introduction to vhdl - ymk.k-space.orgymk.k-space.org/me_vhdl2.pdf · entity mux select is port...
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![Page 1: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic](https://reader034.vdocuments.site/reader034/viewer/2022050807/5aedcf4c7f8b9a572b8bd28d/html5/thumbnails/1.jpg)
Introduction to VHDL
Modules #6 and #7
Digilent Inc. Course
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Data Selectors / Multiplexers
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Bus Multiplexer
![Page 4: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic](https://reader034.vdocuments.site/reader034/viewer/2022050807/5aedcf4c7f8b9a572b8bd28d/html5/thumbnails/4.jpg)
MUX VHDL Example:
Selected Signal Assignment
![Page 5: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic](https://reader034.vdocuments.site/reader034/viewer/2022050807/5aedcf4c7f8b9a572b8bd28d/html5/thumbnails/5.jpg)
Bus MUX VHDL Example:
Selected Signal Assignment
![Page 6: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic](https://reader034.vdocuments.site/reader034/viewer/2022050807/5aedcf4c7f8b9a572b8bd28d/html5/thumbnails/6.jpg)
More Complex MUX VHDL:
Conditional Assignment
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Decoder
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Decoder VHDL Example:
Selected Signal Assignment
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DeMultiplexer (DeMUX)
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DeMUX VHDL Code
� Assignment: modify the code of a MUX to implement a DeMUX
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7-Segment Decoder
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7-Segment Decoder VHDL Code
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Priority Encoder
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Shifters
![Page 15: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic](https://reader034.vdocuments.site/reader034/viewer/2022050807/5aedcf4c7f8b9a572b8bd28d/html5/thumbnails/15.jpg)
Shifters
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Shifters VHDL Example
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Bit-Slice Design Method
� Consider a circuit that works on a pair of bits
� Goal is to create a circuit that can simply be replicated N times
� once for each bit
� Some circuits defy this approach
� Information passing between adjacent bits
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Comparators
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Comparator Bit-Slice Design
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Comparator Bit-Slice Design
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Adders
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Arithmetic and Logic Unit (ALU)
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8-Bit, 4-Function ALU VHDL
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Assignment
� Lab Project P6
� Do only on Xilinx Webpack
� Simulate to show results
� No Digilent board demo is necessary