introduction to semiconductor industry & experiences sharingpre.tir.tw/099/fju/may29.pdf ·...
TRANSCRIPT
Confidential
Introduction to Semiconductor
Industry & Experiences Sharing
S R Sheu
VP of Engineering Services, UMC
May 29, 2018
Confidential 2
Outline:
1. History & Prospect of Semiconductor Industry
2. Semiconductor Applications
3. Semiconductor Supply Chain Eco-System
4. Introduction to UMC
5. Working Experience Sharing & Suggestions
6. Q&A
2
History of Human Civilization
Stone Age Bronze Age
Iron Age
Silicon Age
Machine Age
Source: M. Sze
Confidential 3
(IC Chronology)
1823
Silicon was Discovered
1904
Diode Vacuum Tube was Invented
1947
Bipolar Transistor was Invented
1958 發明積體電路
Integrated Circuit was Invented
1959 發展小型積體電路
SSI was Developed(RTL)
1964 P
P MOS IC was Developed
1967 TTL ,
TTL MSI and C MOS IC were Introduced
1968 P
P MOS LSI was Introduced By Intel
1979 64K DRAM ( VLSI )
64K DRAM was Introduced By IBM
Confidential 4
Confidential 5
First Transistor: Point Contact Transistor
• 1st Transistor
(Ge) was
invented by:
William Shockley,
Walter Brattain &
John Bardeen (1947)
Award: Nobel Prize in 1956
~ 50 µm
Confidential 6
First IC
6
• First IC by Jack Kilby (Feb, 1958) at TI
1 transistor, 1 capacitor and 3 resistors on Ge bar. Awards: Nobel Prize in Physics (2000)
U.S. Patent 3,138,743
"Miniaturized Electronic Circuits",
the first integrated circuit, was filed
on February 6, 1959
From Wikipedia, the free
encyclopedia
Confidential 7
First Monolithic Silicon IC Chip
7
• First planar commercial IC made on Si by Robert
Noyce (1961) at Fairchild Company
For NASA and camera control.
10mm silicon wafer
4 transistors:
From Wikipedia
Confidential 8
The Integrated Circuit
P. 8
Confidential 9
IC v.s. Wafer
P. 9
Die
Wafer (42 millions transistors)
Wafer Diameter: 2 inch -> 4 inch/ 5 inch -> 6 inch -> 8 inch -> 12 inch ->..
Yield Model: Bose-Einstein Model, Murphy’s, Poison’s… for Defect
Density & Yield prediction
The Growth of Single Crystal Silicon
Seed Holder
-
Silicon Seed
(100), (111)..
Ingot
Melt
Silica Crucible
Czochralski Process:
* Floating Zone Process for Higher Resistance
Confidential 11
12
2” , 4” , 6” , 8” Wafer
Confidential 12
12” Wafer
Confidential 13
Confidential 14
IC Integration level
14
Confidential 15
Moore's law
15
Moore's law: Intel
Founder: Gordon
Moore: Integrated
Circuit 上可容納的Transistor 數目,約每隔兩年便會增加一倍;經常被參照的「18個月」,是由英特爾 CEO
David House所說:預計18個月會將晶片的效能提高一倍(即更多的電晶體使其更快)。[1]
L=5nm
L=5000 nm
From Wikipedia, the free encyclopedia
Shrinkage
Confidential 16
IC Design:
CMOS Inverter
Metal 1, AlCu
P-Epi P-Wafer
N-Well P-Well
PMD
p + p + n + n +
W
Metal 1 Contact
P-well N-well Polycide gate and local
interconnection
N-channel active region
N-channel S/D
P-channel active region
P-channel S/D
Shallow trench isolation (STI)
Vss
Vdd
NMOS PMOS
Vin
Vout
STI
• Schematics
Inverter
• Layout
IC Device Structure
• Cross-
section
L: Channel Length
Confidential 17
P. 17
Brief Process Flow - First Layer (Diffusion)
P-sub
(Silicon wafer)
SiN (Nitrid)
Pad oxide
1.1. Wafer Start
1.2. PAD Oxidation (stress buffer)
1.7. SiN (Nitrid) Deposition
1.8. Diffusion Lithography :
1.8.1 P.R. coating
1.8.2 Lithographic Exposure
1.8.3 Development
Photo Resistor coating
Diffusion mask Lithographic Exposure
Diffusion P.R.
P-sub
(Silicon wafer)
SiN (Nitrid)
Pad oxide
P. 18
Diffusion P.R.
P-sub
(Silicon wafer)
SiN (Nitrid)
Pad oxide STI STI
Brief Process Flow - First Layer (Diffusion)
1.7. Trench (STI) Plasma Etching
1.7.1 SiN Etching
1.7.2 Silicon Etching
1.8. Photo Resistor remove
Confidential 18
P. 19
Brief Process Flow - Backend Flow (Aluminum line)
P-sub
NWELL STI
PWELL
Poly PR coating
Poly Mask NLDD
N-LDD
N-PKT N-LDD
N-PKT
P-LDD PR
P-LDD P-PKT
N+ PR
N+ N+
P+ PR
P+
SAB
PSG
USG
PR Coating
Contact Mask
PR coating Contact PR Metal 1
Contact plug
PR Coating
Metal 1 mask
Metal 1 PR
Metal 1
HDP-1
PEOX
Cap Oxide
PR Coating
MVIA1 mask
MVIA1 PR Metal 2 Stepper Exposure
Stepper Exposure
12. IMD deposition
12.1 HDP-Oxide deposition
( Gap filling)
12.2 PE-Oxide Deposition
( Planarization and uniformity)
12.3 IMD CMP
12.4 Cap PE-Oxide
13. MVIA plug formation
13.1 MVIA Lithography cycle
13.2 MVIA Etching and PR strip
13.3 Glue Layer deposition
(Ti + TiN for plug adhesion)
13.4 WCVD filling
13.5 WCMP
13.6 Metal Liner deposition
(Ti + TiN for Metal adhesion)
13.7 Metal Sputter
Confidential 19
Applications with New Innovations
Every 2 yrs: Feature size 0.7x shrinkage, Area ~50% scale-down
New technology for device performance and power
Technology Challenges & Opportunities
Confidential 20
Confidential 21
Scanner machine type (Light source / l )
Pro
cess ge
ne
ration
Immersion Scanner
K-SCANNER (KrF / 248nm)
A-SCANNER (ArF / 193nm)
0.13m
90nm
65nm
40nm
28nm
14nm
IA-SCANNER (ArF / 193nm)
Scanner Light Source Application for Process Generation
Patterning resolution can be enhanced by wavelength reduction
R = k1 * l / NA 0.35m
I-STEPPER (I-Line / 356nm)
0.25m
0.18m
0.15m
Confidential 22
(1972~ now)
28nm
Confidential 23
IC Process Scaling Down Gate length: scaling from 10um (1971) to 10nm (2017) Moore’s Law
Transistor: 2D (Planar) to 3D (FinFet)
Planar FinFet
Frederic Boeuf, Device challenges and opportunities for 10nm and below CMOS nodes, IEDM Short Course, 2013
Technology Challenges & Opportunities
Confidential 24
WW Semiconductor Market Outlook
High growth of WW semiconductor market to ~$500B in 2019 with
CAGR(‘11~’19) ~5.2%
Source : Gartner
2011-2019 CAGR : 5.2%
308 300 315
343 335 346
420
470
502
0
100
200
300
400
500
600
2011 2012 2013 2014 2015 2016 2017 2018 2019
USD
$B
WW Semiconductor revenue & forecast
Confidential 25
Semiconductor Market Revenue (devices & applications)
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Non-Optical
DSP
8-Bit
16-
Bit
32-
Bit
22
MCU/DSP
Compute
Embedded
47
MPU
Automotive
Communications
Consumer
Data Processing
Industrial
Application-Specific
150
Data
Co
nve
rter/
Sw
itc
h/M
ult
iple
xe
r O
ther
An
alo
g
Vo
ltag
e R
eg
ula
tor/
Re
fere
nce
26
Analog
Image
Sensor
LED
Other
Optoelectronics
Photosensor
37
Optoelectronics
Dio
des
Other
Discrete
Tra
nsis
tors
23
Discrete
Dis
pla
y D
rive
r F
PG
A/P
LD
O
ther
Lo
gic
14
General
Purpose
Logic
No
no
pti
ca
l S
en
so
rs
13
Microcomponent Logic OSD Analog
Military/Civil Aerospace (US$B)
<0% 0~5% 5~10% >10% CAGR(‘17~’20) Note: exclude memory
Confidential 26
Confidential 27
Outline:
27
1. History & Prospect of Semiconductor Industry
2. Semiconductor Applications
3. Semiconductor Supply Chain Eco-System
4. Introduction to UMC
5. Working Experience Sharing & Suggestions
6. Q&A
Confidential 28
Semiconductor Market Shift –
Application Diversification
Yole, 2017 Semicon Taiwan
Confidential 29
Industrial Segments & Applications
• Industrial 5-Segment : Mobility, IoT, Automotive, HPC & Memory
• 5G* Modem / Antenna
• RF* / FEM*
• Networking Switch
• AP / BB
• PMIC* / Sensors* / MEMS*
• Touch Driver / Touch ID
Mobility
• MCU
• Sensors (CIS* / MEMS*)
• PMIC*
• Memory (eFlash*)
• RF* (Connectivity)
IoT
• ADAS / AI
• Infotainment
• Body Electronic
• Power / Micro Control
• Sensors* / MEMS*
Automotive
• Crypto Currency
• Networking (Router /
Switch)
• AI Cloud
• GPU / CPU / FPGA
HPC
• DRAM (DDR4/5)
• Flash (Universal Flash
Storage)
• HBM / HMC
Memory
Confidential 30
Mobile Phone -> Smart Phone
30
1994 2017 2000 2007 2009 2013 2013 2011
Smartphone
AR/VR Market Innovation
Epson
Moverio BT-200
$699.99
Oculus
Rift
$599
Smartphone
HTC
Vive
$799(
Microsoft
HoloLens
$3,000
Vuzix
M100
$999.99
Timeline
Virtual Reality (VR) Augmented Reality (AR) Mixed Reality (MR)
Message on glasses lens Contents on display Contents on display or lens
Developing
(Magic Leap’s patent)
AR/VR/MR drives the demands on head mounted display (HMD)
Q4, 2016 Q1, 2016 2015
Pokemon Go
Plus (2016/9)
Google Glass
($1,500)
[Cancelled]
2013
Ma
in E
qu
ip.
2n
d D
evic
es
/
Ac
ce
ss
ori
es
Game
Console PC/NB Game
Console PC/NB
In near future
Pokemon Go
Smartphone
Confidential 31
Q1, 2018
Confidential 32
Automotive Products– Another Carrier of IC
Confidential 33
Automotive Package Types & Requirement
• Automotive package must endure extreme stress in harsh conditions
• Various categories apply different package type with different Grades
• AEC-Q100 Grade 0~3 packaging solutions are ready in major OSATs
* AEC: Automotive Electronics Council
Engine Control
Driving Control
Comfort
Infotainment
Motor Driver, PMIC
Safety
• HSOP • HQFP
Grade 0 ~ 1
• HSOP • HQFP
• TQFP • QFN
Grade 0 ~ 1
• HSOP • HQFP
• TQFP • QFN
Grade 1 ~ 3
• HSOP • HQFP
• TQFP • QFN
• PBGA • FCBGA
• SiP / MCP
Grade 1 ~ 3
• HSOP • HQFP
• TQFP • QFN
• PBGA • FCBGA
• SiP / MCP
Grade 1 ~ 3
• HSOP • HQFP
• TQFP • QFN
Grade 0 ~ 1
33
IoT Applications & Key Technologies
Smart Home
Smart Energy
Smart Logistics
Smart Health Smart Transport Smart City
Wearable
LP MCU
HP AP
RFID/NFC
GPS
WIFI
PLC
BT/BLE
ZigBee
2G/3G/4G
Display
Charger,
PMIC,
Energy
Harvest
Sensors
: eNVM : Advanced Logic/MM : RFCMOS : CIS, MEMS : eHV : BCD
IoT
Confidential 34
IoT: Sensing + Big Data + App/Service
Sensing device Big data - Data capture
- Data storage
- Data analysis
Application
Confidential 35
Confidential 36
IoT Solutions
• MCU (8/32-bit), sensor (light/humidity/temp), & wireless products are developed for IoT
• Connected home, wearables, IIoT, & smart meters are the arenas targeted
36
Wearables
Smart Sport
Watch
“HoT”
Smart Watch Baby
Monitor
Smart Meters
MCU
IIoT
Sensing
Motor
Control
MCU
Interconnect
Wireless & RF Sensors
MCU Products
Zigbee/Thread
Wi-Fi/Ethernet
Gateway
Zigbee/Thread
Dimmable
Light Switch Zigbee/Thread
Contact/Temp
Sensor
Connected Home
Confidential 37
Key IoT Applications & 2019 Market Forecast
37
Confidential 38
Drone ‒ IC Detail
• Auto-Return-to-Home
• Support fly-path programming
• No-Fly-Zone feature
• Camera tilt & stable control
DJI Phantom II Quadcopter
Weight 1Kg
Battery 5200mAH
(25min flying time)
Main Board
MCU
NXP LPC1765 Cortex-M3
@ 100MHz, 256KeFlash,
64KB SRAM
CAN
Network
TI SN65HVD23x 3.3V CAN
transceiver
GPS
Board
Receiver Ublox GPS chipset
Processor Freescale 8-bit MCU
Wireless 2.4G Hz WiFi
(300m remote control)
Motor
Control
MCU
Silicon Labs C8051 @
25MHz, 32/64KB eFlash,
4.25KB SRAM
MOSFET AOS mosfet
Sensor
Inertial 6-axis accelerator/gyro
Environment barometer
range
Camera
module
Video FHD 1920 x 1080
Stabilizer 3-axis gimbal (gyro)
(brushless motors)
Price
USD1229
(UAV + Battery + 3-axis
gimbal + Camera)
Myriad Things for Data
Confidential 39
World Is Running on Data
1.4B+ websites
2.4B+smartphone users
3.3B+ internet users
22.5B+ internet searches per day
3.5x1018 byte data generated per day
Cloud
Infrastructure
Confidential 40
Confidential 41
Healthcare
BFSIs
Retail
Manufacturing
Automotive Utilities & Telcos
Government &
Education MEMS
AI
CPU
(HPC+HBM)
Chips on
Interposer
NAND
CNTL
HPC
(GPU/
CPU/
ASIC)
CIS MEMS
MCU /
DSP AP
RF
Cloud
Edge Computing
End Devices
AI
Semiconductor technology will enable critical
applications across end devices, edge and cloud
Audio
Codec
ASIC
HBM
Confidential 42
New era: artificial intelligence will kick start the
next IT revolution before 2025
Computing
Mobility
Internet of Things
Artificial Intelligence
1995 2005 2015 2025
AI is everywhere: a set of disruptive technologies that are revolutionizing the speed
and accuracy of problem-solving and decision-assistance
AI revolution has been driven by a manifold increase in processing power, improved
algorithms, lower-cost hardware, and the exploding creation and availability of data
1 billion
PC users
2.5 billion
mobile
users
100s billion
connected
devices
46 billion spending
2100+ startups
Data Source: IDC, Gartner, Market Research
Confidential 43
Automotive ecosystem and value chain will face dramatic change
43
Confidential 44
AI is shaking up the entire value chain while semi -
conductor plays a critical role as key accelerator
Semiconductor Algorithm Systems Service/
Application
FPGA
CPU
GPU
TPU
Memory
Sensors
Machine/deep
learning
Reasoning
Software
Platform
UI
System Integration
Finance
Manufacturing
Retail
Healthcare
Confidential 45
Outline:
45
1. History & Prospect of Semiconductor Industry
2. Semiconductor Applications
3. Semiconductor Supply Chain Eco-System
4. Introduction to UMC
5. Working Experience Sharing & Suggestions
6. Q&A
Confidential 46
System
Architecture
Knowledge
IP and Design
Methodology
SoC Process
Platform
World Class
Manufacturing Fast Yield Ramp/
Package
Solution
•90/65/45/28/14nm
• Mixed Signal
• RF
• e-Memories
• High Voltage
• CIS
•RFSOI
Expensive Advanced Process Cost
High cost on advanced chip development Unit: US$ M
Confidential 47
Confidential 48
10,000 Times
IC Design
Confidential 49
( )
( )
( )
1995 2018 2018
8" 晶圓 8" 晶圓 12" 晶圓
300
steps
700
steps
1000
steps
製程步驟
15~50
Wafer Manufacturing
Confidential 50
Assembly & Test
Processed Wafer Wafer Sort, Dicing Wire bonding
Assembly
Shipping
IC Testing
Confidential 51
聯電
Manufacturing
(Consumer to Auto)
Process Qual
(AEC-Q100)
Device Qual
(AEC-Q100)
IC晶圓製造
生產製程
&
檢測設備
Semiconductor Supply Chain
光罩
化
學
品
IC封裝測試
IP設計/
IC設計代工服務
IC
設計
IC
模組
IC
通路 導線架
基
板
生產製程
&
檢測設備
Foundry:
tsmc, UMC, Global
Foundries, SMIC ..
Design
House:
Ali,
AMD,
Broadcom,
Mediatek,
Qualcomm
,
Realtek…
IP:
ARM,
Cadence,
eMemory,
Synopsys,
…
ASIC:
Faraday,
GUC,
…
日月光,矽品,京元電.
華泰電,菱生,超豐電,
力成,同欣電
崇越科,
致茂電,
漢科,
PDMC,
Toppan
,
Hoya,
TMC
永光,
華立,
三福化,
致茂電.
蔚華科,
漢科
欣興,
景碩,
長華電材.
同欣電,
順德,
百容,
健策,
台達電,
宇瞻科,
福懋科,
創見,
聯強國際,禾伸堂.
益登,
Design Wafer Manufacturing OSAT: Packaging & Test
Advance Process
New materials (HK/MG)
New device schemes (FinFET)
& Char. methodology
New design methodology
(DPT)
Today’s Designers Face Challenges
Customer Growing design complexity &
challenging PPA target
Peak time design resource
shortage
Time-to-market pressure
IP
Portfolio completeness
Time to market readiness
ARM core & POP solution
Design Support Reference design flow
FDK
Adv. process effect ( DFM, 2nd
order effect, DPT, FinFET)
On-site FAE support and APR
service
Confidential 52
Design & Manufacturing Ecosystem
Customer’s
ONE Stop Solution
Design
Flow
Foundry
UMC
Design
Service
IP
Solution
Confidential 53
Digital Design Flow
Confidential 54
EDA Platform Reference
FDK Cadence Platform
(IC6.X & IC 5.X)
Schematic
Entry Tool
Virtuoso Schematic
Editor / Composer
Simulation
Tool
HSPICE
Spectre
Layout
Editor Virtuoso Layout Editor
Verification
Tool
DRC : Calibre
LVS : Calibre
RCX : QRC/StarRC/XRC
Process
Technology
Information
Netlisting Info &
Views
Pcells / Routing /
Connectivity /
Symbolic VIAs
Verification /
Parasitic
Extraction Rules
Cell View &
Symbols
Confidential 55
Mask (Photomask)
Confidential 56
• Blank
Pellicle is used to prevent the particles in environment from falling onto the
photomask and assure the defect free exposure process.
Cr/CrOx
photoresist
quartz
A substrate consisted of a quartz plate sputtered with a chrome thin film and
coated with a light sensitive polymer (photoresist) onto the chrome film.
• Pellicle
MoSi
Binary PSM
Materials for Photomask
Confidential 57
QZ
MoSiON
Cr/CrOx
photoresist
Resist coating
Alignment exposure
Cr border HTPSM
Cross-section of Mask -PSM flow
Confidential 58
General Mask Process Flow
Confidential 59
Confidential 60
Challenge of Adv. Mask Technology
Difficulty (Cost) increases significantly for new material, tool and new
technology by generation.
1985 1990 1995 2000 2005 2010
Design Rule 90nm 65nm 45nm 130nm 180nm
Laser Writer
D
ifficulty
of m
ask m
akin
g
28nm 14nm…
EB Writer
MoSi Cr
MoSi Cr Cr
BIM
(Binary)
KrF
HTPSM
ArF
HTPSM
ArF
MoSi-BIM
…
2018
50kV EB Writer
EUV
Mask
Isolation
(前段)
Device
(中段)
Interconnect
(後段)
Passivation
(護層)
Wafer start
Wafer out
Inte
gra
tion 前段製程
From: IEMN -High performance SOI-CMOS flexible electronics
後段製程
From: IEDM 2002, Intel
Process Flow Structure
Confidential 61
Diffusion
(擴散)
Lithography
(黃光) Etch
(蝕刻)
Thin film
(薄膜)
Module Engineering ( Process & Equipment Engineer )
Isolation
(前段)
Device
(中段)
Interconnect
(後段)
Passivation
(護層)
Wafer start
Wafer out
照像專家
印製元件圖
案
地基專家
鋪下元件材
質
熱處理,活化
雕刻專家
刻出元件圖
案
架橋專家
連接元件線
路
隔絕層
Function: Function: Function: Function:
Fab Organization — Four Modules
Confidential 62
Module Integration
STI
Well/VT implant
Gate oxide
POLY
S/D implant
ILD/ Contact/ M1
IMD1/ VIA1/ M2
Passivation
PAD
~
PHOTO- STI
ETCH- STI
DIFF- PAD Oxide
T/F- M1 Cu Sputter
PHOTO- M1
ETCH- M1
T/F- IMD1 CVD
Process Flow Layer (Route) Module (Step)
Recipe control
Equipment
Facility
Metrology/ Inspection
Recipe control
Equipment
Facility
Metrology/ Inspection
Confidential 63
Module - Diffusion
In the diffusion, two methods
deliver the dopant into Si wafer :
. Implant : Accelerate the isotope
and direct bombard the wafer
. Furnace : Use thermal diffusion
potential
Deliver the dopant into right
depth with right concentration.
Diffusion
Raw material :
Chemical Gas, Isotope gas
Equipment :
Implanter , Furnace
Confidential 64
Module - Photolithography
Optics lithography to reproduce the
specific patterns.
Today, UV Excimer laser provides
the wavelength of the light less
than one tenth of half pitch.
Technology shrink exposure
light into deeply UV zone.
I-line
(365 nm)
0.35um
DUV
(248 nm)
0.25um
DUV
(193 nm)
65 nm
DUV
(immersion)
28 nm
EUV
(13.5 nm)
<7 nm
Photo:
Raw material :
Reticle, Photo Resist
Equipment :
I-Line(MUV), DUV, EUV
(Stepper, SCANNER)
Confidential 65
Module - Etch
In general, RIE is in the term of
Dry etching, dominated by
Physical Ion bombard &
Chemical reaction
with the surface to evaporated the
byproducts.
Reactive ion bombard
Etch
Raw material :
Solvent, Reactive gas
Equipment :
Dry Etch (RIE), Wet Bench (Chemical Station)
Confidential 66
Module - Thin Film
Thin-Film: Chemical dominated
(CVD) and Physics dominated
(PVD)
CVD: Chemical reaction to deposit
a film on wafer surface
PVD: No chemical reaction.
Accelerated Ar bombard/ evaporate
the target & deposit on wafer, such
as Sputter
CVD PVD
Chemical reaction
Thin-Film:
Raw material :
Metal Target, Chemical
Equipment :
Sputter, RTP, CVD (AP, PE, LP, SP, MO), Scrubber
Confidential 67
Module – CMP (Chemical-Mechanical Polishing)
Polish films with chemical-
mechanical assistant.
Two factors dominated CMP:
First is chemical hydrolysis slurry
to hydrolyze the surface
Second is the slurry abrasive to
remove the hydrolyte which under
the mechanical dominated.
CMP
Raw material :
Slurry, polish pad
Equipment :
CMP (W, Oxide, Cu)
Confidential 68
Confidential 69
Testing Development & Services
• Work with Customers for Cost Effective Test Solution Development
• Production Yield Monitoring & Improvement by Bin Limit Control Mechanism
• Proactive Product Yield Improvement and FA as Value-added Services
69
Customized Service
Cost-Driven Testing Evaluation
Testing Hardware Design
Program Development &
Validation
Multi-DUT Migration / TTR
Yield Analysis & Diagnosis
Remote Assess Engineering
Analysis
Probing Optimization DOE
Best-in-Class FA Capability
Real-Time Data Feedback
Production Yield Monitor
Customized Yield Report
SBC* Implementation
*SBC : Statistical Bin Control
Volume Production Test Solution Development
Package Technology Evolution Technology node (nm)
1980 2020 1990 2000 2010
Leadframe
PDIP
SOJ
SOP
QFP
QFN
90 65 40 28 14 / 7
Perf
orm
an
ce
FC / WLP / PoP
PoP
WLCSP
FCBGA
FOWLP
Stacked die
2.5D / 3DIC / SiP
3D IC
FO-SiP
Logic
TSI
2.5D TSI
BGA
TFBGA
LGA
PBGA
Stacked die
Confidential 70
Confidential 71
Advanced Package Trend & Solutions
• Advanced SiP package: 2.5D / 3DIC & Low Cost Option : FOWLP
71
Cost
Package Size(Length)
FO-POP • AP + BB
• Networking
PKG = 8 ~ 25 mm
Memory
AP BB
2.5D TSI
• FPGA
• GPU + HBM
• Networking
PKG = 40 ~ 60 mm
GPU HBM
3DIC • Stacked memories
• Wide IO DRAM + Logic
PKG = 15 ~ 30 mm
AP
Wide IO Memory
SIP (System in Package)
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• Diversified Packaging Solutions for Mobile, IoT, Automotive, HPC &
Memory Applications Including:
Wire Bond, Bump, Stacked Die, WLP, 2.5D, 3DIC, FO-WLP
Diversified Packaging Solutions
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PoP
FO-PoP
Wire Bond
WLP
FO-WLP
Flip Chip
SiP / MCP
3DIC /
2.5D TSI
FCBGA HS-FCBGA
Stack Die TFBGA Stack Die QFP Stack Die QFN
3DIC 2.5D TSI
PoP FO-PoP
WLP FO-WLP Panel PoP Packaging Solutions
QFN QFP/LQFP TFBGA LGA SOP
Thank You!
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