Introduction to RF PA design

Presented by Dr. Chris PotterChris.Potter@CambridgeRF.com

Copyright © 2018 Chris Potter, Cambridge RF, U.K. All rights reserved

Power Amplifier Techniques WorkshopCambridge Wireless

22nd May 2018

Contents

◼ Generic PA transistor

◼ Achieving power amplification

◼ Application types

◼ Considerations of carrier frequency, power level

◼ Modulation waveform and how it affects PAPR

◼ Key specs

◼ Noise, distortion, efficiency

◼ Circuit and Topology choices

◼ Class A, AB, C, Balanced circuits

◼ Device Technology Overview

◼ Design methods

Generic PA Transistor

◼ A control current or voltage causes a greater current swing at the output

◼ A bias circuit holds the operating point at a desired part of the linear range

◼ Optimisation of output current-voltage relationship (load line)

◼ Minimisation and control of parasitics

Applications of PAs

Application Power Technology

TV Broadcast 100W x many in parallel

LDMOS, GaN

Cellular Base-station

10 to 50W LDMOS, GaN, GaAs FET

Cellular Handset

0.25 to 2W GaAs, Si, SiGe

WiFi 0.1W GaAs HBT, Si

Bluetooth, ZigBee, LoRa

0.001 – 0.1W Si

Device Technology Overview

◼ Differing parasitics and thermal conductivity characteristics

0.1W

1W

10W

100W

1000W

1000W

1GHz 3GHz 10GHz 30GHz

SiC MESFET

GaAs HEMT

Si MOS, LDMOS

GaN

GaAs HBT

Tubes, TWT

Modulation and PAPR

Technology Modulation PAPR

CW Sinewave 0dB

2-tone 2x sinewaves 3dB

GSM, DECT, Bluetooth 1.0

GMSK, GFSK 0dB

Bluetooth EDR, TETRA

QPSK, 8PSK 3.2dB

3GPP-UTRA WCDMA 11.2dB

3GPP-EUTRA LTE (OFDM) 11.5dB

802.11n OFDM 11.5dB

DVB-T OFDM 11.5dB

PA Specs: Efficiency

◼ PAs are most efficient when operating near maximum output power

◼ Drain Efficiency is the ratio of RF output power over DC input power

◼ Power-Added Efficiency subtracts RF input power from DE calculation

◼ For signals with high crest factor, the PA is backed-off and operates at lower efficiency most of the time

%100,

%100,

−

=−

=

inDC

inRFoutRF

inDC

outRF

P

PPPAEEfficiencyAddedPower

P

PDEEfficiencyDrain

PA Specs: Distortion

◼ Two input tones presented to a device with non-linearity will create many other frequency products

f1 f2

f1+f2

f2-f1

2f1+f2

2f1 2f2 3f1 3f2

2f1-f2 2f2-f1

2f2+f1

Third-order distortion products

Intermodulation distortion (IM3)

Third-order distortion products

Second-order distortion products

Frequency

Am

plitu

de

( ) ( )

( )( ) ( )( ) ......2cos2cos......

coscos

12

2

21

2

3210

21

++−+−+++=

+=

tABtBAaaaav

tBtAv

out

in

Input tones at f1, f2

Third-order terms

PA Specs: Noise

=

output

output

input

input

N

S

N

S

FfactorNoise ,

Thermal noise, P = kTB

Equates to -174 dBm/Hz at room temperature

G1 G2 G3

...11

21

3

1

21 +

−+

−+=

GG

F

G

FFF

Cascaded noise figure (Friis’ equation)

=

output

output

input

input

N

S

N

S

dBNFfigureNoise log10)(,

Circuit Topology - PA Classes

◼ Class A◼ Linear, simplest circuit,

◼ Transistor is conducting all the time

◼ 25 or 50% efficiency limit depending on circuit

◼ Class AB◼ Transistor is conducting most of the time

◼ Common compromise between efficiency and linearity

◼ Class B◼ Transistor is conducting half of the time

◼ 78.5% theoretical efficiency limit

◼ Class C◼ Transistor is conducting less than half of the time

◼ Non-linear amplification, high efficiency

Class A

◼ Transistor output swings from near-supply to near-zero

◼ Half-power dissipated in transistor, half in load

◼ Not all of the power in the load is useful signal though

◼ Example circuit:

◼ PR1=132.46mW (AC+DC)

◼ PR1=27.646mW (AC)

◼ PV2=228.92mW (AC+DC)

◼ 12% efficiency

Class B

◼ Transistor output swings from near-supply to near-zero

◼ Reduced input DC to cause transistor to spend 50% time off

◼ No dissipation while it is off

◼ Increased input swing

◼ Example Circuit:

◼ PR1=103.87mW (AC+DC)

◼ PR1=60.086mW (AC)

◼ PV2=147.97mW (AC+DC)

◼ 40.6% efficiency

50% 50%

Class C

◼ LC added to load, Transistor output swings from above-supply to near-zero

◼ Low input DC bias to cause transistor to spend >50% time off

◼ Increased input swing (less gain)

◼ Example Circuit:

◼ PR1=161.56mW (AC)

◼ PV2=227.28mW (AC+DC)

◼ 71.1% efficiency

Class AB◼ Linear amplification

with better than Class A efficiency

◼ Use two Class B stages

◼ Operate them in antiphase

◼ Combine outputs

◼ Adjust bias to minimise crossover distortion

◼ Example Circuit:

◼ PR1=206.31mW (AC)

◼ PV2=303.08mW (AC+DC)

◼ 68.1% efficiency

Balanced Power Amplifier

◼ 90° Hybrids, parallel PA stages

[SA]

[SB]

a1

b1

a2

b2

a1A

b1Aa2A

b2A

a1B

b1B a2B

b2B

3dB 90° 3dB 90°

PA Design Challenges

◼ Delivering RF power into 50 ohms requires a voltage swing 50x the load current (Amps) (from V = IR)

◼ Typical PA devices handle 5V to 28V supply, (GaN may be 55V)

◼ The load current for a typical PA device may be several Amps, with peaks of 10s of Amps

◼ “Matching” is required to transform the low output impedance up to 50 ohms

◼ Expect output device has parasitic series inductance and shunt capacitance

Devices and Package Parasitics

◼ The diagram shows an internally matched LDMOS device. Drain voltage is provided via a ¼ wave feed line. RF and Modulation frequencies are terminated by bulk decoupling capacitors at the supply side of the ¼ wave feed.

1/4 λ

VDD

LDMOS Package

Examples (Reference Designs)

Design Approaches

◼ Small Signal approach

◼ Load line

◼ Conjugate match

◼ Nonlinear approach

◼ Harmonic Balance modelling and simulation

◼ Non-linear characterisation and simulation

◼ Load pull

Load Pull System

Source Tuner Load Tuner

Signal Generator

Preamplifier

Coupler

Power meter

Sensor

Isolator

Coupler

Sensor

Spectrum Analyzer

Vector Signal

Analyzer

Input

Transformer

Output

TransformerDUT

Attenuator

Dual PSU

GPIBGPIB

Load Pull System

Load Plane Contours

Load match contours of ACLR,

gain and drain current for a 20

Watt 3GPP W-CDMA Device

1.40.5

0.1

0.2

0.3 0.4

0.1

0.2

0.3

0.4

0.5

0.6

0.7 0

.8 0.9 1.0

1. 2

1.4

1.6

1.8

3.0

2.0

4.0

5.0

10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0 1.2

1.4

1.6

1.8

2.0

3.0

4.0

5.0

10

20

20

50

50

0.6

0.7

0.8

0.9

1.0

1.2

1.6

1.8 2.0

3.0 4.0

5.0

502010

Z0=3

BestEfficiency

MaximumGain

BestACLR

Conclusions

◼ Generic PA transistor

◼ Achieving power amplification

◼ Application types

◼ Considerations of carrier frequency, power level

◼ Modulation waveform and how it affects PAPR

◼ Key specs

◼ Noise, distortion, efficiency

◼ Circuit and Topology choices

◼ Class A, AB, C, Balanced circuits

◼ Device Technology Overview

◼ Design methods