introduction to microprocessors - programming books€¦ · course was given to provide an...

Introduction to Microprocessors Edited by D Aspinall and E L Dagless University College of Swansea

Pitman Publishing · London Academic Press · New York

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First published in Great Britain by Pitman Publishing Limited 1977 Published simultaneously in the USA and Canada by Academic Press Inc 1977

©D Aspinall, LAM Bennett, E L Dagless, R D Dowsing, J S D Mason 1977

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording and/or otherwise without the prior written permission of the publishers. This book may not be lent, resold, hired out or otherwise disposed of by way of trade in any form of binding or cover other than that in which it is published, without the prior consent of the publishers. This book is sold subject to the Standard Conditions of Sale of Net Books and may not be sold in the UK below the net price.

UK ISBN 0 273 01060 3 US ISBN 0 12 064550 5 LCCCN 77-72278

Reproduced and printed by photolithography in Great Britain at Biddies of Guildford

Preface

In recent years there has developed a wide interest among the designers

of information processing equipment in the use of the microprocessor.

There is a need for the logic designer, familiar with logic diagram

and wiring list, to acquire the confidence to implement design solutions

in terms of program code and data structure.

In January 1975 at the University College of Swansea, a short workshop

course was given to provide an introduction to the microprocessor for

practising engineers. The course comprised lectures and practical

programming classes, during which the students were able to implement

worked examples and examples of their own design on an actual micro-

processor system. The workshop course has been repeated several times,

and many engineers have used it to gain their first experience of a

microprocessor system. This book is based upon the workshop course

manual.

In Chapter 1, the engineer is led from the familiar logic circuits

through large scale integration (LSI) digital circuits to the micro-

processor. He is next given an initial description of a basic micro-

processor structure, which should be sufficient for him to follow the

worked examples and find his way round the console of the microprocessor

system. For his first practical encounter with a microcomputer, it is

better for the student to use one with a restricted instruction set

containing a few basic operations.

In Chapter 3, a series of case studies provide an indication of the

possible range of applications for the microprocessor and suggest

examples for practical work.

Chapter 4 discusses the addressing modes that are provided in the

instruction set of the microprocessor used in the practical exercises.

An attempt to suggest ways in which comparisons could be made among

microprocessors is given in Chapters 5 and 6. The software necessary

to support the development of microprocessor implementations is described

in Chapter 7 and the reader is introduced to (or reminded of) the need

for a structured design approach in Chapter 8.

In editing the workshop course notes into a book for use by readers

who are remote from the laboratory, it has been necessary to add material

describing the features of development systems and detailed worked

examples. A glossary is provided as substitute for a tutorial session.

Where general principles are illustrated with examples from commercial

microprocessors, the text is printed in italics. These portions are

intended to give the reader insight into practical solutions provided

by manufacturers. They also help to highlight the particular

characteristics of the microprocessors concerned, and enable him to make

his own mental comparisons of features that are available which suit his

own requirements.

The workshop that we have conducted and this book have both been

team efforts involving not only those listed on the title page, but

also the research assistants and postgraduate students who willingly

and cheerfully made their contributions as demonstrators in the practical

classes: J. Proudfoot, B. Davies, M. Edwards, D. Riches, J. Lewis,

M. Barton, D. Harvey.

We are all grateful for the support of the technical staff of the

Department of Electrical and Electronic Engineering, University College

of Swansea, and for the cooperation of Mr R. Edwards and his staff in

the reprographic section for the careful preparation of the drawings.

Finally, the workshop would not have succeeded without the patience and

ability of Mrs E. Phillips in keeping track of a stream of handwritten

notes from many hands and in processing these into coherent typescript.

D. ASPINALL

E.L. DAGLESS

SWANSEA

October 1976

1 Components for Information Processing

INTRODUCTION

Fifteen years ago, the manufacturers of digital information processing

systems, such as computers, based their circuits upon diodes, transistors,

resistors, and capacitors obtained from the component manufacturers.

These components were assembled onto printed circuit boards as logic

modules. The modules would then be interconnected by wires.

A family, comprising a limited number of different logic modules, would

be established by the system manufacturer, each member of the family

being an individual production item which could be produced in bulk.

As a typical large digital computer was based upon a family of twenty

to a hundred logic modules, copies of each module would occur ten to

several hundred times in each computer manufactured.

All system manufacturers produced their own individual family of

modules, which reflected both the style of their circuit and logic

designers, and also their production techniques. Though all families

had many similar features, in detail they were all different.

During the last ten years, the component manufacturers have been

developing semiconductor technology which assembles the basic diodes,

transistors, resistors, and capacitors in a surface layer, some ten

microns thick, on top of a thin wafer of silicon, and these are connected

by means of a layer of metal evaporated onto the silicon, which is

subsequently etched to produce the required interconnecting pattern.

The wafer is packaged as a logic module, suitable for interconnection

to other modules by conventional printed circuit techniques. These

integrated circuit modules are less costly, more reliable, smaller, and

lighter than discrete component modules.

The low cost is achieved by high volume production. Whereas a system

manufacturer could contemplate production quantities of the order of

one to ten thousand copies of a discrete logic module per annum, the

semiconductor manufacturer must think in terms of ten thousand to one

million copies of an integrated circuit module per annum, to be

competitive.

1

2

Components for Information Processing

A small number of module families which satisfy the needs of most

system manufacturers has been developed and are produced in large volume.

These include transistor/transistor logic and emitter-coupled logic,

based upon the bipolar junction transistor technology and also the

complementary MOS based upon unipolar field-effect transistor technology.

The detailed specification of each module in a family has been arrived

at as the result of an iterative process of consultation between the

system and component manufacturers to produce a logic module family which

satisfies wide system needs and can thus justify large production runs.

The modules comprise simple logic gates and bistable memory elements

which the system designer uses as basic components. They are at a

sufficiently basic level to give the designer the freedom to produce a

unique system which meets its specification in a way which reflects his

skill and style. They have few features which are redundant for many

applications; thus the designer is able to produce a trim system in which

each gate and bistable element serves a useful purpose. He has learnt

to live with these families, and accepts that his rivals are also using

identical basic components.

His skill as a logic designer has become more important than his skill

as an electronic circuit designer. Whilst it is necessary to analyse and

evaluate the circuits offered by the manufacturers and to understand the

interconnection design rules, the creative talents show in the ability

to design and create elegant economic logic circuits to meet a specification

which is attractive to the market.

Integrated circuit technology now makes it possible to pack over one

thousand logic elements onto a small silicon wafer. Large-scale integration

(LSI) permits a system in a package between finger and thumb. Such systems

can compete with those based upon the logic module families, provided the

production quantities are sufficient. The design, production, tooling,

and establishment of test facilities and documentation for production

and marketing of an LSI circuit are very expensive. These costs can be

recovered if, for a particular circuit, it serves a large-volume market

such as the pocket calculator, or watch. Attempts have been made to

reduce the initial costs. By adopting a well-proven technology such as

four-phase metal oxide semiconductors (MOS), and using computer-aided

design techniques, special circuits have been produced which match a

specialized market. Also, semiconductor manufacturers have arranged

their production facilities to provide a regular array of components


in the top layer of the silicon wafer, and these may be interconnected

in many different ways by unique patterns of metal layer connections.

The silicon wafers are mass-produced, whilst the metal layers are applied

in small production batches. This procedure offers the system designer

an opportunity to obtain circuits which meet his unique requirements

and, for the quantities he requires, are less costly than specially

designed LSI circuits.

LSI FOR DIGITAL SYSTEMS

The next step that the semiconductor manufacturers are taking is to

analyse many different information processing systems and partition

their logic circuits into self-contained units which can be identified

as universal system components. These larger components may then be

offered to all system designers, and be used to augment and replace the

existing families of logic modules. The most common large component

in such a system is the digital computer; therefore this is the obvious

starting point.

To appreciate some of the problems facing the manufacturer, let us

analyse a computer structure and attempt to partition it into its

component parts. The block diagram of a digital computer, which shows

its four main units, appears in Fig. 1.1. Information is fed into the

MEMORY

1 INPUT DEVICES

^^^^ ™ V ^

PROCESSOR

OUTPUT DEVICES

Fig.1.1 A typical computer

computer by means of peripheral input devices, and is obtained from

the computer through the output devices. Both sets of devices are

controlled by processes in the computer. The information held in the

memory comprises both the data being processed and the instructions

of the programs which define the actual operations to be carried out


in the processor.

There are several situations that call for the provision of input-

output devices and their contrpl, and that suggest a role for LSI

components. Since their specification is affected largely by the nature

of the devices rather than by memory or processor, we will not consider

them in any more detail. Instead, let us consider only the memory and

processor units and their interrelationship. By excluding the input-

output devices, we are left with the block diagram shown in Fig. 1.2.

MEMORY

I READ

PROCESSOR

WRITE SELECT

Fig. 1.2 Processor-memory relationship

Within the memory unit, information is held as binary digits,or bits,

in registers comprising several bistable storage elements. The length

of each register is determined by the specification of the overall

computer system. Typical values are eight, sixteen, and twenty-four

bits. The number of registers is also determined by the requirements

of the system, depending upon the amount of data to be stored and the

length of the programs. Sizes range from 4K to 256K (K = 1024).

Circuitry is provided to give communication between any one of the

registers and the processor, and for reading the information held in

the register or writing new information into it. To select a register,

the processor must present an address word to the memory which is

decoded by selection circuitry to open the communication channel. The

length of the address word depends upon the number of registers in the

memory. An address length of n-bits selects one of 2n registers. (12

bits selects from 4K, 18 bits selects from 256K). To achieve high

computer performance, the delay between presenting an address to the

memory and reading a register, the access time, should be very short,

in the region of one hundred nanoseconds to one microsecond.

5


A large memory may be constructed from sub-units of LSI random access

read write memory (RWM) modules of say IK registers of 1 bit. A memory

of 4K registers of 8 bits uses 32 such modules. The system specification

of a RWM module is simple, since it comprises only the number and length

of the registers and the access time. A joy to behold by the semiconductor

manufacturer! A universal system module with an assured market! Also,

other forms of memory are required universally. These include the read

only memory (ROM) for holding fixed information which does not change,

a programmable version of the read only memory (PROM) which enables the

system designer to change the fixed information for different versions

of the system.

The specification of the processor is a different matter. Every computer

designer has his own view of the ideal processor specification, and it is

unlikely that one module would embrace all in an efficient way. The

factors which influence the main items in a specification, such as word

length, range of processing functions, and modes of addressing information

in the memory,are many and varied. They depend upon the type of use for

which the computer is intended, ranging over scientific calculation,

business data processing, and real time control. The software, placed

between the processor and the end user to provide high-level languages

and afford automatic management of the input-output devices and flow of

work through the system, also affects the detailed specification of the

processor.

However, there are some general features which are common to all

processors. The processor must carry out arithmetic and logical

operations on the data held in the memory. Before it can do this, it

must find the instruction in the memory to discover the next function;

also, it must find the data operand in the memory and fetch it to the

processor so that the function may be performed.

Instructions are stored as patterns of binary digits in the registers

of the memory. In many cases, the consecutive instructions of the

program are held in consecutive registers of the memory; thus the

address of the next instruction is implicitly the address of the present

instruction, plus one. A program counter register in the processor holds

the address of the present instruction, its contents being incremented

by one as the next instruction is fetched.

Certain instructions may explicitly specify the address of the next

instruction, which may be at any address location in the memory, causing

a jump to another section of the program.


The circuit block diagram of this small processor is shown in Fig. 1.3.

READ

| BUFFER | I BUFFER |

Γ" "~1

CONTROL CIRCUIT

-L.

SELECT

Fig.1.3 Data paths of a typical small processor

Communication between the processor and the memory is by way of three

ports labelled SELECT, READ, and WRITE. The select port passes

information from the processor to the memory, coded as the address of

the selected register in the memory, to request either a Read or Write

channel between the selected register and the processor. Data passes

through the write port to the selected register, or information passes

from the selected register to the read port of the processor. Within

the processor there are two distinct regions: the data paths, and the

control circuit. The data paths comprise the function unit, accumulator

register, program counter register, and buffer registers, together with

the gating and routing circuitry between them. The control circuit

ensures the correct sequence of flow through the data paths.

The function unit carries out operations of the form Z <- X b Y. The

operator b is selected by the control circuit. Typical operators are

7


ADD, SUBTRACT, SHIFT, LOGICAL and NON-EQUIVALENCE. The operands X Y

and the result Z are all words composed of many bits in parallel, and

the operation is performed on all bits of each operand in parallel to

produce a result on all bits of Z in parallel. The operand X is

selected to be either the information read from memory or that buffered

on the output of the function unit at the write to memory port. The

operand Y is selected from either the accumulator register or the

program counter register. The result may be routed to either register

or to the output buffers, and it is also sent to the control circuit.

All of these routes are many bits in parallel and, together with the

registers, gates, and functional unit, represent the majority of logic

modules within the processor.

There are two ways to divide the data paths into circuit modules which

may be suitable for LSI. By drawing lines across the diagram, it is

possible to identify four types of module. The function unit, the gating

system producing operand X, the output buffer registers, and the small

memory unit of two registers, and the gating system for operand Y. At

the boundary of each partition there must be leads to interconnect the

modules together. In the case of the function unit, there must be leads

to route in X and Y and route out the result Z. The number of leads

required for each of X, Y and Z is equal to the number of bits processed

in parallel by the function unit. In a typical system, this number may be

sixteen—thus forty-eight leads are required for X Y and Z. In addition,

there must be leads to permit the input of the control signals. These

are coded in a similar way to addresses, and four bits permit selection

of one of sixteen operators. A typical function unit permitting sixteen

operations on two operands of sixteen bits could require at least fifty-

two interconnection leads. These leads are routed from the surface of

the silicon wafer to pins in the package which carry the wafer, and

provide mechanical and environmental protection. Package technology

has kept pace with semiconductor technology, but is only able to provide

economic packages with approximately twenty pins. Packages with forty

pins are rare and expensive.

The other modules produced by horizontal partitioning of a 16-bit

processor require in the region of thirty to fifty pins, and are not an

economic proposition.

The diagram may be sliced in a vertical direction into data path

modules, similar to those shown in Fig. 1.3, but only two bits wide.

8


Such modules would require only twenty pins. Eight such modules could

enable the construction of a processor for word lengths of sixteen bits.

Thus, one important item in the specification of a computer, the word

length, is catered for by connecting a sufficient number of the modules

in parallel.

DATA PATH MODULES

Let us consider how the other basic requirements of a computer are

satisfied by an assemblage of such data path modules. The first require-

ment is an ability to control the flow of the program which is based on

designating an internal register as a program counter. This register

will hold the address of the present instruction. Usually, the next

instruction is fetched by passing the contents of the program counter

through the function unit which is controlled to carry out Z «- Y + 1.

The output of Z is then copied to both the program counter and to the

select buffer. The memory is accessed, and the next instruction appears

at the READ port of the processor; it is gated to the function unit

which is controlled to carry out Z «- X. The appropriate part of the

instruction, which describes the address of the operand, is then copied

from Z into the select buffer and the function digits are transferred

into the control circuit, where they are decoded to control the function

unit to perform Z «- X b Y at the appropriate time. Before this time,

the memory must be accessed to produce the operand at the READ port of

the processor, whence it is gated to the X input of the functional

unit; also the contents of the accumulator register must be gated to

the Y input of the functional unit. When this operation (Z <- S b A)

has been completed, Z must then be copied back to the accumulator

register to complete A «- S b A. This cycle must be repeated by

fetching the next instruction. This complete cycle contains the

following basic sequence of activities:

(1) Fetch next instruction

(2) Decode instruction

(3) Fetch operand

(4) Execute instruction

Within each activity there is a distinct sequence of events, each of

which involves the opening of gates, the control of the function unit,

and the setting of bistable elements in registers or buffers.

9


Each event requires a unique combination of control signals from the

control circuit. At any particular time the pattern of signals emanating

from the control circuit can be said to describe its state. Thus, the

control circuit may be conceived as a machine which can change its state

as it moves from event to event within the total cycle. The sequence

of states is determined by the required sequence of events within each

activity of the cycle. Certain sequences will always be the same.

There must always be a sequence to fetch the next instruction, but the

decoding of the instruction may result in different sequences. In

addition to the sequence described above to execute A «- S b A, there

are different sequences to execute S -*- A and jump of program control

resulting from different instructions.

The computer which we have considered so far has very limited operand

addressing capabilities and a very restricted set of operators. In other

computers, the specification may require the option of processing the

address field of the instruction to compute the operand address leading

to many alternative states of the control circuit within the fetch

operand sequence.

Arithmetic operators, such as multiply or divide, involve many passes

through the simple function unit which, in turn, involve many different

sequences of states within the execute instruction activity.

The data path module provides the necessary components for controlling

the flow of instructions and obeying them, provided a control circuit

can be designed to control the repeated use of these components, in

different combinations, within the cycle of activities involved in each

step of the program. Such a module would seem to satisfy the requirements

of a wide range of computer functional specifications. However, it can

only be used in different systems if each system has its own unique

control circuit described by a unique sequence of states. The semi-

conductor manufacturer may have found a module which meets half of the

requirements, but the complexity and variety of the control circuit

still presents a problem.

LSI COMPONENTS FOR CONTROL LOGIC

The control logic is generally described by a flowchart and corresponds

conceptually to a bit serial system. The complex and varied route taken

by the pre-pulse or token as it moves through the flowchart, to indicate

the current region of activity in the total process, is the representation


of both the specialized nature of the equipment specification and the

personal design approach and ideas of the logic designer.

The control logic is characterized by its uniqueness and also by its

complexity. Certain components are often used, such as counter,

decoders, and delay elements, but these are generally quite small in

size and are classed as MSI (not LSI).

The role which a general-purpose LSI unit could play in the area of

control logic design would be to provide a unit onto which the designer

could map his complex control logic. Such devices are beginning to

appear. The first is the uncommitted logic array (ULA) which provides

on the chip an array of standard gates which can be interconnected by

a programmable mask technique to suit the particular requirements of

the logic designer. The familiar circuit diagrams of the logic designer

can be mapped onto the programmable mask. However, there is a limit to

the complexity that can be handled by this approach. An alternative

which has long-term implications is the use of memory arrays and table

look-up techniques for the implementation of control logic.

To illustrate this approach, consider the illustrated example of a

typical design problem. The problem is specified by the truth table

in Fig. 1.4.

Row

o 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15

Inputs

x0 x l x2 x3

o o o o 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 O l l i 1 0 0 0 1 0 0 1 1 0 1 0 l o i i 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

Outputs 1

z0 z l z2 1

—· O

O O

O O

O —

' O O

—i—

■—·—

■ O

O

—■ O

O O

O O

O O

O O

—»

—■ O

O O

O

1 .—

—

Fig.1.4 Truth table

To implement these expressions in terms of NAND gates, we obtain the

circuit as shown in Fig. 1.5.

Components for Information Processing 11

-H>o-

*i -H>o-

x2 -r-Dx>—1

0-30-FÎ)-!

D-P>"

" T^t^V-l-t^., Fig.1.5 Gate implementation

To the uninitiated, the circuit drawing bears little or no relationship

to the design problem as stated in the truth table. When this circuit

is implemented, either by hand-wiring of logic modules or on a printed

circuit board, or ULA, the result will appear to be even more complicated

and more difficult to check out.

Is it possible to implement a logic functional unit which has less

complication at the later design and construction stages of the process?

One obvious method is to map the truth table onto a conventional RWM or

ROM. The memory would need to be of 2n words of m bits where:

In our example

n - number of input variables m = number of output variables

n = 4 m = 3

Thus: 16 words of 3 bits

In practice, the input variables would be arranged to act as the

address for the memory and the word read from the line of memory by

this address would act as the output, each bit of the output word

corresponding to an output variable (Fig.1.6). Thus, we see a direct

correspondence between a familiar tool of the logic designer, a truth

table, and an actual circuit implementation, a read only memory. We

have removed all the placement and wiring problems implicit in the


■•\y 7 \ :r \ n)

ROM

1 1 1 zo zi z

t 2n 1 1

? ( m )

Fig.1.6 ROM implementation

implementation of the earlier logic circuit, and can see this approach

as a possible way to implement combinatorial logic.

There is however, one obvious economic disadvantage. The height of the

ROM = 2n where n = number of bits in the address = the number of input

variables. Thus, for say 10 input variables, the ROM must have 1024

words of length depending upon the required number of output variables.

An eight-input adder, producing an eight-digit sum plus carry overflow,

would involve 64 K words of nine digits. Is there a method of reducing

the number of words in the ROM?

If we return to the original truth table, we find that certain output

rows contain all zeros, (0, 1, 6, 7, 9, 10, 11, 12, 13, 14). Fewer rows

contain at least one 'Γ (2, 3, 4, 5, 8, 15). If we could find a way to

store these six rows in a ROM and access these by an associative or

content addressable memory (CAM), then we could reduce the size of the

memory to six words instead of 16 (Fig. 1.7).

CAM

x0 x1 X2 x3 ( n )

* —»

ROM

\ ZO z1 Z2

( m )

<2n

Fig.1.7 FM (functional memory)


Thus, if we replace the conventional decoder of a ROM by an associative

store and write into the associative store a bit pattern describing only

those input patterns which produce an output, then we obtain a significant

reduction in the number of words stored (Fig. 1.8).

0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1

1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1

FUNCTIONAL MEMORY

INPUT TO SEARCH FOR MATCH

OUTPUT SELECTED BY MATCH

Fig.1.8 FM implementation

If such a combination of CAM and ROM were constructed on a single

silicon chip and offered as an LSI module, it would present the designer

of logic functional units with a component which enables the removal of

much of the drudgery inherent in the final stages of the current design

process. This component may be termed a functional memory.

The functional memory can also be applied in sequential logic. To

illustrate this, let us consider the design of a simple counting sequence,

as shown in Fig. 1.9.

o o o o — - — o o o 1 0 0 0 1 — — 0 0 1 0 0 0 1 0 — h 0 1 1 0 0 1 1 —■« 0 1 0 1 0 1 0 1 — ■ - 0 1 1 1 0 1 1 1 — » 1 0 1 1 1 0 1 1 — 1 1 0 1 1 1 0 1 — » 0 0 0 0

T T 1 T

I I I I

T T f f

OUTPUT SEQUENCE 0.1. 2. 3. 5.7. 11.13.0..

Fig.1.9 FM counter


The provision of flip-flops in the feedback path makes possible such

sequences. Since a flip-flop may be described by a series of Boolean

expressions, these may also be implemented on the CAM-ROM fields of the

functional memory, as required.

Programmable Logic Arrays

This approach can be taken a stage further. If we return to the original

example and examine the minimized truth table and Boolean equations, we

find that by exploiting a third state, the 'don't care' state φ, it is

possible to reduce the size of the functional memory from six words to

four (Fig. 1.10).

(&) 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1

INPUT XQ X, X2 X3

(OR)

1 0 0 1 0 1 1 0 0

, Z0 21 22

OUTPUT SUM OF PRODUCTS

Fig.1.10 PLA (programmable logic array)

Development of microprogramming

It is essential at this point to reconsider the conventional ROM as a

generator of control sequences. If we return to our example, we could

use a ROM of two words, i.e. 16 words instead of 8, and only populate

half of them (lines 0, 1, 2, 3, 5, 7, 11, W) with a bit pattern of

four-bits for the next number in the counting sequence. The physical

size would be 16 χ 8 = 128 bits (64 bits for CAM-ROM functional memory).

Alternatively, one could use the arrangement shown in Fig. 1.11.

Components for* Information Processing 15

0 0 0 0 0 0 0 1 0 0 1 0 ( 0 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 (

im

D 0 1 3 1 0 ) 1 1

0 0 0 1 1 0 1 1

) 0 0

~Γ υυ ι r u ι 1 1—1 1

Ί π ΓΤ

Fig.1.11 ROM sequencer

The address of the next number is held alongside the present number

in the counting sequence. The size of this ROM is 7 χ 8 = 56 bits. The

obvious final step is to dispense with the 3-bit binary counter field

within the ROM and replace the D-type flip-flop by a 3-bit counter. At

the expense of extra logic external to the memory, we have reduced the

ROM size to 32 bits.

We have seen how one can generate a repetitive control sequence by a

completely table-driven approach, and also by a combination of table

plus external logic. The next stage of the problem is to consider ways

of controlling the number of times the complete counting sequence or

control loop is executed, and also ways of initiating the next counting

sequence or stage of control that is required. Both these decisions may

be conditional upon the value of data in the data path generated as a

result of the data path operations initiated by the current sequence, or

by some external event. To solve these problems we need a system as

shown in Fig. 1.12.

With this system, it is possible to map control patterns of up to

m bits into the memory and permit the next pattern to be either the

content of the next word in memory (Address + 1) or. the content of

the word specified by the next start address, either unconditionally

or conditional upon one of the external conditions K.

The design process consists of determining the control patterns,

placing them in the memory, and organizing the linkage between patterns

by writing a pattern into the JUMP ADDRESS, JUMP UNCONDITIONAL and

JUMP CONDITION fields of the memory.


OUTPUT

Fig.1.12 Basic microprocessor

The choice of m , n and I is determined by the problem. This system,

which has been described briefly, is of course the microprocessor

suggested by Wilkes in 1950, for which one could write microprograms

to provide the control sequences necessary for the control of the data

paths of a computer.

A generalized microprogram control system is shown in Fig. 1.13. Each

line in the memory contains four fields: the control pattern to define

the control signals to produce the required operation of the data paths;

the address of the next microprogram instruction in the sequence: the

address of the instruction to be jumped to, out of sequence; the pattern

of conditions which must be combined with condition data from the data

paths to determine the type of next address. External to the memory are

the connections from and to the data paths, which provide the conditions

and start address if required. The decoder selects the address of the

next instruction which is clocked into the address buffer to begin the

next stage in the control sequence.

Components for Information Processing 17

CONTROL SIGNALS TO

DATA PATHS

t ROM / \

;-l— 1 ADDRESS

BUFFER

t '

CLC

CONTROL PATTERN

NEXT ADDRESS

OF SEQUENCE

M = £ _

JUMP ADDRESS

IN PROGRAM

—JfcL v )CK \ ' 1 E

^ " ^ ^ ^

CONDITIONS FOR

NEXT ADDRESS

—I— DECODER

J

~l

_l

CONDITIONS p ^ FROM

DATA PATHS

START ADDRESS

DATA PATHS

Fig.1.13 Simplified microprogram control unit

This external circuitry may be placed on an LSI chip to provide a

general-purpose microprogram control module. This is then used in

conjunction with a memory module which can be either ROM or PROM or

RWM, to provide the control circuit for the processor.

Microcomputer

In addition to these separate units, the manufacturers have also offered

processors as modules, including both the data paths and control circuit.

External logic circuitry to provide the basic clock signals and

interconnections to memory and peripheral equipment are required, but

it is possible to obtain the basic features of a microcomputer within

approximately twenty separate modules.

In using such a microcomputer, the logic designer may establish complex

data paths as data structures within the memory, and map his control

logic flow diagrams into programs of machine instructions. The techniques

of logic design become those of program construction, by using either

the machine code or assembly language of the microcomputer or a suitable

high-level language.

The microcomputer is used in situations where the processing power or

speed of computation is not critical but where a complex information


processing task is beyond the scope of more conventional logic circuit

techniques.

2 Hardware Structures

INTRODUCTION

To understand the operation and programming of a microcomputer, the

structure of the circuitry on the chip must be understood. The

limitations of the technology of the fabrication processes and the

overall objectives all affect the design decisions. The basic design

methodology is presented here to show how the hardware structure of

particular microcomputers develops and how this affects the programming

and the interface electronics.

Examples from the 8008 and the 6800 are used to illustrate specific

points. Emphasis is placed on the 8008, the machine used extensively

in the workshops, because it is a simple machine to understand, and it

exhibits the main characteristics that must be appreciated at this

stage.

INSTRUCTION SET

A microprocessor is an assembly of one or more LSI chips which form a

basic central processing unit (CPU), capable of obeying code to operate

on data in a memory and control transfers from peripherals.

The processor requires external circuitry to interface it to its

memory and input-output (I/O) facilities. The steps taken to specify

the structure of a processor and the effects on the external system are

now described.

The decisions taken will affect the instruction set, the hardware

configuration external to the computer, and the basic timing that the

machine will achieve. All are affected by considerations of package size

and the fabrication technology.

The processors described are commercial 8-bit devices, the details of

which are used to identify guidelines for presenting the general features

of a microprocessor system.

Basic Operation

A computer consists of a processor, memory, and input-output (Fig. 2.1).

19


PROGRAM AND OPERAND MEMORY

I CENTRAL 1

PROCESSOR |

Machine cycl e : 1 Fetch Instruction 1 2 Decode Instruction 1 3 Fetch Operand | 4 Execute Instruction 1

•^ - INPUT

OUTPUT

ΤΝςΤΒΙΙΓΤΤΠΝ ΓΠΒΜΔΤ 1

OPERATOR OPERAND

Fig.2.1 A basic computer structure

The processor obeys instructions from the program memory which operates

upon data in the operand memory. The basic machine cycle is: Fetch

Instruction-Decode Instruction-Fetch Operand-Execute Instruction. The

instruction must contain two types of information: the operator field,

which defines the operation to be performed, and the operand or operand

address field, which identifies the data.

Choice of Word Length

Data D The smallest word desirable is 4 bits, enough to perform

binary coded decimal (BCD) operations. To be able to handle alphanumeric

characters, more bits are needed; the industry standard is 8 bits, or

1 byte. The word length defines the fundamental length of instructions,

data, and addresses (Fig. 2.2), although multiples of the word may be

used when required.

No. of bits

4

4 BCD

8

16

1 32

NUMERICAL DATA

Range 2's complement

-8 to +7

0 +9

-128 +127

-32768 +32767

i*-10l0 +1010

No.words for 1 million

6

7

3

2 1

MEMORY ADDRESS |

Memory size

16

-256

65536

* 2 1010

No.words for 65k memory

4

-2

1 1/2

Fig.2.2 Word length features


Memory Size D Only 256 words of memory can be accessed by the

fundamental word length. This is too small. Two words will provide

addressing up to 64K words of memory, but requires more program memory

to store addresses.

[ 0 0

0 1

1 0

1 1

14 bit address

..

.. II II

Instruction Fetch

Data Fetch

Input-Output

Data Write 1

Fig.2.3 Address format of 8008

8008 : Only 14 bits of address are used to access 16K words of

memory; the other 2 bits indicate the address type. In

addressing the memory, the processor differentiates between

program and data by using four available states in the

address word (Fig. 2.3).

6800 : All 16 bits of address are used, but no distinction is

made between address types.

Operand Addressing

Having selected an 8-bit word, the instruction set required must be

coded into one or multiples of one word. With one word, a maximally

coded set contains 256 different instructions. Additional words may

be used for addresses. First, the component parts of the instructions

are described, followed by a complete description of each order.

The ability to address operands situated in the central processor,

the memory, and the input and output space is a fundamental feature

of any central processor of a computer.

There are four operand addressing modes available to the programmer

(see Chapter 4 for full range of addressing modes):

Immediate D The operand is situated in the next word of the

instruction.

Direct D The address of the register or memory location which

contains the operand is in the instruction.


Indirect D The address of the memory location which contains the

operand is situated in a particular register.

Indexed D The address of the location which contains the operand

is generated by adding the immediate word to the contents of a special

register (the index register).

|s and D Code

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Register Features |

A Accumulator

w Q f General purpose 1 E J H "L General purpose or L / address of memory operand M Memory operand (H L implied)]

Fig.2.4(a) 8008 Addressing codes

The 8008 has immediate, direct, and indirect addressing

modes. The latter two require a more detailed description.

Registers D The register layout and the seven addressing

codes are shown in Fig. 2.4(a). Mnemonics are used to

identify the seven registers A B C D E H L. All can be

used as general-purpose registers, but three have a special

purpose as well.

Accumulator D Register A is used as the accumulator for

the arithmetic and logical operators. In this case, register

A is implied and no specific reference is made to it in the

instruction.

Memory Operand Address D The registers H and L are used as

the implied memory operand address. To access a location

in memory, the registers H and L are first loaded with the

address of the location; L contains the lower 8 bits of

address and H the most significant 6 bits of address. The

location can then be accessed by executing an instruction

which uses the operand address code lll(M) as the source or

destination. The contents of registers H and L are then

used as the memory address.

Hardware Structures 23

6800 : This has immediate, direct, and indexed operand addressing

modes,

Registers D There are two registers A and B on the chip

that can be used for operand manipulation; a single bit is

used to indicate which one is used. These also serve as

accumulators in the operation orders, both being available

to the programmer,

Memory Operands D In the direct mode, memory operands can

be accessed in two ways. An 8-bit address provided by the

second instruction word gives access to the bottom 256 words

in memory, while a 16-bit address, with two extra words in

the instruction, can access the full 64K locations in

memory,

In the indexed mode, the offset is located in the second

byte of the instruction and is added to the contents of a

16-bit index register on the chip before being used as the

address in memory. The four addressing modes are identified

by 2 bits in the instruction (see Fig, 2,4(b)),

p i 0

1 1

Register

A

B

D2

00

01

10

11

Location

Reg. A

Reg. B

Indexed

Direct Extended

S

00

01

10

11

Location j

Immédiate |

Direct Normal

Indexed

Direct Extended]

Fig.2.4(b) 6800 Addressing codes

Operators

The binary (b) and unary (u) operators provide the basic processing

capability of the machine. Binary operations require two-source

operands, while unary operations only require a single-source operand.

Both will require a destination operand to be specified.

Binary Operators

The main group contains the operators, add, subtract, logical AND,

logical OR, and exclusive OR, which operate on 8 bits in parallel.

They provide the single word arithmetic instructions and bit manipulation


instructions required by the programmer. All arithmetic operations use

the 2's complement numbering system. Multiple word arithmetic can be

performed by using the operators add with carry, and subtract with

borrow. The compare operator subtracts the source operand from the

destination operand, setting the condition flags. It then restores the

destination to its original value. It is a valuable order if comparison

operations are required. Bit test performs a non-destructive AND

between two operands.

Unary Operators

The rotate operators usually require a single operand. They perform a

left or right shift of an 8-bit word-operations which are necessary for

serial-to-parallel conversion-and they greatly simplify the programming

of multiplication and division. Arithmetic shifts are special rotate

orders which maintain arithmetic consistency after the shift operation.

Increment and decrement operations can reduce the number of instructions

and the execution time of program control loops and operand addressing.

New processors contain orders such as negate, complement, test, and

clear. Although they are not essential, they can reduce code and

increase speed of execution.

The move operators are unary orders that require different source and

destination operands and provide the facilities to transfer data between

registers, from register to memory, and vice versa (see References: Lewin

(1972) for a detailed description of operators).

The operator codes must be presented to the processor as binary

information; a well-ordered code can be more easily interpreted than a

random assignment.

[ b code

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

1 u code

0 0 0 0 0 1 0 1 0 0 1 1

1 u code

0 0 0 | o o i

Binary Operators | Add 1 Add with carry 1 Subtract 1 Subtract with borrow 1 Logical AND Logical EX - OR Logical IN-OR Compare 1

Unary Operators |

Rotate le f t round carry 1 Rotate right round carry 1 Rotate le f t through carry Rotate right through carry |

Unary Operator |

Increment | Decrement

Fig.2.5(a) 8008 Operators


8008 : The operator orders and the binary codes used are shown in

Fig.2. 5 (a).

6800 : The operator orders and codes are shown in Fig.2.5(b).

The move orders identified by (1) are unary operators

that have been grouped with the binary operators because

they require two operands.

b or u code

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Binary ( b) Operator

Subtract

Compare

Subtract with

* Logical AND

B i t test

Load (1)

Store (1)

Logical EX-0R

Add with carry

Logical OR

Add

Compare Index

* Load SP + INX

Store SP + INX

Borrow

Reg.

0) (1)

Unary , x Operator v '

Negate

* *

Complement

Logical Shi f t Right

* Rotate r ight

Arithmetic s h i f t R

Arithmetic sh i f t L

Rotate l e f t

Decrement

* Increment

Test

* Clear

Codes unused fo r normal operator orders

Fig.2.5(b) 6800 Operators

Condition Flags

There are five condition flags which are set or reset during the

execution of the operations described above. The flags and the

conditions under which they are set to a logical T are:

Carry - Set if the operation produced an overflow.

Zero - Set if the operation produced a zero result.

Sign - Set if the operation produced a negative result.

Parity - Set if the operation produced an even number of

logical T s in the result.

Overflow - Set if the operation produced an arithmetic overflow,

(e.g. adding two positive numbers producing a negative

result Lewin (1972)).


In ail cases the flags are reset to logical 'Ο' if the condition does

not occur. The flags are used by control instructions to alter the flow

of control within the program. Some processors have instructions which

directly operate on the flags (e.g. clear carry flag).

Instruction Set

Complete instructions are formed by combining the operands with the

operators. The instructions are grouped according to the number of

explicit operand addresses present in the instruction. Additional

instruction words must be used when data or address information is

required in the instruction; thus the appearance of 2 and 3-byte

instructions.

Two address orders:

Register and memory transfer ( D ) - (S)

Immediate transfer ( D ) - n.

Single address orders: Accumulator implied (Register Register and memory operand

( A ) - (A), b . (S)

Immediate operand (A) - (A) . b . n

Increment and decrement (D) - (D) . u*

Zero address orders : Accumulator implied Rotate operations

(A) «.(AJ.U

111 D | S |

o ol 'D 1 no r i Literal (n) |

Π 0| b 1 S' I

0 0 l b ' 11 0 O i l Literal Cn) 1

loom«« i

0 0 | ' u |0 1 0 |

Fig.2.6(a) 8008 Operand instructions

8008 :

6800

Two address instructions

One address instructions

Zero address instructions

MOVE (D)

ARITHMETIC (A)

INC & DEC (D)

ROTATE (A)

(S)

(A)

(D)

(A)

The detailed instructions are shown in Fig. 2.6(a).

Two address instructions

b .

u*

u

One address instructions

MOVE (Dl) «- (S)

ARITHMETIC (Dl) + (Dl) . b.

UNARY (D2) «- (D2) . u

(S)

(S)


These instruction formats are shown in Fig. 2.6(b).

This is not a complete description of the operator

orders of the 6800, the rest are shown in the Appendix.

Two address orders :

Immediate

(Dl) ^ (Dl ).b.n

(Dl) * n (Store order invalid)

(Dl) ^ (Dl ).b.M(n)

| (D 1) - M(n)

Direct extended

(Dl) ^ (Dl) .b.M(m)

(Dl) ^ M(m)

Indexed

(Dl) ^ (D).b.M(IX + n)

(Dl) + M(IX + n)

One address orders :

Register

| (D 1) «- (Dl ).u

Direct Extended

M(m) +■ M(m).u

Indexed M(IX + n)«- M(IX + n).u

i | D i |o'of'A' 1 Literal in) 1

1 | D 1 | 0'l| "b ' 1

Address (n) j |

1 1 Dl 1 1 l| b

Address Pair (m) "I

1 | Dl | 1 " 01 " b" " | ] Offset (n) |

O'l | 0 "D 1 | ' u" " ||

o'l 1 l'l 1 V ' 1 _ Address Pair (m) J

O'l | 1'0 | V ' |

Offset (n) 1

Fig.2.6(b) 6800 Operand instructions

Program Control

For all but trivial programs, instructions are required to allow the

programmer to write jump operations in a program.

Jump Instruction D The information required for a jump instruction

is the address at which program execution continues. The address can be

specified in the same way as operand addresses: direct, indirect, and

indexed. In this case, the address when generated by the processor, is

loaded into the program counter. An addressing method particularly

useful for program control instructions is relative addressing. The

jump address is generated by adding the address in the instruction to


the contents of the program counter. Chapter 4 presents more detail on

this and other addressing modes.

Conditional Jump Instruction D For an unconditional jump, the

program counter always jumps to the address given by the instruction.

A conditional jump is only performed if the condition selected is true;

otherwise the execution of the program continues at the address following

the conditional jump instruction. An operand is required in this

instruction to identify the condition selected. Frequently, a conditional

and unconditional relative jump instruction is referred to as a branch

instruction.

Condition Flag

Carry

Zero

Sign

Pari ty

Higher

< Zero

< Zero

Overflow

Condition Code C |

Flag set

6800

0 1 0 1

0 1 1 1

1 0 1 1

0 0 1 0

1 1 0 1

1 1 1 1

1 0 0 1

8008

1 0 0

1 0 1

1 1 0

1 1 1

Flag rese t |

6800

0 1 0 0

0 1 1 0

1 0 1 0

0 0 1 1

1 1 0 0

1 1 1 0

1 0 0 0

8008 |

0 0 0

0 0 1

0 1 0

0 1 1

Fig.2.7 Condition codes for 6800 and 8008

8008 Λ The jump conditions are shown in Fig, 2,7, Some of the

r conditions are based on the status of two flags, e,g,s

6800 less than or equal.

Jump to Subroutine D There are many situations where a particular

sequence of operations is required many times at different points in a

program. To overcome the need to insert the same piece of program at

each point, a special jump instruction is used (see Fig. 2.8). At point

A in the program, a jump to the subroutine at X is executed, and the

address A + 1 is stored. At the end of the subroutine, a jump (return)

to the address A + 1 is executed. The operation can be repeated at

location B but this time B + 1 is stored.

The jump to subroutine, also named a call, can be conditional or

unconditional, as for the jump instruction.


MAIN PROGRAM SUBROUTINE

Fi g.2.8 The jump to subroutine operation

The return instruction can also be conditional or unconditional, but

does not require the address, since the return address is stored by

the execution of a call instruction.

In the control orders shown in Fig, 2.9(a), only the

direct addressing mode is used; the jump destination

is contained in the 2nd and 3rd byte of the instruction.

The 14 bits of address provide access to any location

in the 16K memory. The return address storage area

(stack) can contain 7 levels of nested subroutine calls.

If the 8th is used3 then one is lost.

Unconditional .jump : Uncondifu (PC) «- m

X = don't care

Oil ' x' h 00

Address Pair(mH

Conditional jump : (PC) «- m if condition C true. JLÜ l o o p

^Address Pa1r(mM Unconditional .jump to subroutine :

Stores (PC) (PC) «- m X = don't care

m l V l i i o UAddress Pair(m)-|

ump Store «- (PC) then as cond. jump

O i l ' C I 0 TO Address Pair(m)-

Unconditional return T (PC) <- Stored address 0 OI'X' M 1 Τ Ί

Conditional return: o o I ' C lo ΓΤ"

Fig.2.9(a) 8008 Program counter instructions


6800 : Unconditional jump instructions have the destination

specified, using indexed, direct extended3 and relative

addressing nodes,

Conditional jump instructions are shown in Fig. 2.9(b).

They are all relative jumps.

Jump to subroutine instructions have the same address

as the unconditional jumps. The return address storage

(stack) is provided in the main memory, which is

addressed by a special register (stack pointer register)

on the processor chip. The number of nested levels is

dependent on the memory size. Instructions to operate

on the stack pointer register are provided. These must

be used with care when subroutines are used in a program.

1 Unconditional .jump:

Direct Extended

(PC) «- m

Indexed

(PC) +- (IX) + n

Relative

(PC) *■ (PC) + n

Conditional jump:

(PC) «- (PC) + n i f condition true

Unconditional jump to subroutine : ,

Direct Extended

Store - (PC), (PC) * m

Indexed

Store ♦ (PC) , (PC)«-(IX) + n

Relative

Store * (PC) , (PC)«-(PC) + n

Return: (PC) «- stored address

oYi^i | ι ΊΊΌ - Address Pair (m) '

O ' l ' l ' d f l ' l ' l ' O

, Offset (n)

o'o'i'o | o'o'o'o

Offset (n)

o'o'l'o | c

Offset (n)

ι 'ο 'Γι | ι Ί Ό Ί

•Address Pair (m)

l'o'i'o I ι Ί Ό Ί Offset (n)

1ΌΌΌ | l 'l 'O'l

Offset in)

o o i i 1 i o o i 1

Fig.2.9(b) 6800 Program counter instructions

Input^Output

A microprocessor must be able to communicate with its external

environment by input and output operations. This can be provided by


special input-output instructions, or by allocating memory as input or

output registers. The latter technique requires no additional hardware

on the microprocessor chip, but program overheads may be high. The

memory addressing becomes fragmented and large decoders are required.

Input and output orders require additional logic on the chip, but can

be more efficient in time and program store.

8008 : The I/O orders are single address instructions with

implied accumulator3 thus:

(A) «- I(N) or O(N) + (A)

where N is the input or output port address (Fig.2.10).

6800 : The memory is used for I/O and no special orders are

provided.

Input-Output A «- Input register Port N.

N=0 to 7 Output register port N ·*■ A

N=8 to 31

0 1 N 1

Fig.2.10 8008 Input-output instruction

PROCESSOR DATA PATHS

An important limitation of the design of a single chip processor is

the size of package, or pin out. The number of external connections

is critical in determining the machine structure and the quantity of

external logic. The basic organization of the data paths is shown in

Fig. 2.11. This is examined in order to obtain an understanding of

the basic requirements of the data paths. The machine timing consists

of:

Instruction fetch (GQ)

Decode instruction (G1)

Operand fetch (G2)

Execute (G-)

Orders which do not require an operand from memory will miss the G«

beat. Times GQ and G« contain the address and data load time, a functi

of the processor speed, and the memory access time. To allow for slow


OA Γ

^Th

^rCl ·^

I Chip

Boundary

Ï=D-<j^t

N Data ♦ 1 Read signal

16K

MEMORY

DATA PATHS

PC Program counter register IR Instruction register MA Memory address register MR Memory data register

OA Operand address register

OR Operand register

R Read memory si gnal

Fig.2.11 Basic data paths

memories, the processor activity may have to be suspended by forcing

it into an idle state. Therefore GQ and G2 will have an asynchronous

period, depending on the system configuration. The pin count for this

data path organization breaks down as follows: Address bits N9 Read/

write 1; Data in 8; Data out 8; a total of 17 + N. More are needed for

control and I/O communication.

6800 : This has the structure described, except that the 8-bit

data paths are commoned into a bidirectional bus. The

read signal is then used to indicate the direction of

the data flow on the bus.

8008 : The organization of the data paths is not based on this

basic structure because the number of pins required is

too great for an 18-pin package. An alternative is to

have a single 8-bit bidirectional port and arrange for

all the data to pass through in an ordered time sequence

(Fig. 2.12).

The beats G and Gp are subdivided into time intervals T 3 T Λ and

T , which identify the status of the information at the data port. 6

These signals are needed both internally and externally. More logic


G0J2

: [7H PC (H) ! (L)

=01 o ?| - ( [GOJ3

LL — ! ' -+*► R

OA | 1H) ! ( L ) \°2

__gJLR.G2J3j ^

OR -T=

I 8 Data toi 16K MEMORY

MR ( I ) 4

V I- R.G2.T DATA PATHS

f T l copy PC(L) t o MA(L) <12 copy PC(H) t o MA(H) L.T3 copy MR(O) t o IR

Control Timing

f T l copy OA(L) t o MA(L) r J T 2 copy OA(H) t o MA(H) b2 v 3 - R c°py MR(°) t 0 0 R

LT3.R copy OR to MR(I)

Fig.2.12 Multiplexed data paths

is required outside the chip to latch the port data-one penalty for

reducing pin count—and the machine beat is slower since more

processor cycles are required to transfer the information to the

memory system.

Input and Output

Input and output can be organized by mapping the input-output registers

within the processor memory space, or by having a special input-output

register space. In the former case, the data paths required are

identical to those required for memory accessing; although the memory

decoder will be a discrete set of logic gates connected to one or more

registers. In a processor where special input-output instructions are

provided, additional data paths may be needed.

8008 : The input and output instructions utilize the memory

access sequence described above in a special way. During

the operand fetch cycle, the processor executes the

input-output order3 but the data transmitted is different

to that for a normal operand fetch. The G^ sequence is:

Τη copy accumulator to output buffer

T9 copy port address to port address buffer

T copy input register to accumulator or load 6

output buffer to output port.


OUT 1

CENTRAL 1 PROCESSOR Γ

L

L T J

OUT N

OUT DEC

L

1 1

Θ BIT BUS

MEMORY

i I IMI-UI ! A i 1

L

h-: 8 '

^Γ Γ-.

PUT ODE

lr-STRC )BE

L

T2

8

f 8

"

5 > ^ l

πτ; . ^ "" V—Y - ΚΙΔ-

"Ί 1

J t t U U t

1 IMPM 1 C

T3 KEY

L 8 BIT LATCH D 5 BIT DECODER

Fig.2.13 Input-output structure

The basic circuitry required to interface the processor

to digital input or output signals is shown in Fig, 2.13,

By careful use of the information capacity available, the

designers have produced an input-output system that only

utilizes the memory interface signals.

6800 : As the input-output is organized within the memory space,

the memory organization specifies the input-output

organization. Special input-output devices are provided

to simplify input-output system design (Motorola, 1974).

Processor Control Signals

The transfer of data between the processor and external devices is

synchronized by control signals that must cross the chip boundary.

At the hardware level, control signals are needed to indicate that

bus data is valid and to specify the data type. This information is

interpreted by the external hardware to ensure that it uses the data

correctly.

Before data transfers are executed the processor must be synchronized

to an external device. If the memory access time is longer than the


maximum allowed within the synchronous processor cycle, then the processor

must be made to idle until the memory is ready to perform the transfer.

8008 : A READY signal is available externally> and when low, the

processor idles and replies by issuing a WAIT status.

6800 : No direct mechanism exists3 but the clock can be stopped

for a short period.

Processor—input-output interaction can occur in four ways:

(a) Unconditional Transfer D The timing of the external event is

unimportant. The input-output transfer occurs at a particular point in

the program immediately the order is executed (as in the circuit of

Fig. 2.15).

(b) Conditional Transfer D Again, the input-output transfer

occurs at a specific point in the program, but in synchronism with an

external control signal. The processor is made to idle, using a hand-

shaking procedure, until the conditional signal is true. This can be

achieved by program, but for slow memory and time-critical input-output

situations, a ready-wait handshake protocol is used. When the ready

signal (RDY) is low, the processor enters an idle state and issues a

wait status signal. When RDY is raised, the processor continues with

the execution of the instruction (see Fig. 2.14).

8 BIT BUS

CONTROL LOGIC

v VOUT

Fig.2.14 Digital to analogue converter

(c) Interrupt D An interrupt input-output transfer occurs

asynchronously with respect to the program currently being executed.

When an interrupt is detected by the processor at the end of the current


instruction execution, the processor suspends the current program and

jumps to the program associated with the interrupt recognized. The

status of the suspended program is stored either automatically or under

program control. The processor completes a handshake in response to an

interrupt signal (INT) and issues an interrupt acknowledgement when

servicing the interrupt.

(d) Direct Memory Access D An external processor may require direct

high speed access to the memory. A request is made to the central

processor to relinquish the address and data paths (DMARQ); the CPU

then signals to the external device that it has done so (DMA ACK).

See Chapter 5 for a more detailed description of input-output operations.

Summary of Control Signals

8008 The control signals of the processor can be summarized

as follows:

2 Clock signals

1 Sync,

3 Code status j

bits OUT

1 Ready signal

1 Interrupt

IN

OUT

i l l , T23 T3

T4, T5

Til

WAIT

STOPPED

IN

IN

Data type and

data timing

Execute beats

Handshake for INT

Handshake for RDY

Handshake for HALT inst.

These, together with 2 power and 8 data pins, comprise the

full complement of the 18-pin package,

The control signals are:

2 Clock signals IN

1 Address valid OUT

1 Read write OUT

2 Interrupt requests IN

2 DMA request IN

1 DMA acknowledge OUT

2 Hardware control IN

Data and

address timing

and validation,

Int, request (no handshake

on hardware)

DMA handshake signals

Halt and reset signals


EXAMPLES OF INPUT DATA

A block diagram of two typical processor input-output systems are shown

in Figs. 2.14 and 2.15. The first demonstrates the use of a digital-to-

analogue converter and comparator as an analogue interface. Applications

of the system are analogue-to-digital conversion, probability density

measurement, and threshold detection. The second shows an operator's

console for a goniometer control system, interfaced to the processor

highway.

B 8 BIT BUS

TH: BCD THUMBWHEEL SWITCHES

?TOrÎV' Fig.2.15 Simple switch console

3 Case Studies

BACKGROUND-HARDWARE AND SOFTWARE

The user of a large computing system can remain totally isolated from

the machine and most of its peripherals, both in a literal sense and in

that he need have little or no knowledge of the hardware details. Lower

down the size scale, at the minicomputer level, it is more likely, though

often not essential, that the user becomes involved with the hardware,

even if it is in the sense of becoming familiar with more of the

peripherals such as analogue-to-digital converters. Nonetheless, it is

probably true to say that at this level also most users are software

orientated.

At the bottom of the computer size scale comes the microprocessor.

Here, for the present at least, the user finds a need for both hardware

and software knowledge. For the software support, the development of

which inevitably tends to lag behind the hardware,is yery much in

its infancy, and the subject of much discussion and conjecture.

Consequently, most users at present are working in a low-level language,

assembly code, and contend manually with such problems as matching the

hardware with the software for input-output assignments, memory addressing,

and so on. Trends in software support is the theme of Chapter 7.

Another reason for the need for an understanding of both hardware and

software is the role of the microprocessor. Unlike its larger brethren,

it is unlikely to become a general-purpose machine, but instead may assume

a more specialized role such as the heart of an instrument performing

some sequence control or simple signal processing. In this respect,

there is clearly an area of overlap in applications with the minicomputer,

just as the minicomputers themselves overlap with larger machines.

Of course, the user of the microprocessor might equally have a background

of logic design, and if the approach described above may be considered as

reduction in size accompanied by a greater knowledge of hardware, then the

logic designer's approach is almost the reverse: an increase in sizeH:hat

is, complexity-and a user requirement in software knowledge.

38

Case Studies 39

STUDENT PROJECTS

The undergraduate and postgraduate students who undertake projects

incorporating microprocessors usually are following courses in computer

technology or electrical engineering. The students possess a limited

background knowledge of both hardware and software and some logic design

experience; but this is largely theoretical, and nearly all start with

little practical experience of either computing or logic design. The

projects can take anything from an afternoon to six months or more.

Some typical examples are quoted below.

Traffic Light Simulation

A simple physical model of a road junction and pedestrian crossing

executes a defined sequence and includes the servicing of external

requests from pedestrians.

Stepping Motor

A simple yet informative example of a digitally controlled servo-

mechanism which, as with the traffic light example, demonstrates

principles of sequence control. This example is treated in detail in

Chapter 8.

Fast Fourier Transform (FFT)

A FFT algorithm is implemented. It is used in applications such as

interferometry and systems identification (see below). The Walsh

transform is available also.

Interferometry

The project here is to process interferograms of the far infra-red

region, but to do the computing locally, i.e. in the laboratory, and

on-line. The FFT algorithm is incorporated into the spectral

calculations.

Function Generator

For simulation purposes an instrument is designed to synthesize

relatively complex waveforms, periodic or nonperiodic.

40 Case Studies

Sinewave Generator

Essentially this is a much simplified version of the function generator;

here the output is restricted to a sinewave of fixed amplitude but

variable frequency. Below, this example is considered in some depth.

Systems Identification

The identification process is based on the well-known pseudo-random

binary sequence (PRBS) technique. The microprocessor is programmed both

to generate the PRBS and to perform the subsequent analysis procedures:

(correlation, averaging, Fourier transform). The first part is realized

by simulating a feedback arrangement around a shift register, while the

second stage involves the mathematical functions.

This last example leads to the idea that microprocessor applications

may be divided into two broad categories, and a glance back at the list

above clarifies this notion. The first two are sequential controller

examples where a standard logic design approach would suffice, whereas

the FFT and its applications are orientated towards signal processing-

computation often performed on large general-purpose machines. The

microprocessor is capable of serving both classes (16-bit processors

being very important for the latter) and, hence, calls for an

amalgamation of the logic designer and program designer.

SINEWAVE GENERATOR-CASE STUDY

Specification D A system is required which outputs a sinewave with

the frequency variable, in steps up to 200 Hz, but with fixed amplitude.

Now the specification suggests that one input parameter should control

the frequency and that the output is a sinewave; it is from this point

that the design commences. A good account of design philosophy in general

is given in Chapter 8; so for this example one possible solution is

described, accompanied by brief comment.

The system is to generate a sinewave by regular outputs of discrete

samples along the time course; two possibilities are, either a 'look-up'

table where a block of memory contains equally spaced samples, or a

routine which calculates the waveform values as they are required. In

making a choice, one should consider:

Case Studies 41

(a) ease of programming

(b) time specification

(c) accuracy

(d) memory requirements

Here, primarily because of (a), a'look-up'table is adopted and the

programming strategy is to step through the table at an appropriate rate.

This then is the first level of design—the overall strategy. Clearly,

a table containing elements spanning the full period of the sinewave

would mean that the output could be achieved by simply stepping through

to the end of the table and returning and repeating from the beginning,

but this would be expensive in memory, since all the information is

available from a single quadrant (a 4:1 reduction). The algorithm

described by the flow diagram in Fig. 3.1 steps forward and backwards

START

Ί I Create Look-up Table |

| Loop r=l to M |

Check si gnj

[Output sample J

| Form time interval |

1 Repeat "r~|

| Reverse s ign~|

|—| Loop r - M-l to 2

Check sign |

| Output samp1e~"|

| Form time interval |

Repeat r~|

1

Starl

■ - .

r M

1 End

N = 4(M-1)

Fig.3.1 Sinewave generator—single quadrant look-up table

42 Case Studies

through the one quadrant, checking and reversing the sign flag on passing

through zero. The cost is an increase in the complexity of the program

(and may be an increase in the effective cycle time), but a compromise

is reached between (a) and (d).

A second flow diagram, Fig. 3.2, is merely an expansion of the first

New Cycle

] | Set Sign Flag & Clock|

Subtract & 0/P

Add & 0/P

] - r -0/P Routine

__J__ Time Interval

| Reverse Sign Flag |

0/P Routine (as above)

I I Time Interval

[Decrement Pointer |

Fig.3.2 Sinewave generator—second flow diagram

and helps to make the transition into assembly code as well as recording

the thoughts of the designer-most important in large projects. In the

next stage of the development the hardware requirements are identified

and matched with the software when producing the assembly and machine

Case Studies 43

codes. A memory map, hardware layout, and codes for the sinewave

generator are given at the end of this chapter.

Finally, there is the testing, 'debugging' and, where appropriate,

calibration. This can prove a most troublesome stage, all too often

aggravated by a poor specification and inadequate documentation. It is

most desirable that the system specification should be of adequate

detail and unambiguous, and that all levels of design are documented

thoroughly. When 'debugging', (an inevitable activity in almost any

design), errors often need to be traced back through the various levels,

from the machine code right back, if necessary, to the initial specification,

and an accurate record of the program designer's thoughts assist this

process significantly.

A calibration curve (Fig. 3.3) for the 8008 shows the relationship

Period T (ms)

T - 0.75 C + 5.25

T - 0.5 C + 3.5

2UO 280

Interval Count (Register C) (Decimal)

Fig.3.3 Sinewave generator calibration curve (8008)

44 Case Studies

between the frequency of the sinewave, the interval count and also the

effect of increasing the number of samples per cycle N. Extrapolation

for larger N is straightforward: from the curves an approximate equation

for frequency is

_ 16000 where 0<c<256 * N{o+7) is the interval count

Thus, if one full page of memory was used to store the single quadrant,

N = 1024, (the maximum permissible without rewriting the program) the

range of frequencies would be approximately 0.06 Hz up to 2 Hz; to meet

the specification of 200 Hz the maximum permissible value for N is 12.

Of course, larger values of N improve the shape of the waveform.

Clearly there are many limitations of this sinewave generator design

when considering a practical instrument: accuracy, low-pass filter

requirement, frequency not continuously variable, etc. But it is a

simple example aimed at demonstrating design procedure.

COMMENTS

In conclusion it is worth reflecting on the experience gained from

projects such as the ones listed. First, the initial specification is

invariably too loose, because all the questions cannot be answered at

the outset, and also additional flexibility might be thought desirable

to produce an attractive 'all-purpose' system. This can result in

either a tremendous increase in the design and redesign times, or

perhaps an instrument which is not quite what the customer wants. Stages

in project development should include the tasks of Fig. 3.4.

Study Specif ication

Input/Output Requirements

Algorithm Design

Match Hardware and Software

/ \ Construct Hardware

\ Testing

Code Program

/

Fig.3.4 Design procedure

Case Studies 45

All too frequently, insufficient attention is given to the first stage.

Also, it is obvious that the designer must have knowledge of both

hardware and software, irrespective of the complexity of the project.

Finally, the comparative lack of software support for microprocessors

makes the translation from the algorithm into assembly or machine code

a rather tedious job.

Memory Map and Hardware Layout

The allocation of data in the memory is shown in Fig. 3.5.

8080 8008

Page/line (Octal)

000.000 s

TO

001.000C

TO

0 0 2 . 0 0 0 ;

TO

0 0 3 . 0 0 0 ;

►

Registers

B

C

: } i/o

Port 8

Memory Maps

Stack Stack and (8080) Subroutines

to i n i t i a l i s e 1/0

Data i . e . Look-up Table

Main body of program and subroutines

Sign f lag

Frequence control

Look-up Table pointer

To 6-b i t DAC

6800

(Hexadecimal)

, 0000

TO

\ 0140

-^ 0240 /General < work

, 0250 espace

TO

^ 0350

Special Locations

0240

0241

Index Register

Memory mapped

800A

Fig.3.5 Memory map for sinewave generator

A suitable hardware configuration is shown in Fig. 3.6, and a complete

description of the individual elements can be found in Appendix 4.

Case Studies

Memory-

Microprocessor I/O Por ts

Console

Oscil loscope

D I I

Fig.3.6 Hardware layout for sinewave generator

FRWD

BKWD

Assembly Code

LBI

LCI

LHI

LLI

CAL

CAL

INL

LAI

CPM

JFZ

LAI

XRB

LBA

CAL

CAL

DCL

LAI

CPM

JFZ

JMP

♦ S u b r o u t i n e s

OUT

PSTV

LAI

CPB

JTZ

SUM

ADI

OUT

RET

LAM

ADI

OUT

RET

000

001

001

000

OUT

CLK

000

FRWD

OUT

CLK

037

BKWD

FRWD

000

PSTV

040 10

040 10

♦ I n t e r v a l forming

CLK

LOOP

LDC

DCD

JFZ RET

LOOP

Address

002.000

.002

.004

.006

.010

.013

.016

.017

.021

.022

.025

.027

.030

.031

.034

.037

.040

.042

.043

.046

002.200

.202

.203

.206

.207

.211

.212

.213

.214

.216

.217 subrout ine

002.220

.221

.225

Machine Code

016

026

056

066

106

106

060

006 277

110

006

251

310

106

106

061

006

277

no 104

006

271

150

227

004

121

007

367

004

121

007

332

031

110 007

000

001

001

000

200

220

000

010

377

200

220

037

031

010

000

213

040

040

221

002

002

002

002

002

002

002

002

002

Comment

In i t ia l ise sign flag

Set clock interval count

Load base address of look-up

table

£orward_ through table

Call 0/P and clock subroutine

Increment table pointer

Test table value for

quadrant end

False:continue forward loop

Complement (reverse)

sign flag and replace in

register B

jlackward through table

Call 0/P and clock subroutines

Decrement table pointer

Test table value for

beginning (peak)

False:continue backward loop

Start new cycle

Output subroutine

Check sign flag for zero

(+ve half cycle)

True:jump to positive

Negate sample value

Add offset (see DAC spec.)

0/P to port 10

Return from subroutine

Ace. A -- sample value

Add offset

0/P to port 10


Reg. D ■*■ Interval count

Loop for Interval count

Note: Octal used throughout.

Fig.3.7 Sinewave generator for 8008

Case Studies 47

Assembly Code Contient LXI SP 000.377 Set Stack Pointer MVI B 000 Set sign flag

MVI C 001 Set clock time interval

LXI H 001.000 Load data base address

FRWD

BKWD

CALL

CALL

INR MVI

CMP JNZ

MOV CMA

MOV CALL

CALL

DCR

MVI CMP

JNZ JMP

*Subroutines OUT MVI

PSVE

CLK LOOP

Note:

CMP JZ

SUB ADI

OUT RET

MOV ADI

OUT RET

MOV DCR

JNZ RET

Octal

OUT

CLK

H A 000

M FRWD

A,B

B,A OUT

CLK H

A 037

M

BKWD

FRWD

A 000

B PSVE

M 040

10

A,M

040

10

A,C A

LOOP

used throughout.

Fprvard_ through table: Call 0/P routine

Form time interval

Increment table pointer

Ace. A «-zero

Test for zero (end of table)

Cycle until zero

Ace. A*- B

Complement (reverse) sign flag

Replace sign flag to B

Backward through table

Form time interval

Decrement table pointer

Ace. A ■*■ peak amplitude

Test for peak (beginning of table)

Cycle until peak reached

Restart new cycle

Test sign flag for zero

(+ve half cycle)

Jump when zero

Negate sample value

Add offset (see D.A.C. spec.)

0/P to port 10


Ace. A ·*· sample value

Add offset

Output to port 10


Timing subroutine

Loop for Interval

Count c



48 Case Studies

Address Machine Code

Hexadecimal Assembly Code

0140 0140 IF 0141 17 0142 00

0240 0240 0241

0250 0250 0253 0256 0259 025A 025B 025C 025F 0260 0263 0266 0268 0269 026B 026E 0271 0272 0275 0278 027A 027B

00 01 0100

8E 00FF BD 0100 CE 0200 01 01 01 BD 0300 08 BD 0317 8C 0202 27 03 01 20 Fl 73 0240 BD 0300 09 BD 8C 27 01 20

SETPIA

EQ

0317 0200 DF

Fl

FRWD

SB BKWD

ORG FCB

ORG FCB

EQU ORG LDS JSR LDX NOP NOP NOP JSR INX JSR CPX BEQ NOP BRA COM JSR DEX JSR CPX BEQ NOP BRA

0140H 1FH,17H,00

0240H 00,01

0100H 0250H #00FFH SETPIA #0140H

OUT

CLK *0142H SB

FRWD 240H OUT

CLK #140H EQ

BKWD

Define origin Look-up table

Define or ig in Set sign f lag and clock

Define address of 'SETPIA'

I n i t i a l i s e stack pointer Set up I/O ports

Start of cycle Sample time equalisation

Forward through table

Form time interval End of look-up table?

Reverse sign Flag Backward through table

Start of table?

Sample time equalisation

LOCATE SUBROUTINES

0300 0300 0302 0305 0307 0309 030B 030E 030F 0311 0313 0316 0317 031A 031B 031D

SETPIA EQ FRWD SB BKWD OUT PSVE CLK LOOP

86 00 B l 0 2 4 0 27 08 AO 00 8B 20 B7 800A

39 AB 00 8B 20 B7 800A 39 B6 0 2 4 1 4A 26 FD 39

0 1 0 0 0 2 5 9 025C 026B 026E 0 3 0 0 0 3 0 F 0 3 1 7 031A

OUT

PSVE

CLK LOOP

ORG LDA CMP BEQ SUB ADD STA RTS ADD ADD STA RTS LDA DEC BNE RTS END

Symbol Tab le

Addresses o f Symbols used

0300H #0 0 2 4 0 H PSVE 0 0 , X #20H 800AH

00,X #20H 800AH

0241H

LOOP

Note:

Define or ig in

Check sign f lag

Jump when zero(+vehalf cycle) Negate sample value Add of fset (see DAC spec.) 0/P Return from subroutine Time equalisation with SUB Add offset 0/P Return from subroutine Interval forming subroutine Loop for interval count

Suffix H indicates Hexadecimal


Case Studies 49

Listings

Assembly code listings for the three machines, 6800, 8008, and 8080,

are given in Figs. 3.7 to 3.9. For the 6800, an assembler was used to

produce the object code, merely for the purpose of illustration; for

the 8008, the process was done manually. Note the solutions could be

enhanced by making the frequency a variable at run time, via either

an ADC or digital switch.

In attempting to improve the end result another point to consider is

the time interval between successive outputs-clearly this should be

constant. Now the simple loop counter (subroutine CLK) together with

the time to execute the main loop and the output subroutine govern

the time interval, and examination of the operation times will show

discrepancies at the end of each quadrant. Where necessary equalization

can be achieved by inserting dummy operations (no ops). This has been

done for the 6800 but is left as an exercise for the reader for the

8080 and 8008. Instruction times will be found in Appendix 1; note

that for the conditional jump instructions there are two alternatives

for the 8008.

4 Addressing Modes

INSTRUCTION WORD FORMAT

The central processing unit (CPU) of a general-purpose computer requires

five basic items of information each time it executes an instruction in

a program. They may be listed as:

(a) the location of the next instruction

(b) the code for the operator

(c) the location of the first source operand

(d) the location of the second source operand

(e) the location of the destination operand

All five items could be contained in each instruction word of the

program stored in the main memory. It is not usual to do this, mainly

on economic grounds because of the length of the resulting instruction

word and the storage capacity required for the program. If the

information is not provided in the instruction word, then it must be

provided by some other means. It is normal practice, for example, to

provide the information in (a) by a separate register, called the

'program counter'. Because instructions are normally required to be

obeyed in sequence, the contents of the program counter need only be

incremented to provide the next instruction address. If an instruction

is required which is out of sequence, then a special jump instruction

must be used to load the program counter with the relevant address. If

(a) were included in the instruction word, a separate jump instruction

would not be required.

By providinp a fixed initial destination (an accumulator) for all

operands, item (e) could also be removed from the instruction word. A

special operator would then be required to permit the transfer of the

contents of the accumulator to a specified memory location.

If the source of the second operand were always taken to be the accu-

mulator, then item (d) could also be removed from the instruction word.

Thus, the initial universal instruction word consisting of five fields,

and known as a 4-address format, may be reduced to a 1-address format.

In general, a greater range of operators is required to compensate for

50

51 Addressing Modes

the lack of generality, and usually more instructions are required to

complete a given operation when a restricted address format is used.

It is possible to reduce the instruction word format to the ultimate

of 0-address, in which case the operands are to be found in fixed

locations, and special long instructions, formed by concatenating two

or more instruction words, are required to transfer operands between

these fixed locations and specified memory locations. The most frequently

used formats are the 1-address and 2-address, and it is usual to find a

mixture of different formats in one machine.

Although it has been assumed so far that each operand field of the

instruction word contains information about the location of the operand,

this information need not be the actual address in memory of the operand.

Indeed, as will be shown in the next section, it is desirable that the

operand field information be capable of specifying the location of the

operand in a number of different ways. These different ways of

specifying the location of the operand are generally known as addressing

modes, and together with the range of operators provided in a particular

machine, will largely determine· the computing power or usefulness of

that machine.

COMMON ADDRESSING MODES

Immediate

In this mode the operand field contains the operand itself. It will

usually be the numerical value of the operand, but in some machines a

name corresponding to the operand may be used instead.

The provision of this mode of addressing is necessary in order to permit

the loading of numerical values, which may be constants or the initial

values of particular variables, into memory locations or particular

machine registers.

6800 : LDA A if 23 ; Load accumulator A with the number

23 hexadecimal.

8008 : LUI 23 ; Load the number 23 octal into a

location determined by contents

of memory register M,

52 Addressing Modes

Direct

In direct addressing the operand field contains the address of the operand.

This mode of addressing is useful when a series of calculations is being

performed and the result of a calculation at one stage is to be used as

data for the next. If a particular memory location or set of memory

locations is to be used as a store for the intermediate results, the

programmer simply has to refer to the specific location by its address

to find the data. If only the immediate mode of addressing were available

then, because the data is changing during the course of the problem, the

programmer would have to write a large number of individual instructions,

each referring to a separate item of data.

; Load accumulator A with the contents

of memory location 23 hexadecimal

Transfer data at input port No, 7

to the accumulator.

Indirect

The operand field in this case contains either a memory address or an

internal register name. The contents of the memory location or the

register referred to are used as the address of the operand.

This mode of addressing is useful when a program contains a number of

instructions referring to a single operand. If the operands had to be

relocated to another part of memory, then if the direct addressing mode

had been used, all instructions referring to that operand (and

instructions referring to other operands) would have to be modified

so that the new operand addresses would be changed for the old ones.

If, however, the indirect mode had been used, the program itself need

not be altered. The only alteration would be to a table which lists

the relationship between the actual operand address and the operand

field used in the instruction. The amount of effort involved in the

modification is thus greatly reduced.

8080 : WAX BC : The contents of the memory location whose

address is in register pair BC is moved

to register A. (See Fig. 4.1)

Note that indirect addressing is not available on the 6800, and is

available only through register addressing in the 8008 and 8080.

6800 : LDA A 23

8008 : Ifjp ?

8080

Addressing Modes 53

Main Memory Registers B C Register A

Befoi

Register A

After

Fig.4.1 Representation of the LDAX BC instruction

Indirect addressing is frequently found in computers with a small

word length, where the size of the operand address field is limited

and insufficient to address the whole of the main memory directly.

The memory is divided into a number of equally sized sections, called

pages, the whole of each page being capable of being addressed directly

by the limited operand field. When an instruction word is fetched from

the memory, the operand field is used to access an operand within the

same page as the instruction word. Because each operand in memory will

be full length, i.e. long enough to address the whole of memory, this

operand can be used as the address of the true operand and is capable of

accessing operands anywhere in the memory.

Auto-Increment/Decrement

Indirect addressing is often used to sequence through a table of operands.

The address of the first operand in the table is placed in a register and

the first operand is accessed by indirect addressing of the register. The

register contents are incremented/decremented before the next operand is

accessed. In some machines, the incrementing/decrementing of the register

contents is done automatically when the operand is accessed. This extra

facility is known as auto-increment/auto-decrement.

Indexed

This is effectively a special form of indirect addressing. The number

in the operand field is added to the contents of a register called the

index register (sometimes called the modifier register), to determine

LOC:

54 Addressing Modes

the operand address. In some computers there is more than one index

register, in which case the instruction word must contain the identification

of the index register to be used. Various operators are usually available

to permit modification of the number in the index register.

6800 : Fig. 4.2 illustrates what happens when the instruction

LDA A 43 X is executed.

Register A

Befoi

Register A

After

Fig.4.2 Representation of the LDAA 4,X instruction

The indexed mode of addressing is very convenient when the same

calculations, or sequence of calculations, has to be performed upon

different sets of data. If the data is stored in a series of memory

locations, then at the completion of the calculation on the first set

of data, the index register contents are changed so that during the

next calculation the addresses formed will be those of the next set

of data·.

An example of this is the simple waveform generator discussed in

Chapter 10. In that example, the same sequence of operations is performed

on each segment of data in turn.

The 8008 does not have an indexed mode of addressing, but the 6800 does,

and therefore the example program for the latter has been written using

this facility. The range of operations available on the index register

of the 6800 is limited, and this requires the repetitive use of the

increment index register instruction (INX) in order to change the

register contents.

In machines with an index register, therefore, it is desirable to have

other operators which allow the direct addition/subtraction of numbers

to the register contents.

Main Memory Index Register

1 0 0

Addressing Modes

The 8080 does not have an Index register as such, and the 8008

program could be used for the 8080. However, the 8080 does have a form

of indexed mode addressing because arithmetic operations can be performed

on register pairs BC, DE and HL which are also used for memory addressing.

This is illustrated in the 8080 program for the simple waveform generator

in Chapter 10.

OTHER ADDRESSING MODES

Register

It is common for even small computers to have several general purpose

registers inside the CPU. These are quite separate from the registers

in the main memory, and are usually referred to either alphabetically or

numerically.

In the register mode of addressing, the operand field contains the

description of the register to be used. In a similar manner to memory

addressing, register addressing may be direct or indirect in most

machines.

8008 and 8080 : Both have seven such registers.

In the 8008, the register description is

contained in the operator itself (see Inherent

Addressing^ e.g:

IND ; increment register D

In the 8080 the register description is in a

separate field, e.g:

INX D ; increment register pair DE

Accumulator

This is simply a particular form of register addressing, because the

accumulator is usually one of the internal registers.

6800 : This has two internal registers only, known as accumulators

A and B:

CLE A ; the contents of accumulator A

are replaced with zero.

56 Addressing Modes

Inherent

This is another particular form of register addressing. It is a mode of

addressing used in some computers where the register to be used is implied

with the operator. The operator and operand descriptions can be considered

to be contained in one field:

8008 : RAL ; rotate accumulator left.

6800 : CBA ; compare accumulators A and B.

Relative

In relative addressing, the operand address is determined by adding the

address specified within the operand field (offset) to another address,

known as the base address. In many computers, relative addressing applies

only to branch instructions and the base address is derived from the

program counter. The offset in this case is usually an 8-bit number

having a decimal value in the range -128 to +127. It can be calculated

as:

Offset = destination address - program counter - 2.

In the source program statement, the absolute address of the destination

of a branch instruction, either as a numerical value or as a name, is

specified. The assembler determines the offset.

Branch instructions are generally used when a test has been performed

and it is required to return to the beginning of a loop. The number of

instructions in the program over which branching is required is usually

quite limited. Hence, the advantage to be gained by using relative

addressing is that only a small address need be used as it is the

incremental address which is required. It would be inefficient in terms

of storage requirements to provide a full absolute address field, capable

of branching anywhere in the program, for each branch instruction.

6800 : P.C. Value (hexadecimal) : Example program:

0200 LOOP :

0250 BNE LOOP

The relative address = D -(PC + 2) = 0200 - 0252 = AE Hexadecimal

57 Addressing Modes

The programmer, therefore, need not be concerned with calculating the

relative address unless programming directly in machine code.

When it is required to branch over a range outside the limits of the

relative address field, it is usual to branch to a near location containing

a jump instruction, which has a full absolute address field.

In some applications, the facility to locate a program anywhere in

memory is desirable. Relative addressing enables this to be achieved

without modification to the program.

THE STACK

General

The stack consists of a number of registers which may be inside the CPU

(8008), and therefore limited in number, or in the main memory (8080 and

6800), and therefore virtually unlimited in number. Special control

logic inside the CPU ensures that when information is stored in the stack

in a certain sequence, it is retrieved from the stack on the basis of

'last in—first out'. The CPU has a register called a stack pointer

register whose contents, the stack pointer, is used to address the next

register to be used in the stack. Different machines have different

ways of maintaining the stack.

Stack Stack

Before After

Fig.4.3 Storage of information in 6800 stack

6800 : When information is stored in the stack, it is stored at

the address which is contained in the stack pointer. The

stack pointer is decremented by one immediately following

the storage of information in the stack, and incremented by

one immediately before information is retrieved from the

58 Addressing Modes

stack. The stack pointer is therefore normally pointing to

the next empty location in the stack. This is illustrated

in Fig. 4.3.

8080 : A different method of maintaining the stack is used. The

stack pointer contains the address of the last item of

information in the stack. HenceΛ when information is stored

in the stack, the stack pointer is decremented by one

immediately before the storage of information. When information

is retrieved from the stacks the stack pointer is incremented

immediately after information is retrieved. This is

illustrated in Fig. 4.4.

Before

Stack

X

U- ^J

SP

Stack

X 1

Y

Z

- ^J After

Fig.4.4 Storage of information in 8080 stack

Usually, special operators are provided for manipulating the stack

pointer, and it is important that the programmer ensures that the stack

pointer is initialized before the execution of the first instruction

involving the stack.

Other operators effect the storage and retrieval of information

in the stack. The decrementing and incrementing, of the stack pointer

is performed automatically as part of the operator function.

Use of the Stack

Subroutines

The stack provides an orderly method of storing a subroutine return

address and returning from a subroutine. This is probably the most

59 Addressing Modes

common use of the stack, and in machines such as the 8008 where the

stack size is limited, it may be the only use of the stack.

A return address is saved on the stack automatically when a subroutine

call is executed. The return address saved on the stack is that

corresponding to the next instruction after the subroutine call. Sub-

routine calls are usually terminated by a return instruction in the

program. Upon execution of this instruction, the return address is

obtained from the stack and loaded into the program counter.

The 'last in—first out* procedure used with the stack allows subroutine

calls to be made within another subroutine (nested subroutines).

Storing Machine Status

Another use of the stack is storage of the contents of the internal

registers (machine status) of the CPU when an interrupt from a peripheral

device occurs. The servicing of an interrupt requires the CPU to

execute another program sometimes called the device service routine. In

order to return to its current program correctly after servicing the

interrupt, the contents of the CPU internal registers are first stored

on the stack, to be retrieved later. Again, as with subroutines, the

stack allows nested operation, i.e. the servicing of an interrupt may be

temporarily suspended, whilst a higher priority interrupt is serviced.

The maximum depth of nested operations is determined by the size of

the stack. Precautions must be taken by the programmer, therefore, to

ensure that the capacity of the stack is not exceeded. In some computers,

a hardware monitoring of the stack pointer is available. Failing this,

the programmer should ensure that the stack pointer value never exceeds

certain predetermined limits corresponding to the top and bottom of the

stack in the main memory.

Operand Stack

The facility for storing data on the stack provides another location

for operands and can therefore be regarded as another method of operand

addressing. The advantage of using the stack for operand addressing

is that the program being executed may be interrupted, and the interrupting

device may then use the same program. The use of the stack as an

addressing mode in the shared program, rather than the use of absolute

main memory addresses, prevents data associated with the interrupted

60 Addressing Modes

program from being overwritten. The original data can be retrieved

from the stack when the interrupting device has finished. In this way,

the same program may be used by several different devices. This is

sometimes known as re-entrancy.

MIXED ADDRESSING MODES

In those computers using a 2-address or 3-address instruction word format,

it is usual to allow each of the operands to be specified in a different

way, i.e. different addressing modes may be used within the same instruction

word.

Therefore, the 6800 example used earlier

LDA A #23

uses mixed addressing modes. The destination operand field uses the

register (or accumulator) direct addressing mode, whilst the source

operand field uses the immediate mode.

Not all the addressing modes of a machine are necessarily available

with each operator in the instruction set. Sometimes, as in the case

of some special operators, the reason is obvious. In other cases it

may be simply a limitation of that machine.

5 Comparison of Devices: The Processor-Memory Switch

INTRODUCTION

The main components of a microcomputer system are shown in Fig. 5.1.

They comprise the mainframe and the peripherals. Whereas in the case

of a large computer system the mainframe is often first and the

peripherals are added later, to provide the necessary flow of information

between the processor and the user, now, in the case of a microcomputer

system, it is the peripheral equipment that usually exists first, as it

is the system to be controlled or measured or tested.

PROCESSOR k1- -N MEMORY

MAIN FRAME

\7\7 SWITCH

/± 4± V-j\n

INPUT/OUTPUT £EJ?IPHE_RALS |

SYSTEM

Fig.5.1 A microcomputer system

One must choose the mainframe to match the requirements of the total

system specification, which includes parameters such as data rate from

external transducers, crisis time for responding to critical situations,

as well as the details of the processing algorithm to be executed in a

mainframe.

61

62 Comparison of Devices : The Processor-Memory Switch

Certain features of the mainframe configurations, from the microprocessor

product ranges, can be identified as being significant when attempting to

choose the mainframe to meet the total system requirement.

Within the mainframe, there are three separate components (see Fig.5.1).

The processor is the component which executes the set of instructions.

The memory holds data and code, whilst the switch links processor,

memory, and peripheral equipment. There are three sets of routes through

the switch:

(a) Processor-memory

(b) Processor—input-output (special f ac i l i t i e s for data/command

transfer)

(c) Processor interrupt

The complexity of the switch component is determined to a large extent

by the limitation in the number of pins on an LSI processor package,

which ranges from 18 to 64 pins on the latest products. The same pin is

often required to pass different types of information at different times

in the processor cycle. Multiplexing circuitry is provided within the

processor, but it must also be provided externally in the switch or

memory, often by use of many extra logic circuits. As the use of the

microprocessor develops, the manufacturers are producing special LSI

circuits to serve in the switch role and reduce the package count.

THE PROCESSOR : MEMORY ROUTE THROUGH THE SWITCH

The route between processor and memory carries both memory address and

data, as shown in Fig. 5.2. It also carries control signals which are

not shown. The existence of these associated control signals will be

implied. The address must pass from processor to memory to select the

memory register involved in each transfer. However, a transfer is

either read data from memory or. write data to memory; thus these two

routes can be served by one bidirectional route, as shown in Fig. 5.3,

whicn halves the number of pins on the processor required for this

route. The products which exploit this technique are listed in Fig.

5.4.

Comparison of Devices : The Processor-Memory Switch 63

Fig.5.2 Processor-memory: basic routes

PROCESSOR

ADDRESS REGISTER

JSf

DATA REGISTER

^

SWITCH

Kr DATA

MEMORY

ADDRESS (DECODE MEMORY REGISTERS

3E 1—Nf DATA \-\A REGISTER

ΚΓ"

Fig.5.3 Processor-memory: bidirectional data route


PROCESSOR

8080

6 8 0 0

F 8

6 5 0 1 / 2

6 5 0 4

6 5 0 3 / 5

EA 9002

2 6 5 0

TMS 9900

*By te Add

WORD 'LENGTH

(b i ts )

8 8

8

8

8

8

8

8

16

ADDRESS LENGTH

(bits)

16 16

16

16

13

12

12

15

16

ressing allowed

MEMORY SIZE

(words)

64 K

64 K

64 K

64 K

8 K

4 K

4 K

32 K

32 K*

Fig.5.4 Processors: basic bidirectional data

PROCESSOR SWITCH

ADDRESS IN BANK

BANK NUMBER

REGISTER k N"

K DATA

N~

MEMORY

_s £ MEMORY

REGISTERS

L_T\r IE

DATA I / I REGISTER

K ΚΓ

Fig.5.5 Processor-memory: basic and bank switching

PROCESSOR

MK 5065

SCAMP

CDP 1801

WORD LENGTH

(b i ts )

8

8

8

ADDRESS LENGTH Bank Word

(b i ts ) (b i ts )

7 8

4 12

8 8

MEMORY SIZE Banks BankSize

(No.) (words)

128 256

16 4 K

256 256

Total

(words) 1

32 K

64 K

64 K

Fig.5.6 Processors: basic bidirectional data and bank switches


The number of processor pins to pass a large address can be reduced by

a technique known as 'bank switching'. The total memory space is

divided into a number of banks of equal size. The bank number is

represented by a set of bits at the most significant end of the address.

The bits of lower significance denote the location of a word within a

bank. The bank number is held in a register between processor and

memory, which may be loaded by the data path (Fig. 5.5). On each

processor-memory transfer, the least significant address digits are

provided over the address path, to address the word within the bank,

and are concatenated with the bank number to access the total memory.

Thus, after an initial bank switching process, when the bank number

register is set to a new value, each subsequent access to that bank

takes no extra processor cycles, and can operate in the same way as

those in the system shown in Fig. 5.3. The processors which exploit

some form of bank switching are shown in Fig. 5.6.

When the number of pins is at a premium, it is expedient to provide

one bidirectional route for both data and address, as shown in Fig.5.7.

To effect a transfer between processor and memory, the address must

first be set on the buffer, followed by a processor cycle to enable use

of the bidirectional route for the data to be made. In the case of the

16-bit processors shown in Fig. 5.8, two cycles are sufficient, but in

the case of the 8-bit processors, two cycles are necessary to establish

the address on the buffer before the data transfer can occur in a third

cycle.

PROCESSOR

ADDRESS REGISTER

TU v — ^

c

I v

DATA 1 REGISTER |

1 ' > I

A

E s & D R I v E R s

Fig.5.7 Processor-memory: single bidirectional route


\ PROCESSOR

Gl-1600

PACE

MPS-1600

CRD-8

8008

WORD LENGTH

(bits)

16 16

16

8

8

ADDRESS BUFFER LENGTH (bits)

16 16

16

16

14

MEMORY 1 SIZE

(words) 1

64 K

64 K

64 K

64 K

16 K |

Fig.5.8 Processors: one bidirectional route

Summary

The processors listed in Figs 5.4 and 5.6 are all capable of a maximum

transfer rate between processor and memory, limited by the time for one

processor cycle. The relatively successful performance of the 8-bit

processors 8080 and 6800 can be attributed to this feature. In the

case of the TMS 9900, a 16-bit processor in a massive 64-pin package,

this mode of operation is essential since its architecture is such that

all operations take place between registers held in memory and there are

no central operand registers within the processor.

In the case of processors shown in Fig. 5.4, it is possible to allow

a bus highway system directly from the ports on the processor to many

memory modules (Fig.5.9). All the other processors require circuitry

in the switch to generate a bus highway.

Fig.5.9 Bus highway system

In the case of the unidirectional address bus, the processor must

merely provide sufficient fan-out to drive the load. In addition,

when a bidirectional bus is involved, the port circuit must also

present a high impedance when it is not sending but acting as a


receiver or is passive. In some processors, the TTL open collector

output stage is employed, but for better definition of binary values

and more rapid response, the three-state driver is preferred.

Types of Memory Module

There are two classes of memory module that can be included within the

total addressable memory space:

(a) Conventional memory

(b) Image memory (for input^output devices)

Apart from the memory size, the next important factor to consider is the

time to access data. This is the time between the address being

established on the input address port and the instant the data is read

out of the array of memory registers and placed on the data register in

the memory module. Most processors will have allowed for a reasonable

access time within their internal timing, and it is usually possible to

match memory performance to demanded access time. However, memory with

longer access may be used, provided the processor has a facility which

enables it to pause within its internal timing to wait for the access to

take place. For example, in the case of the 8080, the processor will

enter a WAIT state if the memory does not respond within the required

time; it stays in the WAIT state until the correct response is received

from the memory.

Conventional Memory

The conventional memory is usually based upon a semiconductor LSI circuit.

There are two basic types:

(a) Read write memory (RWM)

(b) Read only memory (ROM) (PROM) (EAR0M)

The use of these within the addressable memory space is at the discretion

of the system designer.

Image Memory

Special facilities may be provided within a processor and its instruction

set for communicating through the switch to the input-output devices.

However, such special facilities are never (or hardly ever) essential.


The information to be communicated comprises the data, plus commands

from the processor and status signals, from the device. The data will

be stored, buffered, on a register within the device. The commands

received by the device must be held on flip-flops which can be assembled

into a register. The status signals produced within the device may also

be assembled to appear as a read only register. Such registers can be

located within the addressable memory space (Fig. 5.10). Transfer of

data from the processor requires a conventional MOVE order which passes

the data from a central register to the distant destination register

within the device. A command may be assembled in a central register

within the processor and passed to the device by a MOVE order. Data

may be transferred from the device to a processor central register, and

also the indicators in the device may be brought to a central register

in the processor, all by MOVE orders.

DATA FROM DEVICE

Fig.5.10 Image memory of input device

This technique was first used in the Atlas computer. All the various

registers, flip-flops, switches, etc., scattered amongst the peripheral

devices and the mainframe logic of this large computer system, were

assembled into a V-store, which was included within the main addressable

memory space. It is now customary to call such an arrangement an image

memory. The space contains images of all the various bits of information.


The access time to the image memory is dependent upon the device used

and its distance from the processor. If the processor does not contain

the pause capability mentioned above, then intermediate buffer registers

must be provided. In general, within the large addressable memory space,

it is possible to allocate many thousand locations to the image memory,

which should be sufficient to deal with most situations.

EXTRA PROCESSOR: INPUT-OUTPUT ROUTES THROUGH THE SWITCH

Though the image memory concept satisfies all the logical requirements

for the programmed control and transfer operations of the peripheral

devices, certain extra facilities are provided in microprocessor structures.

Extra Image Memory

In some systems, the address and data paths are intercepted before they

reach the memory, and routed to an extra image memory. In the case of the

8008, when an input^output instruction is obeyed, a special signal is

generated which permits five bits of the address to access an extra set

of 32 input-output ports; of these, eight are input ports and 24 are

output ports-all eight bits wide. A similar procedure is used in the

8080 in which eight bits of the address are routed to access an extra

set of 256 input and 256 output ports for special input-output instructions.

Extra Data Ports

As an alternative to using the existing address and data routes, it is

possible to provide additional ports direct into the processor. Since

pins are scarce, these are usually only one-bit wide, as in the 2650.

In the case of the TMS 9900, the single-bit input port and single-bit

output port are serviced by a process on the chip which enables automatic

serial to parallel conversion on input and parallel to serial conversion

on output. The multi-chip F8 system provides two 8-bit bidirectional

ports on each of the CPU and PSU chips. It is possible to have more

than one PSU chip.

Apparent Concurrency

Twenty years ago, when a computer was expensive, on account of labour-

intensive manufacturing, the time to execute a job was dominated by the

input and output of data whilst the processor was idle. Thus it became


necessary to introduce the concept of sharing a mainframe activity

between computation and the servicing of the input-output devices so

that both sets of activities appeared concurrent.

There are three ways of sharing a single mainframe between several

tasks:

(a) Polling

(b) Interrupt

(c) Direct memory access

Polling benefits if the several tasks are well defined and can be sub-

divided into clearly partitioned sub-tasks that can be completed in

sequence in such a way that the next sub-task can be one from any of

the several tasks. If one is less sure of the nature of all tasks, as

is the case when a large computer handles a varied mix of jobs, one can

divide the jobs into two sets: urgent, and non-urgent. The non-urgent

jobs are scheduled in some way, and each in turn is allowed to run to

completion, except that, from time to time, its progress will be

interrupted by one of the urgent jobs: interrupt and direct memory access

are in this class.

Concurrency by Polling

A timing diagram for a typical polling system is shown in Fig. 5.11(a).

In the example, there are three activities which can occur concurrently:

(a) The computation involving only the mainframe.

(b) Data transfer from the mainframe to an output device.

(c) Data transfer to the mainframe from an input device.

COMPUTATION Γ Α Π |~ΑΓ| |~ÀT| ["ÀT| |~ÀT|

OUTPUT

INPUT

ta !

m tb!

m (H il ©

te

t τ f

id ici id te)

TIME

Fig.5.11(a) Polling timing diagram

71 Comparison of Devices : The 'Processor-Memory Switch

INPUT REQUEST = 1

Fig.5.11(b) Polling program

It is assumed that the computation program can be partitioned into a

series of sub-sections, A0:A-:A? A -, and that the maximum time to n-1

execute each section does not exceed £ . The data transfer to the output a

device is performed by a program B which does not exceed t. and the data

transfer from an input device is performed by C in time less than t .

The time to execute the sequence A : B : C is less than T = t + t. + t .

It is in the nature of input-output devices that they are asynchronous

to the processor rhythm within the mainframe. Further, that the time

interval between requests for service T is yery long compared with the

time to obey an instruction; it must be indeed long compared to the

time T above. However, when a request arises, it must be serviced by

B or C within a crisis time, T , after which the data will be corrupted

or wrongly transmitted to the device. Thus, T must be less than T . Due

to the asynchronism and the long period, τ , between requests for service,

it is conceivable that the actions B and C may do nothing. As shown in

Fig. 5.11(b) the program for each of B and C must begin with a test to

determine whether a request is pending. If it is, the trnasfer takes

place (BT or CT), else an action (BI or CI) is entered, which does


nothing but waste time equal to the time taken by BT or CT. Thus, if

an input request arises whilst the CI action is taking place, the request

will have to wait until the next C period at time, approximately T later.

The sections B and C each use the processor and some of its central

registers. If these same registers are used by A, then at the end of

each sub-section, A., it is necessary to add a small program (DUMP) to

place the contents of these in the workspace for A before calling the

subroutine do B : C. On return from the subroutine to A.Ll these

registers must be restored to the values they held at the end of A. by

a small program (RES). This pedantic polling scheme may be modified

to allow BI and CI to approximate to zero, thus causing a rapid poll of

inactive requests and a return to A. There is less idle time.

In many microprocessor applications, where the task is mainly to pass

data with little computation, a polling scheme would seem to be adequate.

Devices with differing crisis times can be accommodated in the design

of the polling sequence.

Concurrency by Interrupt

In a typical interrupt scheme, the timing is similar to that shown in

Fig. 5.12(a). The background non-urgent computation tries to run all

the time (in many microprocessor applications this seems to be an idling

loop). When an urgent request for service by a device occurs, the

background job is suspended and the interrupt process is executed. At

the program level, this is equivalent to inserting the following

selection clause after each order:

if interrupt request

do interrupt process

else continue.

This is too cumbersome for the programmer, so special circuitry is employed

in the processor to execute a similar selection clause after each

instruction is obeyed. The test is carried out upon a special interrupt

signal brought into the processor from the devices. If the interrupt is

present, an interrupt routine is entered and obeyed as if it were a

conventional routine. Ideally, the interrupt routine would use a program

counter and central registers different from those used by the interrupted

program (cf. MK 5065) and protected from corruption by other programs.

It is normally the case that the first action of the interrupt routine

Comparison of Devices : The Processor-Memory Switch 73

COMPUTATION | A |

DEVICEo

< ROUTINE IR0

DEVICEi IMTpppi IDT

ROUTINE IR,

CNABLC INTERRUPT

Π

"ÏRÔ"

1 _

A | -

h HRÖI

1 ! I i

c

1 LJL

1

1

IRi 1

Ξ

Π '< 1

"ÎR01 ;

—jg

1_T~

- - Γ Χ Ί

n TRT

1 1

PRIORITY RANKING 1. DEVICE 0 2. DEVICE 1

Fig.5.12(a) Interrupt timing diagram

is to dump all central registers (the state vector) into a reserved part

of memory before it proceeds to service the request. The state vector

is restored before returning to the interrupted routine. During the

interrupt routine, it is normal to disable the interrupt signal in the

processor so that all other interrupting devices are ignored. Thus,

before leaving the interrupt routine, the interrupt signal must be

enabled.

If several devices are classed as urgent and allowed to interrupt, they

must be ranked in order of priority. Usually, all the interrupt signals

will be ORed together, externally, to produce a single interrupt input

to the processor. In this case, the second task of the interrupt routine

is to find the interrupt of highest priority and service it first.

Each device may require a different interrupt routine IR.. A device

of low priority may require a long interrupt routine, much longer than

the crisis time of a higher priority device. If this is the case, the

long interrupt routine should enable the interrupt early, so that higher

priority devices may interrupt it, as if it were a normal routine (see

Fig. 5.12(a). In large systems with many levels of interrupting device,

it is possible to imagine a situation where the main computation and

several interrupt routines are nested in suspension under an active

interrupt routine servicing the device of highest priority.


The actual routine which services the device is embedded in the house-

keeping routines shown in Fig. 5.12(b). These overheads can take up

considerable code and can add a significant amount to the time taken in

servicing each interrupt. Certain processor specifications include

features to reduce these overheads. Some of these features are also

contained in special LSI circuits to interface peripheral devices to

the bus highways.

END OF LAST INSTRUCTION

^_0 X > INTERRUPT SIGNAL = 1

DUMP I STATE VECTOR|

I DISABLE I | INTERRUPT I

CONVERT PRIORITY INTERRUPT INTO

NUMBER I

BEGIN NEXT INSTRUCTION

Fig.5.12(b) Interrupt sequence

Direct Memory Access

With certain types of peripheral device, the peak demanded transfer rate

is too high to be managed by obeying a program in the processor. In this

r4>


situation, it is necessary for the peripheral device to have direct

access to the main memory on demand. A controller is provided (DMA

controller: Fig.5.9) which is able to generate addresses for the data

transferred between device and main memory. The controller steals

memory cycles from the processor by sending a control signal, which

forces the processor to HALT as soon as possible, and forces its address

and data ports to the high impedance state to permit the DMA controller

to use the bus highway. When the DMA controller has finished with the

bus highways, it releases the processor from the HALT state and allows

it to proceed with its next action.

Before the DMA is allowed this priveleged access, a process in the

mainframe must set up initial conditions in the controller which ensure

that the data to be transferred into the main memory will not corrupt

information being used concurrently by the main process.

Comments on Polling and Interrupt

The polling system can be employed by using the memory and input/output

facilities discussed above. If the system specification is bounded and

explicit, then it should be possible to devise a program structure

similar to that in Fig. 5.11(b) which will serve. The development and

testing of such a system should be relatively straightforward since the

sequence is well ordered.

There is a strong temptation to use the interrupt facilities provided

by the various processors. In systems with a high diversity in the

activity of the various external devices, the pedantry of the polling

system may seem wasteful of surplus processor power. However, if all

devices are active most of the time, the various levels of nesting which

could occur in an interrupt system may cause problems during development

and testing.

In the polling system, the problem is treated as one large program.

The main computation and separate device-handling routines may be written

separately but they must eventually be merged into one. In the case of

an interrupt system it can be argued that the separate routines may be

treated as independent of each other, and the interrupt mechanism is

transparent to the programmer of each routine. This is dangerous, since

without automatic protection or dynamic store location facilities, there

is a chance that a routine will corrupt others. The probability of

indeterminancy and deadlock is increased.


The designers of operating systems for large time-shared computer

systems have been living with such problems for nearly twenty years.

Microprocessor users should build on this experience and proceed with

caution.

Synchronization

All methods of servicing input-output devices meet a situation in which

the asynchronous request for service from the device must be synchronized

to the basic rhythm of the processor. When the asynchronous request

signal is clocked into a flip-flop, there is a probability that it will

be changing from a zero to a '1' whilst the clock signal is changing.

Such an event might, or might not, succeed in setting the flip-flop. In

either event, the flip-flop will take a time to settle that is longer

than normal, and can be yery long indeed. By increasing the time allowed

for settling, it is possible to reduce the probability of failure. It is

not possible to make such a system 100% reliable.

SUMMARY

There are many ways in which the processor-memory-switch structure has

been arranged. The most elegant is that shown in Fig. 5.6, which allows

a bus highway system and the attachment of a wide range of modules for

both memory and input-output devices.

In small systems, and for certain peripherals, the special ports may

be used to advantage.

Though concurrent activities can be handled by polling, extra interrupt

facilities are provided. These facilities seem to offer a new degree of

freedom to the system designer. This freedom hides many dangers familiar

to designers of large operating systems, but as yet uncharted by the

microprocessor user.

Since the price of a processor is so low, one wonders whether it would

be better to devise a system in which many processes are active

concurrently in many processors.

6 Comparison of Devices: The Instruction Set

INTRODUCTION

There are many factors which must be taken into consideration before

choosing a microprocessor as a component in a digital system. The obvious

factors which influence the choice of logic circuit family still apply.

These include: the number of voltage supplies and the voltage value and

current drain of each supply; overall power dissipation and temperature

operating range; representation of binary values at the input/output

ports and compatibility with an existing logic circuit family; timing

requirements of the various data and control signals.

At the other extreme, one should consider the support systems for

program development. The existence of high-level assembly language with

cross-compilers and assemblers; emulation of the microprocessor on a

minicomputer, either with a one-to-one time relationship or a simulator

running at a different rate from that of the microprocessor; a micro-

computer or 'debugger' based on the microprocessor, to develop prototype

hardware/software systems.

In between these two extremes are a whole set of factors which determine

whether or not the microprocessor can execute the task for which it is

intended in a manner which meets the real time constraints by means of

efficient well-structured programs and straightforward reliable logic

circuits at the interface between the microprocessor and the rest of the

system.

WORD LENGTH

At first glance, the word length of the processor directly affects the

range of numbers that can be represented, the number of binary variables

that may be manipulated at one time in parallel, and the number of states

that can be represented (Fig. 6.1).

Hence, the information content which can be processed in a single

order is directly related to the word length.

77

78 Comparison of Devices : The Instruction Set

WORD LENGTH :

NUMBER Ï 0

RANGE i or - 2 n _ 1

NUMBER OF BINARY VARIABLES :

NUMBER OF STATES

_

n

+(2n-l)

+2η"Ί-1

n

2n

8

0 255

-128 +127

8

256

Fig.6.1 Word length features

The word length of the memory should equal the word length of the

processor. The usual concept of a computer is that operands and

instructions are both capable of being held in the same memory. Thus,

the word length has a direct effect upon the size of the instruction.

The instruction length is equal either to the word length or multiples

thereof.

ORDER CODE

The power of the order code is measured in terms of the number and type

of functions or operators which the processor can perform, and also the

number and type of addressing modes which are possible.

As each order is obeyed, the processor needs to identify the location

of the operands Ζ,Χ,Υ and the type of operator b in the equation:

Z ^ - X b Y

Also, the processor must identify the location of the next instruction.

The identification data needs to be either explicitly stated in the

instruction or implied in the design of the processor.

In general, the number of bits required to identify Ζ,Χ,Υ and the

address of the next instruction could, in each case, be equal to log2 m

where m = number of words in the memory. For example, if the memory

size m = 64 K words and log2 64 K = 16, then 16 bits would be required

for each,giving a total of 64 bits in the instruction.

This is too cumbersome, and since there is a high level of redundancy

in this data, steps can be taken to restrict the meaning of the equation

Z «- X b Y and place restrictions on the location of the next instruction.


Step 1 Program Counter (PC)

The location of the next instruction is usually a fixed distance from

the location of the present instruction. Therefore it is usual to

incorporate a program counter to perform NI «- (PC) + 1 as each word of

the instruction is read from memory, where NI is the location of the

next instruction.

Step 2 Two Types of Instruction

Type 1: Program Control D In this type of order, an alternative

location for the next instruction is provided to be used in place of

NI=(PC) + 1 produced by the program counter. This alternative may be

used unconditionally or as a condition of certain flag bits being set

or unset.

Type 2: Operation Statements D In this type of order, the next

instruction is at PC + 1 and the instruction specifies the operands and

operators (Fig. 6.2).

Key: St

b

A

Three Address

Two Address

One Address

also

Zero Address

Operand at top

- binary operator

Z - X b Y

X +X b Y

(A)«-X b(A)

X «-(A)u, (A) «-Xu

X «- Xu

(A)-(A)u

(A)*-(A) b st

of stack

u - unary operator

- Implied General Register (Accumulator) J

Fig.6.2 Summary of operation statements

OPERATION STATEMENTS

The operation statements form the major part of the instruction set

of the processor, and will be dealt with first.

In considering the operation statements, it is convenient to divide

them into their component parts of operands (Z, X, Y, A, st), and


operators (b,u).

The convention of placing the register designation in parenthesis, (A),

is used to denote that the operand value is to be located at the designated

register, A.

Operand Addressing

Literal/Immediate □ That section, or field, of the instruction that

describes an operand may represent the value of an operand.

In the case of a multi-byte instruction, the first byte may contain the

definition of the type of instruction and the operator, whilst the second

byte comprises a bit pattern which represents the value of an 8-bit

operand; or the second and third bytes may be concatenated to represent

the value of a 16-bit operand.

The literal meaning of the bit pattern is the value of the operand; the

bit pattern follows immediately behind the instruction word. Single-word

immediate operands will be designated by n, whilst double word immediate

operands will be designated by m. (An immediate operand that is part of

a single-word instruction is designated g.)

General Register - Direct -G(g) D That section, or field, of an

instruction which describes an operand may represent the location of the

value of an operand in an array of general registers on the processor

chip. The location of a register in the array is designated g (i.e. g

is part of a single instruction word). The array is designated by G.

8008 : There is an array of seven general registers in the

processor chip. An address field, three bits within

the instruction word, permits the location of an operand

in one of up to seven general registers : the eighth code

designates a memory operand (See Fig. 2.4(a)).

8008 : Direct register addressing-move

ISP* Code/Mnemonic Operation

(D) +- (S) ] U D ~"S~] Move the contents of S to D.

G(A) +- G(B) 1 Mov A B ] Move the contents of general register B to general

_____________- register A ΓΊ1 000 OOlt

Instruction set processor language; see Bell and Newel! (1971)


All the subsequent examples will have the same layout as above3 and

ISP3 Code/mnemonic3 description is omitted for clarity»

Main Memory - Direct M(g)3 M(n)3 M(m) D That section, or field, of

an instruction which describes an operand may represent the location of

the value of an operand in the main memory external to the processor

chip, M(g) M(n) M(m).

The size of the main memory demands that the immediate word n or

immediate word pair m are required to provide the necessary addressing

capability. M(g) usually provides a limited addressing field.

6800 : Direct Extended Addressing-move

G(A) + M(m) 266

m

M[0:177777o]<0:7> o

6800 : Direct Normal Addressing-move

M(m)

Move to general register A the contents of line m within the main memory M of size 2 t 16 - 64 K bytes.

G(A) 226

n

Move to general register A the contents of line n within the first 256 bytes of main memory. M[0:377o]<0:7>

o

Main Memory—Indirect M(G(g)) D That section, or field, of an

instruction which describes an operand may represent the location in

the general registers, G, of the address which represents the location

in the main memory, M, of the operand.

8008 (HL) - M[0:37777g]<0:7>

8080 (HL) - M[0:177777g]<0:7>

8008 : Indirect Addressing-move

Move contents of the memory location addressed by (HL) to register C.

G(C) ' " "

(S)

(G(E1 rJ) 1

U

Mov

1n

D S

C (HL)

010 111

Main Memory—Indirect Indexed M(G(IX) + n) D That section,or field,

of an instruction which describes an operand may represent the number to

be added to the contents of a general register or pair of general registers

acting as an index register.


The sum so formed to be used as the address of the location of the

operand in main memory.

6800 : Index Addressing-move

G(B) «- M(G(IX)+n)

IX <0:15>

346 n

Move contents of the memory location addressed by (IX)+n to register B,

Summary of Explicit Operands

The explicit operands described above are summarized in Fig. 6.3.

Immediate

Di rect

Indirect

Indexed

Part of Instruction word

9

G(g) M(g)

M(G(g))

M(G(IX) + 1)

Immediate word

n

M(n)

M(M(n))

M(G(IX) + n)

Immediate word pair

m

M (m)

M(M(m))

M(G(IX) + m)

The following abbreviations are used in the comparison tables :

Γ7 Mn

Mm

"v

- G(g)

- M(n)

- M(m)

- M(G(IX) + 1)

M g

n

m

, M(G(IX)

M(g) 1

M(M(n))

M(M(m))

+ n ) , M(G(IX) + m)

Fig.6.3 Summary of explicit operands

Implied Operands

Implied Accumulator-^. D The instruction may imply that one of the

operands is contained in the general register designated A or accumulator

8008 : Implied Accumulator—subtract

(A) «- (A) - M(G(ED) | SUB (HETI Subtract from A the -jTj—QjTj—««- I contents of the location

1 addressed by (HL)

Stack-st: The instruction may imply that the operand is

located at the top of a stack (LIFO). (LIFO = Last in First Out)


8080 : Stack-move

M((SP) - 1) + G(B) 11 000 101

M((SP) - 2) + G(C)

(SP) + (SP) -2

11 BC ÏÏÏT

Move (push) contents of register pair BC to the stack.

Operators

Operators are of two types: binary

unary

Typical binary operators are ADD,

typical unary operators are MOVE,

b Z + XbY u Z «- Xu

SUBRACT, whilst

DECREMENT.

PROGRAM CONTROL

Jump Instructions

The forcing of the program counter (PC) to a value different from the

implied (PC) + 1 is achieved by orders such as JUMP. The jump may be

absolute or relative to (PC)

Absolute (PC) «- S, Relative (PC) + (PC) + S

S may be designed in the same way as any one of the previous operand

designation schemes, n> m, G , M 3 M Λ M , M . 9 9 n m v

The jump may be unconditional,

8080 : Jump immediate

(PC) «- m

8080 : Jump indirect

(PC) + G(HL)

303

m

Jump to location m in main memory.

351 Jump to the location in main memory whose address is in the register pair (EL)

or conditional

8080 Jump conditional immediate

if parity odd

then (PC) + m

else (PC) + (PC) + 3

342 Jump location m if parity oddj otherwise continue from (PC) + 3.


6800 : Jump conditional relative

if overflow

then (PC) «- (PC) + n+2

else (PC) «- (PC) + 2

Jump to Subroutine and Return

051 n

Jump location (PC)-hn+2 if overflow set, otherwise continue from (PC) + 2.

On making a jump to a subroutine, it is necessary to preserve the present

value of the PC on the stack so that, on returning from the subroutine,

the next instruction of the calling program can be found automatically.

Methods of designating the starting address of the subroutine are

similar to those outlined in the case of JUMP and the call may be

conditional or unconditional.

The return instruction causes the stored address to be loaded into the

program counter, and so does not require an address. The return may be

conditional or unconditional.

STACK MANIPULATION

Special orders may be provided to permit manipulation of the stack pointer.

Orders to LOAD, STORE, INCREMENT, and DECREMENT are common.

COMPARISON TABLES

The comparison method presented here is based on a tabular description of

the instruction set information. The tables contain:

Operation orders

Program control orders

Stack manipulation orders

Each table has an operand dimension and an operator dimension. Each

operand/operator pair is represented by a square on the matrix; a mark

in the square indicates that the instruction is present in the processor's

instruction set. A large cross in the square means the operand/operator

pair is impossible.

Operator Orders

The operator orders are divided into unary and binary groups; the operands

into two, one, and zero address groups. The combinations of operands shown

represent the likely pairs found in microprocessors, and is not an

exhaustive list.

BIN

AR

Y

D—

DbS

UN

AR

Y

D^

uS

8080

80

00

OP

ER

AT

OR

D

S

+ ♦ c - -b &

Φ

OR

C

OM

P

MO

V

LO

AD

(P

US

H)

ST

OR

E (

PO

P)

DEC

IN

C

RO

TR

(L)

RO

TR

RO

TL

(L)

RO

TL

EX

CH

C

OM

PL

DE

C

AD

J C

OM

C

RY

S

ET

C

RY

TW

O

AD

DR

ES

S

D-

DIR

EC

T

G

3 Tl

1

n I

m

3

M„

Mm

5

MG

! M.

2

M«

G

Mo

M-

G

5

MG

D-

IND

IRE

CT

M

G

n

G" '

1 J

M„

M^

M,

M.

G

Mo

ON

E

AD

DR

ES

S

UN

AR

Y

G|M

n|M

rr|M

G

G

M„

Mm

|M&

Mv

M,

1.3

1,3

D-I

MP

LIE

D

A

n 1 1 1 1 1 1 L

1

G

M„

Mm

M&

_jl

M,

1

i t [

1 1

St

n

G

M„

1 1 j ; "j

M.

Mo

M,

_4 .

i..

—

I4 H4 1 i

i ! i

! 1

iiL·

—t ■

-J

1

ZE

RO

A

DD

RE

SS

A

A

, S

t

St

St

1 i i!

i 1 1 1 -

H—

A

i -

8080

Co

de

De

sc

ri

pti

on

DE ,

HL

<0

:15

>

A,B

,C,D

,E,H

,L

<0

:7>

BC ,

DE

, H

L ,

SP

<0

:15

>

BC ,

DE

, H

L ,

AF

<

0:

15>

HL

< 0

:15

>

imm

ed

iate

b

yte

<

0:7

>

imm

ed

iate

b

yte

p

air

<

0 :1

5>

M(m

) -

M[0

:17

77

77

g]

<0

:7>

M(H

L)

- M

[0:1

77

77

7g

] <

0:7

>

M(B

C)

or

M(D

E)

- M

[0:1

77

77

7g

] <

0:7

>

M(S

P)

- B

yte

p

air

a

t to

p o

f s

tac

k

in

M[0

:17

77

77

g]

<0

:7>

Sym

bo

l

2

Cod

e

G ,

G'

MG

De

scri

pti

on

A,B

,C,D

,E,H

,L

<0

:7>

M(H

/L)-

M

[0:3

77

77

8]

<0

:7>

imm

ed

iate

b

yte

<

0 :7

>

Sym

bo

l

Fig

.6.4

O

pera

nd c

ha

rt

for

8008

, 80

80

00

BIN

AR

Y

D—

Db

S

6810

^

OP

ER

AT

OR

D

S

♦ ♦ c - -b &

Φ

OR

C

OM

P

MO

V

LO

AD

(P

US

H)

ST

OR

E (

PO

P)

DEC

IN

C

RO

TR

(L)

RO

TR

R

OT

L(L

)

RO

TL

BIT

T

ST

D

EC

A

DJ

CLR

N

EG

S

HIF

T

CO

MP

L

SE

T

CY

.OF

L

CL

R

CY

.OF

L

TW

O

AD

DR

ES

S

D-

DIR

EC

T

G

G' 1 1 1 1

n

'.x 1.2

m M

„ V

12 M

m

Ί*

1.2

MG

M, \*

1.2

SP

IX

1 1

1 1

M«

ek

1.2

Mm

G

1.2 M

o

D-

IND

IRE

CT

M

G

n

G" M

n M

JM,

M.

G k

1.2

ON

E

AD

DR

ES

S

UN

AR

Y

G|M

n|M

niM

G)M

. G

M„

Mm

Moi

M.

1.2

1.2

D-I

MP

LIE

D

A

n

G M

n M

m M

G M

.

xxxx

xx

3 3

St

n

G M

n

1

M„

Mo

M,

xxxx

xx

V

X 1

ZE

RO

A

DD

RE

SS

| A

A

St

1

St

| S

t A

Cod

e D

escr

ipti

on

G .

G':

A

,B

<0

:7>

IX

, SP

<0

:15

>

F

<0

:15

>

n

: im

me

dia

te

<0

:7>

m

: im

me

dia

te

by

te

pa

ir

<0

:15

>

Sym

bol

M(n

)-

M[0

:37

78]

<0

:7>

M(m

)-

M[0

:17

77

77

g]

<0

:7>

[(IX

)+n

] -

M[0

:17

77

77

8]

<0

:7>

Fig

.6.5

O

pera

nd c

har

t fo

r 68

00

Comparison of Devices : The Instruction Set 87

Register groupings and additional data are presented next to the table.

The 8080 and 8008 orders are shown on one table, the latter being

indicated by an underlined symbol in the square (Fig. 6.4). The 6800

orders are shown in Fig. 6.5.

Program Control and Stack Manipulation Orders

The address information is split into absolute and relative groups for

the control orders. The return instruction is presented in its own

sub-table.

The stack pointer is the destination register, and the normal range

of source operands is provided.

Special notes list the condition flags and addressing range, etc.

The 8080 and 8008 orders are shown on one table, the latter being

indicated by an underlined symbol in the square (Fig. 6.6). The 6800

orders are shown in Fig. 6.7.

D

K

J

JC

c cc

PC ABSOLUTE

9

0

n m

Q 0

0

0

G» 0

M„ M* Mv

PC RELATIVE

9 n m G, M„ Mm M«

R

RC

St ] 0

Q

D«-uS

S«-SbD S-D*1 D«-S-1

1

D

S

LOAD

STORE

INC

DEC

ADD

TRANS

TRANS

SP

9

X

n

X

m

0

X

Gg

0

0

Mn Mm Mv U

0

0

8080 Code

g

CON

ST

PC

Descr ip t ion

immediate word p a i r <0:15>

G(H/L) <0:15>

C , S , Z , P <0> 1 or 0

M[0 :177777 8] <0:7>

<0:15>

8008 Code Description

m : immediate word pair <0:15>

CON : C , Z , S , P <0> 1 or 0

ST : ST[0:7] <0:13>

PC :<0:13>

Fig.6.6 Control chart for 8008, 8080


D K J

JC

c cc

PC ABSOLUTE g n m

0

0

Gg Mn Mm Mv

0

0

PC RELATIVE 9 n

0

0

0

m G» Mn Mm My

R RC

St 0

D S

LOAD STORE

INC DEC ADD

TRANS TRANS

SP g

X

n

X

m

0

X

Gg

0

0

Mn

0

0

Mm

0

0

M,

0

0

U

0

0

0800 Code * Description

n : immediate word <0:7> signed no.

CON: C , Z , S , OVFL , LZ , GZ , HI <0> 0 or 1

m : immediate word pair <0:15>

Mv : M ((IX) + nj - M[0 :1 77777g] < 0 : 7>

Mn : M(n) - M[0:377g] <0:7>

Mm : M(m) - M[0:177777g] <0:7>

Fig.6.7 Control chart for 6800

7 Support Software

INTRODUCTION

With the advent of microprocessors, the hardware cost of producing a

computer system has fallen. The software cost, however, has not fallen;

indeed in a number of cases it has risen because of the lack of

programmer aids on the microprocessors currently available. To

encourage and widen the use of microprocessors, some simple programming

aids are required which will help to reduce the software cost of the

system. Since, at the moment, it would appear that the main use of

microprocessors is in small dedicated systems, the software for such

systems needs to be developed and tested on a larger computer, since

the dedicated system will almost certainly not provide the facilities

required for software development. This gives rise to the concept of

cross-translators which are run on another machine to produce output

which can be loaded into the target microprocessor system. This also

creates the need for simulators to simulate the action of the micro-

processor on another computer, so that the software can be tested and

debugged before being loaded into the microprocessor system.

The question of what languages to use to develop software for micro-

processors is a difficult one to answer. For very simple systems, which

most of the applications to date fall into, assembly code may well

suffice, but for the more complicated systems which will undoubtedly

emerge over the next few years, a higher-level language is desirable, if

not essential. This is so because of the lack of suitably skilled

programmers and the need to force standardization on a group of programmers

working on parts of one large project. Another related problem is that

of program design for these large projects, and although this has been

faced by the major computer users at present, it will have to gradually

extend to the software designer of microprocessor systems. This design

problem will be magnified greatly with the advent of multiprocessor

systems, as although the hardware costs may be relatively small, the

software complications increase by at least an order of magnitude.

Before considering specific software aids for microprocessors, it is

worth-while reviewing tfi£ lessons learnt by the mainframe computer

89

90 Support Software

manufacturers over the past twenty years. From a software viewpoint

there is little difference between a microprocessor and a mainframe

processor apart from the complexity of the instruction set. This

difference may disappear in the future. The mainframe manufacturers

have learnt the solutions to several problems by experience over a

number of years and there is a danger that the users of microprocessors

will fall into th'e same traps. Three main points which are now widely

accepted by the mainframe manufacturers and which are pertinent to

microprocessor systems are:

(a) Software costs are high.

(b) System software should be written in a high-level

language wherever possible.

(c) Systems should be written with portability in mind.

In the case of microprocessors the software costs will be an even higher

proportion of the total system costs, since the hardware is relatively

cheap. This means that the software costs of most systems will be the

main cost. The problem of high-level languages is described elsewhere

in this chapter. In the case of mainframe manufacturers, it has been

found easier to maintain their systems software and get better productivity

from their programmers by using this approach.

The costs of transporting software from one system to another are

usually high unless prior thought has been given to this problem. This

is especially relevant to microprocessors, since the hardware is changing

so rapidly that there is no guarantee that any particular hardware will

be available for the life of a project; thus all programs will need to

be rewritten for the new hardware if they are not portable.

ASSEMBLERS

An assembly language is one in which there is normally a small ratio,

frequently 1:1, between statements in the language and machine code

instructions. The translator which translates from assembly code to

machine code, the assembler, is therefore comparatively simple to

produce. Assembly code is a mnemonic form of machine code, and

is a low-level language because the programmer needs to know details of

the hardware of the processor on which the instructions are to be executed.

The programmer is able to utilize the special features of the processor,

but this means that the programmer has to be experienced and competent to

91 Support Software

produce an efficient program. The chances of producing an error-free

program decrease exponentially with the length and complexity of the

program: so assembly code is not suitable for use in producing large

programs, especially with inexperienced programmers. Typical figures

for debugged code production are 5 instructions/programmer day for

assembly code and up to 100 instructions/programmer day for a high-level

language.

Until recently it has not been feasible to run an assembler efficiently

on a microprocessor system, since the process of translation requires

a high-speed input-output device and a medium to keep the intermediate

code for several passes of the translator, e.g. a disc pack, together

with a reasonable amount of memory, e.g. 8 K. If these facilities are

not available on the microprocessor system, another larger computer is

used and a cross-assembler produced for this computer which produces

code to run on the microprocessor system.

An assembly code instruction normally consists of an operation code

(opcode) and possibly some address fields (operands). The number of

address fields depends on the instruction

e.g. HLT the halt instruction requires no address fields

LAI 1 this instruction requires one address field.

The address fields may usually be expressions with the operators

allowed dependent on the complexity of the hardware. For example,

multiply and divide would normally only be allowed on processors with

that hardware capability.

All assemblers allow a label to be attached to an instruction or a

data item so that reference may be made to that item symbolically from

elsewhere in the program. The label will be separated from the rest

of the instruction by a delimiter. The exact form of the delimiter

depends on the details of the particular assembler being used. Some

assemblers, based on paper tape or teletype input, accept free format

input in which the various fields are separated by delimiters, while

card-based ones tend to use a fixed field format with particular fields

having to occupy particular card positions.

All assemblers allow the programmer to intersperse assembly directives

or pseudo-operations with the code to be translated. These assembly

directives allow the programmer to control the operation of the assembler.

Two of the most common pseudo-operations are those to tell the assembler

the start address of the assembled code and to tell the assembler that

92 Support Software

the end of the code to be assembled has been reached. In the assembly

code for the 8008 used in this book these directives are ORG and END.

Neither of these directives generates any code; they just control the

assembler. Other types of assembler directives do generate code. One

example is the DEF directive which loads the values of the following

expressions, separated by commas, into the next bytes in the code output.

A DEF directive would normally be labelled so that its associated data

could be referred to symbolically in the program. Also a facility is

usually provided to allow the user to associate a symbol with a value.

This operation on the 8008 is the EQU directive which allows the user

to define a symbol and give it a particular value.

There are frequently many more facilities associated with a particular

assembler, and some assemblers even allow macro facilities as described

later in this chapter. The facilities described here are the basic ones

which will be found in all assemblers, as can be seen in the examples

elsewhere in this book. More details may be found in the reference

(Barron (1969)).

There has to be some method of transferring the cross-assembler output

to the microprocessor system. Many systems use ROM to store the program;

so the output from the cross-assembler has to be in a form to feed into

a PROM programmer whilst other systems may require the program in RAM.

In the latter case, a loader is required to input the machine code either

through a machine-machine link or by the use of some medium such as paper

tape.

SIMULATORS

In order to test whether the program produced is correct, fairly extensive

tests have to be carried out. By the use of a simulator on a larger

computer, this process of testing and debugging can be speeded up because

of the superior facilities available on the larger machine. Essentially,

the simulator works by simulating the hardware action of the microprocessor

system in software on the larger computer. In effect, the microprocessor

code is interpreted on the larger machine. Because of this it is easy to

add features to the simulator which the real microprocessor does not have

to make program testing easier, e.g. explicit error messages, ability to

monitor complete state of the machine, traps for illegal conditions.

Support Software 93

LANGUAGES

The advantages and disadvantages of using assembly code have already

been stated. In many cases, the disadvantages outweigh the advantages,

and it is then better to use a high-level language, i.e. one that is

further away from the machine architecture, as there are a number of

extra benefits which accrue from the use of these languages. Since they

are effectively machine independent, a change from one microprocessor

to another just means that a new translator is required to translate to

the new machine code, and if a cross-translator, usually a cross-compiler,

is being used, this only necessitates a change in the code production

section of the translator. In fact, in using a high-level language, a

cross-translator will be almost a necessity, since it will require greater

machine support facilities than an assembler. One major drawback of

high-level languages is that they do not, in general, produce programs as

efficient as those hand-generated by a competent assembly-code programmer,

but in many situations this is outweighed by their advantages.

There are two types of translator which are especially relevant to

microprocessors: macroprocessors and interpreters. A macroprocessor is

a textual replacement system which pattern matches each input record with

a set of predefined templates, each of which is associated with a set of

output records (see Fig. 7.1). When the macroprocessor finds a match

Fig. 7.1 Macroprocessor

between an input record and a template it substitutes the set of output

records associated with the template for the input record. If the input

record is not matched it is left unaltered. The macro definition consists

of the templates and their associated output records. The following

example shows the use of a macroprocessor.

Input text Output text

ORB ORB

SWAP A,B,C MOV A,C

MOV B,A

MOV C,B

The instruction ORB is passed straight from the input to output since

it does not pattern match any template. The next record matches the

template line and substitutes A for 'Χ,Β for *Y and C for 'Z. The output

records are then inserted into the output with the substitution performed,

hence giving the output text shown. By means such as these it is possible

to build up a simple but effective translator to translate from one

language to another, normally at a lower level. In the above example,

the output text could then have been fed into an assembler to produce

the machine code required. In order to use this system all that is

required is a set of macro definitions. These are normally relatively

easy to produce and, if the output text has to be changed, e.g. for

different hardware, then only the macro definitions have to be changed;

a relatively simple task. A general purpose macroprocessor is normally

available on any large computer. Only the basic principles of macro-

processing are explained here and it is suggested that any interested

reader should consult the references given for more detailed information,

(Brown(1975), Campbell-Kelly (1973)).

An interpreter is very similar to the simulator described earlier. A

language is equivalent to a processor definition and vice versa. For

example, a definition of a machine code language defines the hardware

which 'understands1 it and vice versa. Hence if we have any language

we can regard it as the machine code for some particular hardware (which

may, of course,not exist). To realize a language on some particular

hardware there are two choices; either the language must be translated

into the machine code for the given hardware or the hardware has to be

made to 'understand' the language (see Fig. 7.2). This may be done by

some software, an interpreter, which resides in the hardware and makes

the system now accept the language as its machine code.

94 Support Software

A typical macro definition

Template MACRO SWAP 'Χ, Ύ , 'Z

f MOV 'Χ, 'Ζ Output \ MOV

MOV 'Ζ, Ύ records M0V 'Y' 'X

ENDMACRO

Support Software 95

Translator

LANGUAGE [ ] HARDWARE

Fig.7.2 Relation between interpreter and translator

The disadvantage of this technique is that there is a program

permanently resident in the microprocessor which uses memory space and

slows the hardware because of the interpretation approach. The advantage

is that is is relatively easy to write an interpreter and hence existing

programs may be run on new hardware simply by producing a new interpreter.

The feature of both the types of translator described above is that

they are relatively simple to produce and they both lend themselves to

software portability. The high-level language approach gives a high

degree of machine independence, so that the software and hardware can be

developed in parallel. It also allows major changes in the hardware of

the system to have minimal effect on the software.

PROGRAM DESIGN

As the complexity of computer systems increase, there is a need for more

and more formal design and program structuring methods. This has been

noted, and action taken by the large computer manufacturers; it will

become more and more important with microprocessor systems as their

complexity increases. As the hardware cost of microprocessor systems

is relatively small, there will be situations where the cheapest way to

produce a system with more computing power will be to add more processors

to the system. There are relatively few multiprocessor systems in

operation, and the software design methods to produce such systems,

whilst known in some detail, are still the subject of a great deal of

research. It will take some time to produce formal design methods for

these systems, and so at the present it is difficult to produce

satisfactory dedicated multiprocessor computer systems.

CONCLUSION

There are two major questions concerning software for microprocessors.

96 Support Software

Firstly, what software is required to produce software for a micro-

processor system? A cross-assembler running on a larger computer,

together with a simulator and a loader for the microprocessor system,

are the basic requirements of the software support. It is also very

desirable to have a high-level language available to write most of the

larger production programs so that they can be easily transferred to a

new hardware system. Perhaps it should be mentioned here that the

current trend appears to be for the language translators for the micro-

processor to be provided by the manufacturer on a microprocessor

development system comprising a general purpose computer system based

on the relevant microprocessor. The software can then be developed

and tested on this system and then transferred to the production micro-

processor system. This trend seems to have emerged since the micro-

processor manufacturer wishes to sell more hardware and some users do

not have access to other general purpose computers.

Secondly, how will this software be affected by further hardware

innovations? The software will be helped more by the hardware in

microprocessors in the future, but the situation at present is that

hardware technology is far ahead of software technology. The best way

of using the current hardware technology is not known, and it is likely

that this will be the situation for a number of years to come.

Finally, the lessons learnt by the mainframe manufacturers in producing

software should not be forgotten, so that the same mistakes are not made

for microprocessors.

8 Structured Programming

INTRODUCTION

Structured programming is the name which has been given recently to a

methodology of designing computer programs. Many programmers insist

that they have been using this technique for a long time and this may

well be true but the recent emergence of this technique has resulted

from an attempt to formalize the process of designing programs in the

same manner as logic design has been formalized. The techniques used

are, in general, not new but the formal basis is.

DESIGN CONSIDERATIONS'

The process of designing and writing a program can be subdivided into

a number of tasks:

(a) understanding the problem

(b) producing an algorithm to solve the problem

(c) coding the algorithm in a particular language

(d) testing the resulting program

(e) iterating round the above tasks until the program is correct.

In conventional programming, tasks (a) and (b) are undertaken by the

systems analyst and (c) and (d) by the programmer with (e) shared between

both of them.

This decomposition process can be thought of in a number of ways but

structured programming would suggest that it should be looked at as a

top-down analysis, i.e. each stage is an elaboration of the previous

stage with a greater degree of detail and complexity. This means that

the problem is initially specified at a relatively low level of

complexity and detail, and that the problem is gradually elaborated to

produce the final program by stepwise refinement.

The nature of the difficulties involved in each step will depend upon

the problem and on the constraints of its solution, e.g. resources

available. The main difficulty in any problem-solving situation is to

contain the complexity of the problem, and it is this complexity which

provides the intellectual challenge of programming. In structuring the

97

Structured Programming

solution, an attempt is made to simplify the complexity and to aid

understanding. This approach is more likely to result in a correct

solution.

Structured programming offers a number of benefits to its users:

(a) Each step is independent of other steps hence allowing

separate checks at each step.

(b) Each step may be checked by checking the elaborations

stage by stage.

(c) An error may therefore be detected in a systematic

manner.

(d) At any one time only a small amount of information

has to be remembered and manipulated.

(e) The structure evolved is suitable for a rigorous proof

of the correctness of the entire algorithm.

PROGRAMMING CONSIDERATIONS

How do the concepts of structured programming produce 'better' programs?

If we take the decomposition of a problem into its programming solution

we see that the programming solution must contain a structure of 'boxes

within boxes' in a pictorial representation where boxes within boxes

represent the lower level elaboration at the upper level (Fig. 8.1).

This means that we have a modular structure where modules can be tested

independently.

3

3

3

Fig.8.1 Block structures (the numbers represent the levels)

9 9

Structured Programrmng

It should be pointed out here that we have a structure which looks,

in some respects, similar to a flowchart which gives a pictorial

representation of the program structure. The main difference is that

the concepts in structured programming place restraints on the equivalent

flowchart representation. The shortcomings of flowcharts are that they

are too general and do not constrain the structure to be 'well-formed'.

The main problem is the undisciplined use of the goto or jump instructions

which can cause convoluted flowcharts.

Turning to the constructs in programming languages which allow a

structured program to be built up, a number of simple constructions

suffice in many cases. In the following discussion, textual constructions

are used in the main, rather than graphical constructions. This is

because the author has a programming rather than an engineering background.

Simple succession

This is just the normal sequencing method, i.e. execute the instructions

in sequential order.

Repetition

This involves repeating an operation a sufficient number of times until

a condition is satisfied.

repeat operation

until condition

or while condition

do operation

e.g. while X > Y

do subtract X from Y

Note that this can be decomposed into lower level statements if necessary.

hile A | is

do B J while A ] is equivalent to \ LI: if not A goto L2

B

goto LI

etc. I L2:

This structure is equivalent to the flowchart of Fig. 8.2.


Fig.8.2 While-do construct

Notice that this flowchart has one entry and one exit. This is one of

the constraints of structured programming.

Selection

This involves choosing from a set of actions.

If, A then B else C

which is equivalent to the flowchart of Fig. 8.3. Notice again one

entry and one exit to the flowchart.

! I B I c !

Fig.8.3 If-then-else construct

Subprograms

Subroutines and functions obey the rules of structured programming, e.g.

one entry, one exit; so they may be used in the production of structured

programs.

These constructions are just some of the possible primitives from which

structured programs may be built. Provided that the rule of one control

input and one control output is obeyed, the user may design his own

primitives, although it is not normally necessary.

The programming constructions elaborated above have been specified in

a high-level language but they could equally well be put as constraints


at a lower level.

The task of programming is now reduced to elaborating the structure

in layers by using the programming constructs defined above. To

comprehend fully the benefits of structured programming, it is essential

that a number of examples are worked through. It is not possible to

realize the benefits until the method has been used on specific problems.

It is strongly recommended that the readers try the example before

consulting the solution, to obtain the maximum benefit.

AN EXAMPLE OF STRUCTURED PROGRAMMING

As an example I shall take a stepping motor problem.

The problem is:

Design a stepping motor controller with the following inputs

(a) number of steps

(b) forward or reverse.

The four signals required to drive the motor are shown below.

To run forwards the table is traversed downwards; for reverse it

is traversed upwards. Each line steps the motor once and the minimum

time for each step is 5 ms.

A B C D

1 0 0 1

1 1 0 0

0 1 1 0

0 0 1 1

You may have noticed that I have used the first person in this example.

The reason is that the design of anything is an art as much as a science

and involves personal choices and decisions. I shall hope to show in

this example the way in which I cameto these decisions and my reasons

for them. They would almost certainly not be identical to those you

would take in the same design. Neither of us would be 'right' or 'wrong';

we would both have solved the problem in our own way and both solutions

could be equally valid.

Returning to the example, what was my immediate reaction on seeing the

problem? The table of values stood out because of its presentation, and

I instinctively looked for a pattern, for some order in the table. After

a moment's thought it was obvious that the pattern was that the line above

was the pattern below moved one place to the left with a carry around


from A to D. This is a significant step forward, as it now gives me

two possible strategies for implementing the solution (two different

algorithms). The complete table of values could be stored and the output

generated by sequencing through the table in the correct direction or only

one value could be stored and the subsequent values generated by the

algorithm I have just discovered.

At this stage I do not want to get involved in deciding which method

to adopt, as this detail is not relevant until later in the design and

one of the objects of structured programming is to leave the decisions

until it is necessary to solve them, i.e. to leave your options open

until the last possible moment.

I now wish to consider the overall structure of the problem. I am

going to start my design in high-level programming terminology since

this is my background and I feel 'comfortable' with it. Notice that

this is a personal choice which has no relevance to structured programming.

The problem itself breaks down into two actions; inputting the data

specified and producing the required outputs. Hence the first level of

my design is

L0 «input data»

«generate required sequence»

Each of the actions is enclosed in brackets to show that it is an

intermediate step in the solution of the problem. Only the final code

will be shown without brackets.

What have I done with the design so far? I have split the original

problem into two subtasks which are to be carried out in sequence.

I now wish to elaborate each of these actions at a lower level.

At the next level I need to ask what are the subactions in «generate

required sequence». Since this involves several subactions I shall

write the description as a function.

LI «generate next sequence» becomes

function generatesequence (direction,steps)

«function body»

end;

generatesequence (direct ion, steps)

« input data» becomes «read no. of steps»

«read d i rec t ion»


I have now broken down the action into a function which requires two

parameters, direction and steps, which are the values obtained by the

input action. Notice that I have not attempted to elaborate the algorithm

of the function yet. One of the biggest pitfalls is to try and take too

many decisions at once. If you only make small changes at a time it is

easy to correct if the decision was wrong and, hopefully, this will tend

to isolate the decision-making so that one wrong decision does not mean

modification to all the program.

At the next level «function body» needs to be elaborated.

L2 «function body» becomes «initialize sequence»

while «not finished»

do «get next sequence»

«output sequence»

«wait until ready»

endwhile;

Notice that I have not yet chosen how to generate the next in sequence;

I could still use either method elucidated earlier. This above elaboration

has produced a loop construction which allows us to generate the sequence

of outputs required.

At the next level I wish to elaborate the test for the while statement.

How do I know when the output sequence is to stop? I want to output

steps number of output sequences and so the test is steps > 0 and I also

need to decrease this count inside the dp_ body. This is a standard loop

construction and I could have incorporated this in a special construction

for structured programming, as many people have done, but I will keep to

the simple constructions shown earlier in this example

L3 «not finished» becomes steps > 0

«get next sequence» becomes «get sequence»

steps = - 1

I have assumed that I am producing a high-level language program at this

stage and I have translated some parts into a high-level language notation.

At this stage I can really get no further without making a decision on

how to generate the sequence I require; so I need to make a choice between

the two alternatives. At first sight the generation algorithm looks more

attractive than the table look up since it uses less storage space.

However, I still need to consider how to do the generation. In a high-

level language it is normally difficult to perform bit manipulation


(which is what is called for by this example) so in a high-level language

approach I will use the table look up method since this is easier and

more efficient to implement. Notice that I have taken into account the

target language for this design; we shall see the relevance of this

later on.

Having decided on this approach, I can now decide upon the relevant

program data structure to map the table on to. In the present case the

most appropriate would be a circular list if that were available, and I

would need a doubly linked list to enable forward and backward traversal

of the information as the problem requires. Since I do not wish to deal

with the complexities of such data structures here, I will assume that

the high-level language has the appropriate routines to create (initlist)

and access such a structure.

One more elaboration which I need to do is to elaborate «get sequence»

L4 «get sequence» becomes if «forward direction» then fitem (seq)

else bitem (seq)

where fitem and bitem are standard routines for producing the next forward

item and the next backward item in the data structure.

If I now assume that all the actions that have not been elaborated so

far are calls to functions already present in the system, we have the

complete program as:

read (steps);

read (direction);

function generatesequence (direction, steps);

initlist (seq, 11, 14, 6, 3);

while steps > 0

do if direction then fitem (seq)

else bitem (seq);

steps = steps - l;

output (seq);

delay (5);

endwhile;

end;

generatesequence (direction, steps);

I have assumed here that the function read reads a value of true for

forward, and false for backwards into direction.


This then is the elaboration of the problem into a high-level language.

For this type of problem on a microprocessor, assembly code might well be

used; so I will now consider how the problem could be mapped down on to

assembly code.

The first point is that assembly code is a low-level language, but

this does not mean that the complete design above should be taken and

elaborated downwards. To get even a reasonably 'good' program the design

decisions taken in the previous design need to be carefully scrutinized.

What is necessary is to start at the top level and check each decision

made to see if it is applicable in the present situation. When this is

done the only major decision which needs reconsidering is the algorithm

to be used for generating the sequence. In the high-level language

approach we used a doubly linked circular list. This is not an easy

structure to provide in assembly code; so it is worth considering the

alternative method. The operation to produce the next sequence is a

4-bit rotate operation. Assuming that we are producing code for the 8080

then we have to deal with an 8-bit machine, i.e. our data structure has

to be a minimum of one byte. How can we map a 4-bit rotate operation on

to the 8080 assembly code? This is equivalent to asking how we can

simulate a 4-bit rotate operation on the 8080 hardware. The answer is

to notice that if we duplicate the 4-bit pattern to an 8-bit pattern and

perform the 8080 rotate operations on this pattern we obtain the required

result in the bottom 4-bits. To produce the required output pattern the

top 4-bits must be masked out of the resulting byte pattern. This appears

easier than implementing circular lists; so I shall use this approach to

solve the problem in assembly code.

I can start the new phase of the design from the abstract stage of the

previous design:

«read number of steps»

«read direction»

«routine generatesequence»

«initialize sequence»


do «get next sequence»

«output sequence»


endwhile;

«end of routine»

«call routine with parameters»


Before continuing I must examine this design to see that no false decisions

have been taken. In fact the organization here is not really suitable for

assembly code as I have a routine definition inside the execution sequence.

This would require a jump instruction to jump around the routine definition.

It is better to put the definition before or after the execution sequence.

I shall, therefore, reorganize the design to:

L0 «routine generatesequence»

«initialize sequence»


«get next sequence»

«output sequence»


endwhile;

«end of routine»

«read number of steps»

«read direction»

«call routine with parameters»

You may have noticed that this is not identical to the design I had for

the high-level language solution—I have changed function generatesequence

into «routine generatesequence» and end to «end of routine». These

changes were necessary because I had made too large a step in the first

design and had gone straight to a high-level language. For the present

design I need to go back to a more abstract definition.

I can now elaborate this design to a lower level

LI «initialize sequence» becomes «initialize sequence to first value»

«not finished» becomes «steps > 0 »

«get next sequence» becomes « i f forward direction then next seq.

forward else next seq. backward»

«steps = steps - 1 »

Notice that this looks yery similar to the previous design except that

the statements are enclosed in brackets indicating that they are still

to be elaborated further.

Having reached this stage, certain decisions have to be made concerning

the allocation of data to locations in memory. This is handled auto-

matically in a high-level language but is one of the designer's tasks at

the lower level. In this example we need locations to keep the direction,

number of steps and the current sequence. I shall assume that these


locations are register B, register C and register D of the 8080

(octal used in assembly code).

L2 <<routine generatesequence» becomes GENSEQ as a label

«read number of steps» becomes «read no into C>>

«read direction» becomes «read no into B »

«call routine with parameter» becomes CALL GENSEQ

«end of routine» becomes RET

I do not require any explicit parameters since they are in registers

«initialize sequence» becomes MVI D,063

Assuming as before, that direction is 0 for forwards and 1 for

backwards

L3

if «forward direction» then «next becomes MVI A,000

seq. forward» else «next seq. backwards» ADD B

MOV A,D

JNZ LI

RAR

JMP L2

This looks as though I have taken a large step instead of several small

steps. What I have done is to translate the vf ... then ... else

construction into assembly code together with translating the operations

on the data. Notice that I have now got myself involved with the

intricacies of the 8080. The reason why I need the first two instructions

rather than MOV A,B is due to the way in which the 8080 sets its flags. It

is this sort of detail which should be left for as long as possible

before being inserted into the design.

To keep in mind what we have so far I will write out the complete

solution so far.


GENSEQ MVI D,063

«while» «steps > 0 »

« d o » MVI A,000

ADD B

MOV A,D

JNZ LI

RAR

JMP L2

LI RAL

L2 MOV D,A

«output sequence»


«steps = steps - 1 »

«endwhile»

RET

«read no into C» «read no into B»

CALL GENSEQ

HLT

Refining further

L4 «whi le» «steps > 0 » becomes L5 MVI A,000

«do» ADD C

«steps = steps - 1 » JZ L3

«endwhile» JM L3

DCR C

JMP L5

L3

The next problem is the method of input and output. I shall assume

in this example that both number of steps and directions are single

digits input from switches connected to ports 0 and 1 and are set up

prior to execution. To output the sequence I have to mask the value

and then output it to the correct port which I shall assume is port 8,

i.e. 10 octal.

109

AN I

OUT

IN

MOV

IN

MOV

017

010

000

C,A

001

B,A


«output sequence» becomes

«read no into C » becomes

« r e a d no into B » becomes

The only elaboration left is « w a i t until ready». I need some code to

delay for 5 ms. I need a loop around a piece of code to generate this

delay. In a loop I have to decrement a counter and test to see if it

is the end of the loop. This involves a total of 7.5 yS for the decrement

and 5 yS for the test. To get a delay of 5000 yS I need to go around

this loop approximately 1000 times. I have not used register E so far,

so I may use this as the counter, but 1000 exceeds the maximum count of

256 for this register.

I must make the loop bigger. I could insert 6 NOP instructions which

makes the loop time 19.5 yS, or I could insert PUSH H, POP H and NOP,

which takes 20 yS and uses less storage. For the latter, the loop count

is 250, i.e. 372 octal.

« w a i t until ready» becomes

The complete program is therefore:

GENSEQ MVI

L5 MVI

ADD

JZ

JM

MVI

ADD

MOV

JNZ

RAR JMP

D,063

A, 000

C

L3

L3

A, 000

B A,D

LI

L2

L4

LI

L2

L4

MVI

PUSH

POP

NOP

DCR

JNZ

RAL

MOV

AN I

OUT

MVI

PUSH

POP

NOP

DCR

JNZ

DCR

E,372

H

H

E

L4

D,A

017

010

E,372

H

H

E

L4

C

no Structured Programming

JMP L5 IN 001

L3 RET MOV B,A

START IN 000 CALL GENSEQ

MOV C,A HLT

This is the program in assembly code although it is still not quite

complete. The assembly code which when translated produces the correct

machine code has been produced, but it does not contain any assembler

directives. There are at least two that are necessary. An END directive

must occur at the end to indicate the end of the program to be translated,

and an 0RG directive specifying the address in memory from which the

assembled code is to be placed has to be inserted at the front of the

program.

You may feel that a lot of effort has been expended on what is

essentially a trivial program. This is true, but consider what might

happen on a large program. It is essential that the program should be

designed properly, whether it is small or large, and attempts to cut

short the design process almost invariably end in a badly designed

program that is difficult to modify and debug.

You may wonder at the lack of comments in the final program. This is

really a matter of taste. Provided that the initial design is kept,

there is no need for extensive comments in the program. Some designers

like to keep the design decisions in the program as comments although

I prefer to keep them separately. This is simply a matter of taste.

Some programmers might be tempted to 'optimize' this program to try

and make it more efficient. This is allowable provided that they modify

the design accordingly. The program itself should be transparent, in

that it should represent as clearly as possible what the programmer

intended. This is more important than a saving of a few microseconds

in efficiency.

I hope this example has indicated the methods used in structured

programming and given the reader an insight into program design. For

more detailed information the reader should consult the books given in

the references (Dijkstra (1972), Dijkstra (1976)1

9 Development Systems

INTRODUCTION

The design and construction of a piece of digital or analogue equipment

is concluded by the debugging, testing, and commissioning of the hardware,

a process accepted and well understood by design engineers. It consists

of checking the performance of the equipment against the specification

requirements, and modifying the circuits until it operates satisfactorily.

With microcomputer based systems, the process is just as essential, but

the task should be easier because of the flexibility of the programmed

approach, but in practice this may not be so. New techniques must be

learnt in order that the software and the hardware can be successfully

'debugged' together. The tools are called 'development systems' and

differing approaches are available. The development system must provide

the facilities to

isolate the symptoms,

aid diagnosis (if possible),

correct the fault.

Three basic approaches are discussed.

(a) Simulator

(b) Microcomputer with program monitor

(c) Microcomputer with hardware console

all of which can be used separately or (a) combined with (b) or (c).

DEVELOPMENT PROCEDURE

The hardware consists of three distinct parts. Firstly there is the

peripheral system which defines the interface to the microcomputer. It

comprises devices such as analogue-to-digital converters, digital-to-

analogue converters, relays, random logic, etc; components of the system

that are not part of the microcomputer but form an integral part of the

final equipment. They will be designed and constructed in the usual way.

Secondly, there is the microcomputer hardware used specifically for

prototype development and testing, none of which is used in the final

system.

Ill


Finally, there is the production form of the microcomputer hardware.

It contains a minimum of components compatible with performing the

dedicated function of the equipment, and replaces the development system

used earlier. A good development system should make the transition from

the development hardware to the production hardware as simple as possible.

The translation from the first program to the fully operational equipment

can be broken down into a few phases:

(a) construct the peripheral hardware and connect to the

development system;

(b) load the program from a permanent storage medium (e.g. paper

tape) into the development system, and test. Modify the

program and the peripheral hardware until the performance

is satisfactory, keeping a record of any changes;

(c) transfer the program to PROM or ROM and test with the

development system;

(d) replace the development system by production hardware and

test the production hardware system;

(e) commission full equipment.

Development systems are intended to help the user through stages (b) and

(c) and, in some instances, (d). If the program is correct, then stages

(d) and (e) require standard hardware fault-finding techniques; oscillo-

scopes, logic probes, logic analyser, are typical components used.

The basic commands of a development system will include:

run and stop program execution;

load and read memory locations and registers;

single step program and run to a breakpoint address;

trace the last N instructions,

Cosmetic features include number conversion, search for data, calculate

relative offset, etc.

Commands to manage backing storage on paper tape, floppy disc, or

cassette recorder may be provided.

Simulator

A simulator is usually a program which runs on a large computer, which

takes the machine code of the microprocessor as input and simulates the

instruction execution of the microprocessor. The characteristics of

simulators have been described in Chapter 8. The major drawback is

113 Development Systeme

slow execution of code, which restricts realism on input and output.

Fault-finding aids, console facilities, and back-up storage are usually

excellent,since they normally exist in the computer used. The system

is suited to checking the logical correctness of the program.

Microcomputer with Program Monitor

An obvious way of running the machine code of a microprocessor is to

use the microprocessor itself. This system and the one to follow, use

such an approach. However, there are definite attractions in using a

program, the monitor, to provide the intercommunication between user

and the development system. The options are:

to have two processors, one running the monitor, and

the other the user program;

to make one processor look like two by making it switch

from one program to the other, and back.

Τυο-processor System D The monitor processor executes a program which

organizes the communication between the development system and the user,

and monitors the operation of the second processor, an emulator processor

(EP), which executes the user program. Around the latter is hardware

which performs, at high speed, tasks that are impossible for the monitor.

A further elaboration is the provision of an 'umbilical cord' cable

connected at one end to the processor (EP) and at the other end to a

plug whose pin configuration is identical to the prototype microprocessor.

The plug is inserted in place of the prototype microprocessor so that the

emulator processor in the development system executes the user program in

the prototype hardware under the control of the monitor. This system is

called 'in circuit emulator' (ICE); it is a powerful development tool,

but it is expensive.

One-processor system D Software is used to make the processor switch

from the monitor to the user program, and back again. The main drawback

is that most microprocessors lack the facilities to perform the switching

operation efficiently. This may mean that certain registers cannot be

examined or that operations such as trace are performed at a slow execution

speed, since the program must return to the monitor after every instruction.

Both approaches provide a wide range of 'debugging' aids, good user/

monitor interaction, and can be designed to support paper tape, floppy

disc, or cassette tape back-up storage.

114 development Systems

The development system is provided in a case which can accommodate and

interconnect printed circuit board (PCB) modules. The case contains power

supplies, front panel switches and sockets for the modules. A processor

with monitor program and teletype input-output would constitute the minimum

configuration. Memory modules with read only or read-write capability, and

input-output ports, are inserted by the user.

Microcomputer with Hardware Console

In the two approaches described above, the user feels too remote from the

hardware-« sensation many engineers dislike. A hardware console like those

provided on larger machines, overcomes this problem. To make the cost and

size of the console realistic, only a limited range of fault-finding aids

can be offered. With the hardware console the user is more aware of what

is happening because he is closer to the hardware of the machine.

Except for the console logic, the hardware system is identical to the

system above. A typical configuration is shown in Fig. 9.1. The CYBA-0

ANALOGUE SIGNAL

Γ l 1 I 1

CY B A -0

CENTRAL PROCESSOR

■

SYS BL

'

U K READ WRITE MEMORY

1 1 I

INPUT OUTPUT

TEM S

' PROGRAMMERS CONSOLE

TELETYPE 1 INTERFACE

' 1 1 '

TELETYPE WRITER

' INPUT

OUTPUT

^ 1 ΓΤ7Π ΓΤΤ7Ί

' \

OSCILLOSCOPE

*l

Loe IC TUTOR

1

PAPER TAPE

READER

PAPER TAPE

PUNCH

Fig.9.1 Block diagram of 8008 development system


is a development system with user console, processor, read-write memory,

and a teletype interface. The signal bus is extended to a logic tutor,

a card frame, which can accommodate additional modules, in particular

input and output. A typical selection of input-output devices is shown.

The peripheral hardware can be assembled on the tutor and connected

together using patchcords, and connected to the input-output ports in

the same manner.

Hardware Bus Monitor

Simpler verions of the hardware console are available. These usually

consist of a set of lamps and switches which monitor or load the system

bus, using control switches. Such devices can be useful for 'debugging'

the production hardware, since they show if any bus signals are stuck at

Ί ' or 'Ο', and memory and input-output devices can be checked by

overriding the processor signals and loading addresses onto the bus from

the switches. The facilities provided for testing programs can be rather

limited.

USER CONSOLE

The console controls on the development system are described in detail,

to give some idea of the facilities required by the user.

Fig.9.2 Front panel of 8008 development system


Fig. 9.2 shows the CYBA-0 console. The reader is referred to this

for guidance when studying the description of the console operation.

Console Input and Display

The console accesses one bank of 5 octal lever-wheel switches for both

address and data. It also has two separate output fields consisting of

one bank of 5, and one bank of 3 seven-segment displays, labelled

'address' and 'data' respectively.

Address Input and Display

The address field consists of 5 lever-wheel switches which are separated

into 2 digits for the page address and 3 digits for the line address.

The maximum and minimum address fields are 77.377 and 00.000 respectively,

a total of 64 pages of store, or 16K bytes.

The five-digit address display shows the current value of the program

counter when running a program, and when halted. In console mode, the

address displayed is either the location of the next instruction to be

executed or the location of data in the memory. If a program that is

running stops, by executing a halt instruction, the address displayed

is the address of the halt order. The display will automatically increment

by one when the HLT control on the console is operated.

Note: When performing input-output operations, data associated with the

input-output operation appears on the address display; this could be

misleading if interpreted as program addresses.

Data Input and Display

The data input and display facilities can be used either under console

control or under program control. In both cases the data to be input

are the lower 3 digits on the lever-wheel switches. The maximum and

minimum range for data is 377 octal and 000 respectively.

The data display is a separate set of 3 seven-segment numeric indicators

and only changes when forced to by console action or by the program.

Console Control of Data D The data input field is used when performing

the console operations deposit and read internal registers.

The data display is active for most of the console operations, either

showing the data at a memory location or the data in internal registers.

These operations are described when dealing with the console controls.


Program Control of Data D The data on the lower three octal switches

can be input under program control by using the program instruction INP 7

(See Instruction Set). Machines with the L.E.D. displays can also input

the two upper address digits by the program instruction INP 6. This

facility can be used to input information during program execution. On

the earlier machines, this function does not work in single step mode.

Data can be output to the display by using the instruction OUT 30.

This can be used for displaying numeric messages during program execution.

Console Control Functions

The facilities for program development and debugging are provided by the

console controls. These controls can be used to load addresses, deposit

data to memory, examine memory, step through the program, read the CPU

registers, halt the processor, and start or continue to run a program.

Halt Program (ELT) D This control stops the program running and

forces the processor into the STOP state. It also activates the console

'enable' line, which enables the rest of the console switches. The HLJ

control must be operated whenever console action is required, even if the

processor stops under program control. If any other console control is

inadvertently depressed before the HLT control, then this action is

remembered, and the operation occurs at the same time as the FUJ operation,

(e.g. if LAD is depressed, then HLT, the CPU will stop and then the load

address operation will be performed).

Note: If the processor is in a 'wait' state (Wait light on), the HLJ

control has no immediate effect. To transfer control to the console,

first the HLT must be operated and then the processor released from the

'wait' state by external action. For example, when inputting from the

teletype: after depressing HLT, a character on the teletype keyboard

must be depressed to release the processor.

Start or Continue Execution of a Program (CONT) D The program is

started at the address displayed on the address lamps by operating the

CONT control. This action also de-activates the rest of the console

switches.

If the processor stops under program control, it can be restarted by

operating CONT. The program then starts at the instruction after the

instruction that caused the processor to stop.


Note: Later machines have a START control as well as CONT. For most

uses, the actions of both are identical.

Load Address (LAO) D The address set on the address switches is

loaded into the program counter by depressing the LAD control. The

current address in the program counter is overwritten.

Examine Memory (EXM) D The data at the memory location given on the

address display is shown on the data display when EXM is operated.

Successive operations of the control EXM automatically increment the

program counter before the memory read cycle. Therefore, after examining

a word, the address of the word and the data at that location are displayed

on the indicator lamps.

Deposit Data in Memory (PEP) D The data set on the data switches is

loaded into the memory location given on the address display by raising

the PEP control. The location is then examined automatically and the

data presented on the data display for verification.

Successive operations of the PEP control automatically increment the

program counter before the memory write cycle. An error in depositing

data can be corrected by first depressing EXM then setting the correct

data on the switches and operating PEP.

Single-Step Through Program (SST) D Repressing SST will cause the

CPU to execute the instruction at the location given by the address

display. If the order is 2 or 3 words long, then the address display

will increment 2 and 3 times respectively. The data in the accumulator

at the end of the instruction is output to the data display. If the

instruction is a teletype input instruction, the sequence will not finish

until a character is input.

Read Index Registers (RIR) D The data in the seven internal registers

can be output on the data display by setting up the correct instruction

on the data switches and then depressing RIR. The information to be

set up on the data switches is as follows:

Code Register displayed

301 Register B

302 " C

303 " 0

304 " E

305 " H

306 " L


This operation has no effect on the address display or program counter.

Wait and Run Lamps

AVun' lamp is illuminated when the processor is executing a program.

The lamp is extinguished when a halt instruction is executed, or when the

HLT control is operated. The 'wait' lamp is turned on when teletype

transfers take place.

TELETYPE INTERFACE

The teletype interface is a self-contained unit situated in the CYBA-0

crate. No program resides in the store to operate the interface; it is

only necessary to use the correct input or output instruction to activate

the teletype. The interface incorporates a Universal Asynchronous

Receiver/Transmitter (UAR/T) chip and operates asynchronously to the

computer. Operation is full duplex, with 8 bits, no parity check.

Port Allocation

A teletype interface is assigned as follows:

Input from TTY INP 0 (101 octal)

Output to TTY OUT 16 (141 octal)

Description of Operation

Input from TTY D If the CPU asks for input and it is not available,

the computer is forced into the 'wait' state and the WT lamp on the

console lights up. The keyboard must now be activated. When the

character arrives, it is transferred into the accumulator of the

processor. The UAR/T has a double buffer, thus allowing for the storage

of two characters. If more are input before the CPU requires them, some

will be lost. If the tape reader, on the teletype, is used on the

continuous mode, the program must be capable of handling a new character

every 0.1 second, otherwise errors will occur.

Output from TTY D When the CPU executes an output cycle, the data

is transmitted to the TTY. If the buffers in the UAR/T are full, the

output is inhibited by forcing the CPU into the 'wait' state. This

double buffering allows the programmer to arrange the program so that

Development Systems

the CPU can perform some computation but still keep the TTY running at

full speed.

10 Worked Examples

INTRODUCTION

As with most design activities, program design is very subjective, and

a computer program to perform a specified task will reflect greatly the

thoughts and ideas of the designer. Thus, no two solutions independently

derived for a given example are likely to be identical; the solutions to

the four examples presented below are typical-not the best-and hopefully,

not the worst. That is not to say, however, that good design procedure

is arbitraryH'ar from it—and Chapter 8 describes principles which can

prove invaluable, especially for large programming projects.

One interpretation of design procedure is to view each stage as producing

a different form of definition or description; often, a textual description

is the starting point, followed perhaps by flow diagrams or their

equivalent, right down to the machine code. Each form defines the system

but at a new and usually more detailed level, encompassing new design

decisions. For the examples below, textual descriptions are followed

by flow diagrams, memory maps, and assembly codes. These last three are

tools of the designer, used to transform from the functional definition

through to the program and hardware system, and record the important

decisions. Production of the assembly code is the last stage of the

design. Here one brings together the software in the form of a program

and the hardware in terms of the processor instruction set, the input-

output allocation and memory requirements. The combination is then

tested. The memory maps indicate areas reserved for the main programs

and subroutines, the data, general work space, specific job allocations

to registers and memory locations, and input-output requirements.

The development systems used for the solutions are described in the

previous chapter, and more details of the individual modules are given

in Appendix 4. The solutions for the 6800 and 8080 all assume the first

256 memory locations (0000 up to 00FF hexadecimal and 000.000 to 000.377

octal respectively) are reserved for the stack. For 6800, the input-

output subroutine SETPIA occupies the area 0100 hexadecimal up to 013F

hexadecimal. This subroutine, which initializes the input-output (see

Appendix 3) is called at the beginning of each program, immediately

121

122 Worked Examples

after loading the stack pointer. This allocation is not shown explicitly

in the memory maps. The numbering system for the 6800 is hexadecimal,

and for the 8080 and 8008, octal.

The four examples are: Waveform generator.

Data logger.

Traffic light controller.

ADC via DAC.

Example 1: Waveform Generator

Spécification: Display repetitively on an oscilloscope the ramp

functions illustrated in Fig. 10.1.

9

Signal

Level 6

(volts) 3

0 0 100 130 180 190

Time (ms)

Fig.10.1 Specification of waveform generator

How is the waveform to be generated? Alternatives include either a

look-up table approach, similar to that used for the sinewave in Chapter

3, or a simple calculation for each sample along the time course. The

first flow diagram (Fig. 10.2) reflects the first level of design; note

that the two alternatives are still open. However, the second flow

diagram (Fig. 10.3) indicates the decision that an appropriate increment

is to be added to the accumulator and then output to form the ramps.

The waveform is split up into four segments, and parameters defining

each are stored in a data block. The program switches from one set of

data to the next as each segment is complete. The second flow diagram

details the principal actions of the program, and it is from this that

the assembly codes are derived. The memory map for the three solutions

is shown in Fig. 10.4 and the data structure in Fig. 10.5.

[ Start I 123

Store Waveform Description

Star t Cycle.

No

No

Start Segment

Form next Sample

Output Sample

1 Time Interval

. ^ S e gnien r j s . ^Complete •^x>

j T Y e s

< / C y c l e > ^ ^Complete • ^ >

__Yes_

Either equally spaced samples or parameters def ining each segment.

By e i the r stepping through the look-up table or calculat ion

Ei ther terminal amplitude or segment t ime.

Test for the completion of N segments.

Redundant in continuously cycl ing machine.

I" Stop |

F i g . 1 0 . 2 Flow diagram f o r waveform g e n e r a t o r

Cycle

Load start address of ^ata I

Newseg

I n i t i a l i s e for next segment. J

calculate Output

|T1m1ng Subroutin (CLK)

Fig.10.3 Second flow diagram for waveform generator

124 Worked Examples

8080 and 8008

Page.line (Octal)

001.000

001.100

001.140

Registers

A B C D H L

M Port 12

} }

Memory Map

Main program and subroutine

Table of segment definitions

{ (

6800

(Hexadecimal)

0140

0180

01A0

Special locations

0/P sample Time interval Increment for accumulator Segment f inal value Data block Index Address Register

6 bits to DAC

Memory mapped

800A

Fig.10.4 Memory map for waveform generator

001.100 077 Start Value 1 020 Time Interval 2 377 Increment (+ ,-) 3 006 End Value

4 5 6 7

10 11 12 13

032 377 000 032

032 036 001 057

14 057 15 003 16 001

01.117 077

Fig.10.5 Example data for 8080

CYCLE NEWSEG

C0NTIN

^Subrout ine CLK

Assembly Code

LXI MVI MVI M0V INR MOV INR MOV INR MOV INR OUT ADD OUT MOV

SP 0 0 0 . 3 7 7 H 0 0 1 L 1 0 0 A , M L B,M L C,M L D,M L 14 C 14 E.B

CALL CLK CMP JNZ MVI CMP JNZ JMP

NOP NOP DCR JNZ RET

D C O N T IN A 1 2 0 L NEWSEG CYCLE

E CLK

Comments

Set stack pointer Address of f i r s t

datum Ace A «·- i n i t i a l value

Register B «- time interval

Register C ■*■ increment (+ or-

Register D «- f inal value

0/P i n i t i a l value Add increment ( + o r - ) Ü/T to port (12) Form time

interval Test for segment termination False : continue Ace A «- f inal data addres +1 Data exhausted ? False : New segment Start new cycle

No operations to give time interval unit

(Octal used 1n assembly code)

Fig.10.6 Waveform generator 8080 (8008)

, , 125 Worked Examples

The assembly program in Fig. 10.6 is for the 8080: note that at the

beginning of each new segment the four relevant parameters are transferred

from memory to special registers, for easy access. The same code would

run also on the 8008. The example illustrates how registers on the

processor may be used to advantage, and how the 8008, even with its

limited instruction set, proves adequate for a certain class of application.

Typical data values for the 8008 are given in Fig. 10.5. In order to

relate the waveform amplitude in the specification to the data provided,

one must remember that the CPU works in two's complement arithmetic, and

also the inverted offset binary specification of the DAC given in

Appendix 4.

CYCLE NEWSEG C0NTIN

Assembly Code

LDS JSR LDX LDAA STAA LDAB JSR ADDA CMPA BNE STAA INX INX INX INX CPX BNE BRA

Subroutine CLK NOP

NOP DEC BNE RTS

#00FF SETPIA #0180 0,X 800A l .X CLK 2,X 3,X CONTIN 800A

#0190 NEWSEG CYCLE

CLK

Comments

Stack pointer In i t i a l i se I/O Index register +· data base address Ace A «- i n i t i a l value Output sample Ace B «- time interval Form time interval Form next sample Test segment terminal value False :next sample 0/P segment terminal value

Increment to base address of next segment

Data exhausted ? False : next segment Start new cycle

No operations to give time interval between 0/P

(Hexadecimal used throughout.)

Fig.10.7 Waveform generator 6800

The 6800 program (Fig. 10.7) uses the index register to access the

data; as with the 8080, these are assumed to be in memory area 0180

hexadecimal up to 018F hexadecimal. Data values can be derived from

those given in Fig. 10,5, but allowance must be made for the speed

differences in the machines by changing either the interval counts

(Register B) or the subroutine CLK. An algorithm for the 6800 more

equivalent at assembly code level to that for the 8080, would transfer

the four data for a given segment into a reserved work area; the program

kernel would use these locations throughout, with their values changing

at the beginning of each segment. Another version for the 8080 shown

in Fig. 10.8, uses the same basic algorithm but with a form of pseudo-

index addressing. For while the version which utilizes the four

1 ne

Worked Examples

registers is compact and efficient, the approach would prove very

difficult in the event of the segment definitions requiring more than

the four parameters. However, with the indexing method, the number of

parameters could be extended readily, as it could with the 6800 version.

CYCLE NEWSEG

CONTIN

Subroutine CLK

Assembly Code

LXI LXI MOV

SP 000. H 100. A

XCHG OUT LXI DAD MOV

14 H 0 0 1 . D B,M

CALL CLK INX ADD INX CMP JNZ OUT INX MOV CPI JNZ JMP

NOP NOP DCR JNZ RET

H M H M CONTIN 14 H A,L 120 NEWSEG CYCLE

B CLK

.377

.001

,000

Comments

Set stack pointer H,L «- start address of data Ace A +- i n i t i a l value H,L « - D,E 0/P to port 14 Load immediate H,L H,L + H,L + D,E B -«-time interval Form time interval Increment data address Ace A ■*- Ace A + increment Increment data address Segment terminal amplitude? False : - CONTIN 0/P terminal amplitude Increment data address Is data

exhausted ? False : - NEWSEG Start new cycle

No operations to form time interval

(Octal used throughout)

The solution uses a form of pseudo-index addressing, where register pair D and E is used as a global or base address and the pair H and L as a local modified address.

Fig.10.8 Waveform generator 8080 with pseudo-index addressing

Example 2: Data Logger

Specification: A data logging system is required to store one

thousand samples from a continuous waveform, at a sampling rate ranging

from 500 Hz up to 5 kHz.

A flow diagram of the solution, a memory map and the program listings

are shown in Figs. 10.9 - 12 respectively.

Equalizing Inter-Sample Time

Clearly, it is important that the samples are regularly spaced in time.

For the 8080, since the test for the upper address limit has to be

performed in two stages (m.s.b. and l.s.b. separately), it is necessary

to include the dummy operations following the label EQTI. This

situation does not arise with the 6800 version (Fig. 10.12).

Worked Examples

Set Number of samples N, Interval T

Loop n = 1 to N

Trigger A D C

Wait for Conversion

1 I/P and Store 1

|Form time interval!

Repeat n : Top Ί

Fig. 10.9 Flow diagram for data logger

8080

Page.Line (Octal

001.000

002.000

006,000

Registers

D E H L

ill Port 2 Port 8

} }

}

Memory Map

Main program and subroutine I/P Data

Subroutine CL K Time interval Current Data

address

8 bits to ADC 1 bi t to trigger

6800

(Hexadecimal)

r 0140

\ 0200

^ 0600

Special Locations

Ace B 01FF

( Index V. Register

Memory Mapped

8008 800A |

Fig. 10.10 Memory

Assembly Code

LXI MVI LXI

NEXT MVI

EQTI

♦Subroutines CLK

OUT NOP INP MOV INX MOV CALL MOV CPI JNZ MOV CPI JNZ HLT MOV CMP JNZ

DCR JNZ RET

SP 000.377 E 001 H 001.000 A 001 10

2 M,A H D,E CLK A,H 004 EQTI A,L 350 NEXT

A,L C NEXT

D CLK

map for data logger

Comments

Set stack p o i n t e r Regis ter E «- t ime i n t e r v a l H,L *■ s t a r t address of data T r igger ADC

Wait fo r conversion I /P from ADC Store sample Increment data address Form time

i n t e r v a l Compare m.s .b . w i th

upper l i m i t False : r e t u r n v ia EQTI Compare 1 . s . b . w i th

upper l i m i t False : r e t u r n f o r next sam Stop Equal ise time f o r

I . s . b . comparison

Control t ime i n t e r v a l between samples

(Octal used throughout)

Fig.10.11 Data logger 6080

128 Worked Examples

NEXT

^Subroutine CLK

Assembly Code

LDS JSR LDAB LDX STAB LDAA STAA LDAB INX LDAA STAA JSR CPX BNE SWI

DECB BNE RTS

#00FF SETPIA #01 #01FF 0,X #01 800A 01FF

8080 0,X CLK #05E8 NEXT

CLK

Comments

Set stack pointer I/O Ace B +- time interval Index register *■ data address Store time interval Trigger

ADC Ace B -- time interval \ . nr . . . Λ „„„„„,,«. Increment data a d d r e s s ' * DC t i me t0 c o n v e rt

Ace A ■*- i/p sample Store sample Increment data address 1000 l imi t? i .e . 0200 + ( 1 0 0 0 ) 1Q False : -»- next sample Halt

Control time interval between samples

(Hexadecimal used in assembly code).

Fig.10.12 Data logger 6800

Flexibility

While both programs meet the specification, they could be enhanced to

give greater flexibility and simpler operation. As they stand, to change

either the sampling rate or the total number of samples, instructions in

the program have to be changed. But before modifications are made, one

should ask whether flexibility is really necessary. Is the instrument

to be used invariably at one speed and for 1000 samples? If so, the

solutions given are the simplest and sufficient. Modifications aimed

at improving the operation can prove very costly in program development

and testing. Here, of course, it is \/ery simple to make the parameters

variable at run time by using either special locations or input statements.

Considering the 8080, the instructions to change are, for the sampling

interval :

MVI 001 to LDE 002.000 or INP ^

M0V A,E

M0V A,H to LDA 002.001 or INP W2 (m.s.b)

and for the number of samples:

M0V A,H to LD

CPI 004 CPH CPH

and

MOV A,L to LDA 002.002 or INP W3 (l.s.b.)

CPI 350 CPL CPL

129 Worked Examples

In the first alternative, the special locations (002.000, 002,001 and

002.002) are used to store the parameters; these are set by the user at

run time, and the program accesses them directly. The second approach

implies the use of input devices-a digital switch or teletype-and permits

the number of samples to be changed during the logging process. These

are simple, and may be useful modifications, but one step furtherH'or

example, permitting the input parameters to be given in decimal rather

than octal-proves that enhancement generally is not quite so simple.

This case is left for the reader to examine.

Sampling Rate

8080: Number of clock cycles = 104 + 15 e

6800:

where e = contents of register (E) 10 for 0 < (E) < 256

and when Register E = 0, e = 256

It is a simple exercise to check the sampling rates in

terms of machine clock cycles, as has been done for the

8080. A more accurate calibration could be achieved

by running the program and plotting a calibration curve

similar to that for the sinewave generator in Fig. 3.3.

Example 3: Traffic Light Controller

Specification: Design a traffic light controller for a single

intersection of two roads to provide the following features:

Abbreviations:

Lights North/South denoted by (RAG)N

Lights East/West denoted by (RAG)r

Arbitrary starting state;

stays in this state until PN

It then changes, following the sequence:

If PE occurs in this sequence,

it is ignored.

Stays in this state until Pc

Pads North/South denoted by PN

Pads East/West denoted by P£

State Time in state (seconds)

(RÄG)N (RÄG)E

(RÄG)N (RÄG)E

(RÄG)N (RAS)E

(RÄG)N (RÄ5)E

(RÄG)E

(RÄ5)E

(RAG)

(RAG),; N

6

2

6

18 (minimum)

130 Worked Examples

It then changes, following the sequence:

If PN occurs during this

sequence, it is ignored.

State

(RÄG)N (RÄG)E

(RAG)N (RÄG)E

(RÂG)N (RÄ5)E

(RÄG)N (RAG)E

(RÄG)N (RÄG)E

Time in state (seconds)

18 (minimum)

While there is obvious symmetry in the two transition sequences

(interchange of lights), this does not appear to be useful immediately;

the solution below assigns to each of the six lights one bit of an

output port (port 12), and then identifies the bit pattern for each

state. The flow diagram, memory map and program listing are shown in

Figs. 10.13 - 10.15.

Fig.10.13 Flow diagram for traffic-light controller

Worked Examples

Memory Map

Page 1

IZ° Input :

Output :

8080 (8008) Registers Main Program B and Subroutine. C Subroutine CLK

D E Argument fo r C L K

Port 2 - 1 b i t to N/S pad ; Port 4 - 1 b i t to E/W pad.

Port 10 - 6 b i t s to the l i gh t s as fo l lows:

Green E/W to b i t 0 Green N/S to b i t 3 Amber E/W to b i t 1 Amber N/S to b i t 4 Red E/W to b i t 2 Red N/S to b i t 5

Fig.10.14 Memory map for t r a f f i c - l i g h t controll

START

SEQ1

SEQ2

outine CLOCK CLK1 CLK2 CLK3

Assembly Code

LXI MVI OUT INP JNZ MVI OUT MVI CALL MVI OUT MVI CALL MVI OUT MVI CALL MVI OUT MVI CALL INP JNZ MVI OUT MVI CALL MVI OUT MVI CALL MVI OUT MVI CALL MVI OUT MVI CALL JMP

MVI MVI MVI DCR JNZ DCR JNZ OCR JNZ DCR JNZ RET

SP 000.377 A 041 12 2 SEQ1 A 042 12 E 006 CLOCK A 044 12 E 002 CLOCK A 064 12 E 006 CLOCK A 014 12 E 022 CLOCK 4 SEQ2 A 024 12 E 006 CLOCK A 044 12 E 002 CLOCK A 046 12 E 006 CLOCK A 041 12 E 022 CLOCK SEQ1

B 002 C 000 D 000 D CLK3 C CLK2 B CLK1 E CLOCK

Comments

Set stack pointer Ace A «- (100001 )2 O/P RAGRAG

Ace A «· ( 100010 ) , 0 /p RAGRAG" C

Register E ·*- 6 Form time in terva l 6s Ace A - (100100V, 0/P RÄ5RÄS Form time

in terva l 2s Ace A * (110100)? o/P RA5RA5 Form time

in terva l 6 s Ace A - (001100b O/P RAGRAS Form time

in terva l 18 s

Subroutine to give uni ts of 1 second

i . e . delay = e seconds

e = (Register E)1Q

0 < e * 256

(Octal used in assembly code)

Fig.10.15 Tra f f i c - l igh t controller 8080 (8008)

132 Worked Examples

Example 4: Analogue to Digital Conversion

Spécification: Given a digital-to-analogue converter, a comparator,

and a sample/hold circuit (see Appendix 4 for details), implement an

analogue-to-digital converter and calculate the time for one conversion.

The result is required as a two's complement signed integer of 8 bits.

A basic flow diagram is shown in Fig. 10.16. Notice that the conversion

algorithm is unspecified at this stage. The operation 'convert data'

changes the offset binary code of the DAC into 2's complement.

Fig.10.16 Flow diagram for ADC

Before elaborating any further, the algorithm must be specified.

Alternatives are successive approximation or counter-ramp. The former

consists of making successive binary approximations, starting at the

most significant bit, until all 8 bits have been tested.

A flow chart of the elaboration only is shown in Fig. 10.17. A

solution for the counter ramp is shown in Fig. 10.18.

A memory map of the two solutions is shown in Fig. 10.19, and the

program listing is shown in Fig. 10.20.

Worked Examples 133

Generate and output|

new test value

Reject

Update present value

Fig.10.17 Successive approximation-ADC subroutine

Loop

Add 1 to present value

Fig.10.18 Counter ramp-ADC subroutine

Worked Examples

6800 Memory Map

Program and subroutines

Test bi t

Test datum

Current datum

(OUT) S/H Control

(OUT) DAC (bits C

(IN) Comparator (b

{

(bitO)

-7)

i t 0)

Address Hexadecimal

0200

02FF

0300

Registers

A

B

i/o

800A

800E

8008

}

Counter-ramp

Program and subroutines

Current datum

Work register

(OUT) S/H Control (b i t 0)

(OUT) DAC (bits 0-7)

(IN) Comparator (bi t 0)

Fig.10.19 Memory map for ADC

Assembly Code

LDS JSR LDAA STAA JSR LDAA STAA CMPB BEQ SUBB EORB BRA

TEND LDAB FIN RTS

#00FF SETPIA moo 800A ADC #01 800A #80 TEND #01 #7F FIN #00

In i t i a l i se stack pointer. In i t ia l ise I/O. Set sample hold

to hold. Call ADC algorithm. Set sample hold

to track. Convert offset

binary results to 2's complement and return

Successive Approximation Solution

ADC LDA STA CLRB

LOOP TBA ORA STAA LDAA BITA BEQ ORAB

REJECT ROR BCC RTS

Counter Ramp

#200 TSTBIT

TSTBIT 800E 8008 #01 REJECT TSTBIT TSTBIT LOOP

Solution

In i t ia l ise most significant test b i t .

In i t ia l ise current value (Reg Generate new

test datum. Output to DAC. , s Input comparator value. Test for one. Jump i f zero. Up-date value. Shift test b i t . Jump i f not last i terat ion. Return.

ADC CLRA LOOP INCA

STAA 800E LDAA 8008 BITB #01 BEQ LOOP RTS

In i t i a l i se current value, Add 1 to current value. Output to DAC. } see note on timing. Input comparator value. Test for one. Repeat if zero. Return.

(Hexadecimal used throughout)

Fig.10.20 ADC-6800

135 Worked Examples

Timing

The analogue circuitry will take a finite time to respond to new inputs;

the DAC takes 4 us to settle to 1 l.s.b. accuracy, and the comparator

will take 1 us to respond. The time between the output order to the DAC

and the input from the comparator must be sufficient for both to settle.

These two instructions take 4 us for a 1 us processor clock cycle time,

and this assumes that the output and input occur at the same point in

the instruction cycle. For the DAC and comparator specified, this is

too short, and dummy instructions are needed: 2 NOP orders between STA

and LDA should be sufficient.

Another timing problem occurs with the sample-hold device which will

have a minimum track time. Having converted one sample, sufficient time

must elapse before converting the next. This depends on the program

using the ADC routine.

Conversion time

The time to perform an 8-bit conversion is dependent on the locus of

control through the loop. The longest path occurs if the result is

11111111, the shortest for 00000000, i.e. 302 us and 270 us respectively

for the successive approximation subroutine. A similar calculation can

be carried out for the counter-ramp.

CONCLUSIONS

The examples described above represent typical problems encountered on

the workshop and the reader is advised to study them carefully, possibly

attempting them himself with other microprocessors or looking for

different methods of solution.

xercises

1) How do the two programs (Figs. 3.8 and 3.9) detect the beginning

and end of the look-up table? What are the relative merits?

2) From the assembly codes, deduce calibration curves for the 8080

and 6800, based on machine clock cycles. What is the maximum

number of samples per cycle to meet the given frequency specification

in each case? (See Fig. 3.3).

3) Program the sinewave generator using a complete cycle (4 quadrants)

look-up table, and check the increased performance. Derive estimates

for the 2 quadrant case.

4) In the solution of the sinewave generator of Fig. 3.8, the instructions

LDX and two instructions of CPX use the immediate addressing mode.

Discuss the implications of this, and describe the effect of using

direct and indexed addressing modes instead.

5) What are the advantages of having separate stack pointers for a

subroutine return address stack and an operand stack?

6) In a processor with bank switching, problems occur when a bank

switch of the program memory occurs. What are they? Discuss

methods of overcoming them.

7) Redesign the stepping motor controller of Chapter 8 to perform a

sequence of operations as follows:

10 steps clockwise, wait 1 s; 25 steps clockwise, wait h s;

60 steps anti-clockwise, wait h s.

and repeat from the beginning. Use the graphical structured

constructs to produce a flow chart description.

8) Explain the data values in Fig. 10.4 in terms of the waveform

specification. Derive data for the segment descriptions appropriate

to the 8080 and 6800.

9) What program changes have to be made to incorporate an additional

segment into the waveform?

136

Exercises

10) Change the first ramp segment into an approximate exponential

rise with the same time and terminal amplitude.

11) Devise an expression for the sampling rate of the 6800 data

logger.

12) Assuming an integer number of blocks of 256 data were to be

recorded, rewrite the 8080 program and check improved performance.

What is the difference with the 6800?

13) (a) Derive a general expression for the delay in the traffic

light controller subroutine CLOCK in terms of the registers

B, C, D and E.

(b) Rewrite the subroutine using main memory locations, rather

than registers, and derive a new delay expression.

(c) Incorporate a pedestrian request system on N/S lights in

the traffic light controller.

14) Write a program, using the ADC program of Example 4, to sample

an analogue waveform, delay the data 100 ms, then output the

data to the 8-bit DAC. Modify to include a variable delay time.

What is the maximum sampling rate and minimum delay time, and

the delay increments?

References

D.W. BARRON

C G . BELL and

A. NEWELL

P.J. BROWN

M. CAMPBELL-KELLY

O.J. DAHL E.W. DIJKSTRA C.A.R. HOARE

E.W. DIJKSTRA

INTEL

INTEL

D. LEWIN

MOTOROLA

Assemblers and Loaders, American-Elsevier,

(1969).

Computer Structures : Readings and Examples,

McGraw-Hill, (1971).

Macroprocessors and Techniques for Portable

Software, Wiley,(1975).

An Introduction to Macros, American-Elsevier*

(1973).

Structured Programming, Academic Press»

(1972).

A Discipline of Programming, Prentice-Hall,

(1976).

8008 User Manual·,(1972).

8080 User Manual,(1974).

Theory and Design of Digital Computers, Nelson,

(1972).

6800 Systems Reference and Data Sheets* (1974).

FOR FURTHER READING

C G . BELL, J. GRASON

and A. NEWELL

C.C. CLARE

S.S. HUSSON

J.D. NICOUD

J.L. OGDIN

Designing Computers and Digital Systems,

Digital Press, (1972).

Designing Logic Systems using State Machines,

McGraw-Hill, (1973).

Microprogramming : Principles and Practices,

Prentice-Hall, (1970).

Common Instruction Mnemonics for Microprocessors,

Euromicro Newsletter, April (1975), pp.22.

A Survey of Existing and Advanced Microprocessors,

Proc. Journée d'Electronique, Oct. (1974).

138

Glossary

Accumulator: A register in which the result of an arithmetic operation

is deposited. Frequently part of the arithmetic unit of the computer.

Addressing Modes: Different methods for specifying the address of an

operand to be used in an instruction. Much of the power of a processor

depends on the addressing modes available.

Assembler: The program which translates from mnemonic code to machine

code.

BCD: Binary Coded Decimal is a method of representation where four bits

are used to represent each decimal digit in the number.

Bit: Binary digit. The basic unit of information in a computer, having

two possible values, represented by 0 and 1.

Bus: A common set of signals that interconnect many devices so that

any device may communicate to any other.

Byte: A unit of information normally comprising of 8 bits.

CAM: Content Addressable Memory is a memory whose locations are identified

by their content, rather than their address.

Code: A representation of information.

Condition flags: Single bits which 'remember' the result of the previous

operation. Flags are normally used to indicate zero, carry, sign,

overflow, etc.

Compiler: A program which translates a high-level language into a

low-level language.

CPU: Central Processing Unit, the unit which co-ordinates and controls

the activities of all the other units and performs all the logical and

arithmetic processes to be applied to data. It comprises internal

memory, arithmetic unit, and a control section.

Cross-: Software which runs on one computer producing output which

will run on another, e.g. cross-assembler.

139

140 Glossary

DMA: Direct Memory Access, a technique by which data may be transferred

to and from main memory without involving the central processing unit.

ECL: Emitter Coupled Logic, a high-speed logic family.

Flow chart: A graphical representation of the interaction between parts

of a problem.

Functional memory: Equivalent to a Programmable Logic Array.

Hardware: That part of a computer system implemented by electronic

circuitry.

Hexadecimal : A number system based on the radix 16, i.e. 0,1,2,3,4,5,6,

7,8,9,A,B,C,D,E,F,10,11... .

High-level language: A language in which each statement corresponds to

several machine code instructions. Statements bear some resemblance to

spoken language.

Index register: A register which holds a modifier to be used indirectly

to access data normally in a table.

Instruction: The bit pattern which drives the 'central processing unit'

(CPU) comprising an operation code and (possibly) some operands.

Instruction set: The repertoire of operations available from a particular

computer.

Interpreter: A program which directly executes instructions in a given

language on some specified hardware.

Interrupt: A break in the execution of a program which requires that

control should pass temporarily to another program, e.g. a peripheral

device demanding attention.

I/O ports: InputrOutput registers which allow the central processing

unit to communicate with peripherals.

K.: Multiples of 4024, e.g. 2K = 2 χ 1024.

LSI: Large Scale Integration, integrated circuit technology which has

more than 100 gates on a single silicon chip.

Literal : Any symbolic value which represents a constant, rather than

the address of a location in memory.

Low-level language: A language in which each statement translates into

a few machine code instructions, typically one or two.

141 Glossary

Macroprocessor: A program which effects textual substitution by replacing

one source instruction by many object instructions.

Machine code: A representation of the bit pattern of an instruction,

normally in octal or hexadecimal.

Memory: An array of registers used to store the program and operands for

use by the central processing unit.

Microprocessor: A processing unit constructed as one or more chips,

using LSI.

Microprogramming: The technique of programming a computer at a level

under that of the normal machine instructions, i.e. each machine instruction

is several microcode instructions.

Mnemonic: An aid to memory; a mnemonic here refers to a symbolic character

string used to represent the machine code of a computer.

MOS: Metal Oxide Semiconductor, refers to the structure of the transistor

used in an integrated circuit. Used to distinguish it from conventional

(bipolar) transistor.

MSI: Medium Scale Integration, integrated circuit technology which has

between 20 and 100 gates on a single silicon chip.

Object code: The output from a translator, frequently machine code.

Octal : A number system based on the radix 8, i.e. 0,1,2,3,4,5,6,7,10,

11,... .

Operand: The data, identified by part of the instruction, used by the

operator.

Operator: That part of the instruction which defines the operation to

be performed.

Peripheral : Any device that is connected to a computer whose activity

is under the control of the computer.

Processor: Any device capable of carrying out operations on data.

Program counter: A register containing the address of the next

instruction to be obeyed.

PLA: Programmable Logic Array, a regular array of memory cells used

to implement combinatorial logic functions. The address decoder of

the PLA is non-exhaustive.

142 Glossary

RAM: Random Access Memory is memory in which all locations may be

accessed in any random order. Now synonymous with RWM.

Register: A storage unit of one or more bits; frequently refers to

special locations in the processor.

ROM: Read Only Memory is memory which may be read, but not written,

and hence normally contains instructions or permanent data (e.g. look-up

tables, character converters).

RWM: Read Write Memory is a memory which may be written and read, and

is used to store information that is modified by a program. Has become

synonymous with RAM.

Simulator: A device, either in hardware or software, which imitates

the action of some process.

Software: That part of a computer system realized by programs.

Source code: The input to a translator.

Stack: A storage mechanism which works on the basis of Last In, First

Out (LIFO).

Structured programming: A methodology of designing computer programs.

Subroutine: Part of a program which performs some logical part of the

overall task. It normally has some well-defined structure in any

particular programming language.

Word: A unit of information normally comprising of one or more bytes

(See 'Bit" 'Byte»).

2's Complement: A number representation scheme used in the arithmetic

unit of a computer.

6800: An 8-bit N-MOS microprocessor, first produced by Motorola.

Also being produced by other manufacturers and becoming an accepted

standard.

8080: An 8-bit N-MOS microprocessor, designed to supersede the 8008

and upwards compatible with it. One machine that is becoming an industry

standard, and produced by many manufacturers.

8008: An 8-bit P-MOS microprocessor, first introduced by Intel.

Appendix 1 : Instruction Sets

Summaries of the complete instruction set of the three microprocessors

referred to in this book are presented in Figs. Al.l to A1.5.

The beginner is advised to restrict himself, in the first instance,

to the use of the 8008 in attempting program examples, since a complete

description of this machine is provided.

The worked examples which use the 6800 or 8080 can be followed from

the instruction sets provided here (Figs Al.3-5), but more details are

given in the manufacturers' literature (Intel 1974, Motorola 1974).

INSTRUCTION SET FOR 8008

The instruction set provides the information required to program a

problem and write the octal code ready for loading into the microcomputer.

Key to Figs Al.l and A1.2.

Assembler Mnemonic

The symbolic representation of the instruction is shown in this column.

A letter that is underlined is replaced by one of the symbols shown in

the key (e.g., in the order L R-R2» if the operation required is move

data from C to L, then the symbolic code is LLC). An operand that is

specified in the symbolic code represents a numeric quantity or a label.

Octal Code

The numeric representation of the instruction is shown in this column.

Orders of 1, 2 and .3 bytes are possible, and the symbol B used to show

the 2nd and 3rd bytes. An underlined symbol is replaced by the numeric

value of the symbol used in the mnemonic. (For example (i) the mnemonic

LLC is derived from the code 3 D S, where D is register L, number 6, and

S is register C, number 2, and the order is 362; (ii) LMI Y has code

076 BEtè where BEtè is the octal value of Y.)

143

144 Appendix 1

The 2nd and 3rd bytes of an order are generated from the symbolic or

numeric operand used in the mnemonic.

Execution lime (EX Time)

The numbers in this column are the times taken to execute the order.

Where two numbers are present, the first is the time taken if the test

is successful, the second is the time taken if the test is unsuccessful.

(For example JTZ AD takes 44 ys when the zero flag is set, and 36 ys

if the zero flag is not set).

Operation

A brief description of the instruction operation is given in this

column.

(Figures follow)

REGISTER ORDERS

ACCUMULATOR ORDERS

(Acc)

1 Assembler

1 Mnemonic

L »1 «2

1 L R M

1 L M

R

1 L R

I

Y

L M I

Y

I N R

OCR

Octal Code

1

3 DS

3 D_ 7

3 7 S

006

0 7 6

000

0 D 1

2

BBB

BBB

Ex Time

y s

20

32

28

32

36

20

20

Load register R, with

the contents of

register R»

Load register R with

the contents of

memory location

Load memory location

with the contents of

register R.

Load register or

memory with the

data (BBB)

Increment register R

Decrement register R

orl

7

1*1 ,

R 2,£

A

B

C

D

E

H L

D or S

0

1

2

3

4

5

6

BBB

Second byte of instruction

is the octal value of

Y

M

implies a location in memory

the address of which 1s speci-

fied by the contents of H.L

combined.

Flag operations Orders INR and

DCR affect the flags Z , S , P ,

the rest of the above have no

effect on any flags.

ROTATE ORDERS

Assembler

1 mnemonic

R L C

R R C

R A L

RAR

Octal Code

1

002

012

022

032

Ex. Time

ys

20

20

έύ

20

Operation

Rotate the contents of

Acc

left.


Acc

right.


the Acc

left or right

through the carry flag.

Assembler

mnemonic

[ A

D £

ADM

A D I

Y

A C R

A C M

A C I

Y

SUR

SUM

S U I

Y

S B R

S B M

S B I Y

N D

R

N D M

N D I

Y

XRR

X R M

X R I Y

0 R

R

0 R M

0 R I

Y

c p £

C P M

C P I

Y

Octal Code

1

20 s;

207

004

21 S

217

014

22 S

227

024

23 S

237

034

24 S

247

044

25 S

257

054

26 S

267

064

27 S

277

074

2

BBB

BBB

BBB

BBB

BBB

BBB

BBB

BBB

Ex. Time

ys

20

32

32

20

32

32

20

32

32

20

32

32

20

32

32

20

32

32

20

32

32

20

32

32

Operation

Add the contents of R, M

or data BBB to the Acc.

Add with carry flag the

contents of R, M, and

data BBB to the Acc.

Subtract the contents of

R, M, or data BBB to the

Acc.

Subtract with borrow the

contents of R, M, or data

BBB to the Acc.

Compute the logical

AND

of the contents of R, M,

and data BBB with the Acc.

|

Compute the logical EX. OR

of the contents of R, M or

data BBB with the Acc.

|

Compute the logical INC. OR

of the contents of R, M or

data BBB with the Acc.

|

Compare the contents of

R, M or data BBB with the

Acc.

(performs a subtrac-

tion, which sets flags, then

restores original value to

Acc.) 1

Key 2 :

R, S, M, Y and

BBB

as Key 1.

Flag operation :

All flags are affected by aJJ_ the above

orders.

Flag Operations :The rotate orders affect only the

C

Flag.

Fig

. A

l.l

8008

Re

gis

ter,

ro

tate

, an

d ac

cum

ulat

or

inst

ruct

ion

s

Co

CONTROL ORDERS

INPUT-OUTPUT

Γ Assembler

mnemonic

JMP

Z

JFc

Z

JTc

Z

CAL

Z

CF£

Z

CT£

Z

RET

RF£

RT£

RST

L_

Octal

Code

1

104

1F0

1T0

106

1£2

1T2

007

0F3

0T3

0L_5

2

BBB

BBB

BBB

BBB

BBB

BBB

3

OBjî

OBIÎ

0B£

OB_B

0I3£

OBB

Ex.Time

us 44

44

or

36

44

or

36

44

44

or

36

44

or

36

20

20

or

12

20

or

12

20

Operation

Jump to address OBB. BBB

Jump to address OBB. BBB

if condition £ is false;

otherwise execute next

instruction.

Jump if condition

c

is

true.

Jump to subroutine at

address OBB. BBB.

Save

the contents of P.C. on

stack.

|


address OBB. BBB

if

condition

£ is false.

Jump to subroutine if

condition

£

is true.

Return from subroutine.

Return if condition

£

is false.

Return if condition

£ is true.


1

address

00.0L0

£

C

Z

S P

F_ 0

1

2 3

T 4

5

6 7

condi tion

carry

zero

Sign

Parity

Z is a label whose address

is

OBB . BBB

L

has value

0-7

Assembler

mnemonic

INP

W

(W - 0-7)

OUT

W

(W = 8-31)

Octa.l code

1

1P£

1£P

Ex. Time

us

32

24

Operation

Read the contents of

the Port W into Ace.

Output the contents

of the Ace. to Port W

W

is the decimal value of the port address.

(W)8

is the octal value of W.

PP_

=

(2 x W + 1)8

(e.g., if W = 12

PP = 31)

Some ports have been allocated.

Teletype

IN

W = 0

OUT

W = 16

Console

IN

W = 7 & 6* OUT

W = 30

♦Consoles with LED displays only.

There are three codes for the

Halt

order

HLT

000,

001,

377.

to

Fig

.A1.

2 80

08 C

ontr

ol

and

inp

ut-

ou

tpu

t in

stru

ctio

ns

Appendix 1 147

Mnemonic Descriptio Instruction Codel'l

D6 O5 D4 D3 02 DT 00 Clock (21 Cycles

MOVr l, r2 MOVM.t MOVr.M HLT MVIr MVI M INRr DCRr INR M OCR M AOOr ADCr SUBr

ANAr XRAr ORAr CMPr ADD M ADC M SUB.M SBBM

ANA M XRAM ORAM CMP M AOI ACI

Move register to register Move register to memory Move memory to register Halt Move immediate register Move immediate memory Increment register Decrement register Increment memory Oecrement memory Add register to A Add register to A with carry Subtract register from A Subtract register from A with borrow And register with A Exclusive Or register with A Or register with A Compare register with A Add memory to A Add memory to A with carry Subtract memory from A Subtract memory from A with borrow And memory with A Exclusive Or memory with A Or memory with A Compare memory with A Add immediate to A Add immediate to A with

Subtract immediate from A Subtract immediate from A with borrow And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A

RLC RRC RAL RAR

JMP JC JNC JZ JNZ JP JM JPE JPO CALL CC CNC CZ CNZ CP CM CPE CPO RET RC RNC

Rotate A left Rotate A right Rotate A left through carry Rotate A right through

Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive

Jump on parity even Jump on parity odd Call unconditional Call on carry Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Return Return on carry Return on no carry

0 0 0 0 0 0 0 0

0 S S S

0 S S S

Mnemonic Description Instruction Code Ml

D7 D6 05 D4 03 D2 D, Oo Clock 121 Cycles

RZ RNZ RP RM RPE RPO RST IN OUT LXI B

LXI D

LXI H

LXI SP PUSH B

PUSH D

PUSH H

PUSH PSW

POPB

POPO

POP H

POP PSW

STA LOA XCHG

XTHL SPHL PCHL DAD B DAD D OAD H DADSP STAXB STAXO LDAXB LDAXD INXB INXD INX H INXSP DCXB DCXD DCX H DCXSP CMA STC CMC DAA SHLD LHLD El Dl NOP

Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd Restart Input Output Load immediate register Pair B & C Load immediate register Pair D & E Load immediate register Pair H & L Load immediate stack pointer Push register Pair B & C nn stack Push register Pair D & E on stack Push register Pair H & L on stack Push A and Flags on stack Pop register pair B & C off stack Pop register pair D & E off

Pop register pair H & L off

Pop A and Flags off stack Store A direct Load A direct Exchange D& E, H& L Registers Exchange top of stack, H & L H & L to stack pointer H & L to program counter Add B & C to H & L Add D & E to H & L Add H & L to H & L Arid stack pointer to H & L Store A indirect Store A indirect Load A indirect Load A indirect Increment B & C registers Increment D & E registers Increment H & L registers Increment stack pointer Oecrement B & C Decrement 0 & E Decrement H & L Decrement stack pointer Complement A Set carry Complement carry Decimal adjust A Store H & L direct Load H & L direct Enable Interrupts Disable interrupt No operation

0

0

0

0 1

1

' ' 1

1

' 1

0 0 1

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

0

0

0

0 1

1

' ' 1

1

1

1

0 0 1

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 1 1

1 1 A 0 0 0

0

1

1 0

0

1

1

0

0

0 0 0 0 0 0 1 1

0 0 1 1 1 1 1 1 1 1 1 1 0

3 1 ] 0

0 1

3 1 ] 0 f\ A

1 0

] 0

0

3 0

0 3 0

0

3 0

0

3 0

0

3 0

0

0 1

D 1

0 0 1

a i D 1 1 1 D 1

1 0 0

0 0 1 1 1 a o 1 0 0 0

0 D 1 1 1 D 1 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0

0 0 0 0 0 0 1 0 0 0

0

0

0 1

1

1

1

0

0

0

0

0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0

0

c 0 0 0 0 1 1 1 0

0

0

0 0

0

0

0

0

0

0

0

1 1 1

1 0 0 0 0 0 0

0

N O T E S : 1 . O D D or SSS - 0 0 0 B - 001 C - 0 1 0 D - 011 E - 1 00 H - 101 L - 1 1 0 M e m o r y - 111 A.

2. Two possible cycle times, (5/11 ) indicate instruction cycles dependent on condition flags.

Fig.A1.3 8080 Instruction set (reproduced from Intel Manual with kind permission of the Intel Corporation (UK) Ltd)

148 Appendix 1

ACCUMULATOR AND MEMORY INSTRUCTIONS

LEGEND:

OP Operation Code (Hexadecimal). Number of MPU Cycles;

= Number of Program Bytes; t Arithmetic Plus;

Arithmetic Minus; Boolean AND;

Μςρ Contents of memory location pc

Note - Accumulator addressing mode in

+

0 M

-0 00

Boolean Inclusive OR Boolean Exclusive OR Complement of M,

Transfer Into;

Bit = Zero,

Byte = Zero;

CONDITION CODE SYMBOLS:

H Half carry from bit 3;

I Interrupt mask N Negative (sign bit)

Z Zero (byte) V Overflow. 2's complement

mted to be Stack Pom Carry fro i bit 7

e included in the column for IMPLIED addressing Reset Always Set Always Test and set if ti Not Affected

OPERATIONS

Add

Add Acmltrs Add with Carry

And

Bit Test

Clear

Compare

Compare Acmltrs Complement, t's

Complement. 2's

(Negate)

Decimal Ad|ust, A

Decrement

Exclusive OR

Increment

Load Acmltr

Or, Inclusive

Push Data

Pull Data

Rotate Left

Rotate Right

Shift Left. Arithmetic

Shift Right, Arithmetic

Shift Right, Logic

Store Acmltr.

Subtract

Subtract Acmltrs. Subtr. with Carry

Transfer Acmltrs

Test. Zero or Minus

MNEMONIC

ADDA

AODB ABA

AOCA

ADCB ANDA

ANOB BITA

BITB

CLR CLRA

CLR8 CMPA

CMPB CBA

COM

COMA

COMB NEG

NEGA

NEGB DAA

DEC

DEÇA

DECB EORA

EORB

INC INCA INCB LOAA

LOAB

ORAA

ORAB PSHA

PSHB PULA

PULB

ROL ROLA

ROLB

ROR RORA

RORB

ASL

ASLA ASLB

ASR ASRA

ASRB

LSR

LSRA LSRB STAA

STAB SUBA SUBB SBA SBCA

SBCB TAB TBA TST

TSTA TSTB

IMMEO

OP - =

3B 2 2 CB 2 2

89 2 2 C9 2 2 84 2 2

C4 2 2

85 2 2 CS 2 2

81 2 2 CI 2 2

88 2 2

C8 2 2

86 2 2 C6 2 2

8A 2 2 CA 2 2

80 2 2 CO 2 2

82 2 2

C2 2 2

ADDRESSING MODES

DIRECT

OP - =

9B 3 2

DB 3 2

99 3 2 09 3 2

94 3 2 04 3 2

95 3 2 05 3 2

91 3 2

01 3 2

98 3 2

D8 3 2

96 3 2 D6 3 2

9A 3 2 DA 3 2

97 4 2 07 4 2

90 3 2 DO 3 2

92 3 2 D2 3 2

INDEX

OP - =

AB* 5 2

EB 5 2

A9 5 2 E9 5 2 A4 5 2

E4 5 2

A5 5 2 E5 5 2 6F 7 2

Al 5 2 El 5 2

63 7 2

60 7 2

6A 7 2

A8 5 2 E8 5 i 6C 7 2

A6 5 2 E6 5 2

AA 5 2 EA 5 2

66 7 2

68 7 2

6/ 7 2

64 7 2

A7 6 2 E7 6 2 AO 5 2 EO 5 2

A2 5 2 E2 5 2

60 7 2

EXTND

OP - =

BB 4 3

FB 4 3

B9 4 3 F9 4 3

B4 4 3

F4 4 3

B5 4 3 F5 4 3 7F 6 3

Bl 4 3 Fl 4 3

73 6 3

70 6 3

7A 6 3

B8 4 3

F8 4 3

7C 6 3

B6 4 3 F6 4 3

BA 4 3 FA 4 3

79 6 3

76 6 3

78 6 3

77 6 3

74 6 3

87 5 3 F7 5 3 BO 4 3 FO 4 3

B2 4 3 F2 4 3

70 6 3

IMPLIED

OP - =

IB 2 1

4F 2 1

5F 2 1

11 2 1

43 2 1 53 2 1

40 2 1

50 2 1 19 2 1

4A 2 1

5A 2 1

4C 2 1 5C 2 1

36 4 1 37 4 1 32 4 1

33 4 1

49 2 1

59 2 1

46 2 1

56 2 1

48 2 1 58 2 1

57 2 1

44 2 1 54 2 1

10 2 1

16 2 1 17 2 1

40 2 1 5D 2 1

BOOLEAN/ARITHMETIC OPERATION

(AH register labels

refer to contents)

A ♦ M -A

B + M 8 A + B -A A * M ♦ C -A

B » M <C -B A · M ■ A B · M B A · M

B ' M 00 -M 00 A

00 -B A M

6 - M A B

M - M Ä ·Α B -B

00 - M -M

00 - A - A

00 - B ·B

Converts Binary Add of BCD Characters

.nto BCD Format M - 1 - M

A - 1 - A

B - 1 - B

A © M -A

B © M -B

M + 1 - M

A ♦ 1 - A

B + 1 -B M -A M -B

A + M -A B + M -B

A - I M S P . S P- 1-SP B - MSp , S P- 1 -SP SP ♦ 1 - SP. MSP - A

SP + 1 -SP. MS P- B Ml

A I EHD - 11111111 H-J BJ C b7 — bO M] A [ L-O - ΠΓΓΠΤΤ)—J

BJ C b7 — bO

"1 ■■■-■. . A^ D - 1 1 1 11 1 1 1 1 -0 BJ C b7 bO

M l . r - i . . . - . , . . A> L-H'| [ 1 | 1 1JJ - D BJ b7 bO C Ml Α^ o - i I 3 ~ a Bj b7 bO C

A - M B - M A M -A 8 - M -B

A 8 ·Α

A - M - C -A B - M - C - B A - B 8 -A

M - 00 A - 00 8 - 00

COND

± H

!

H

4^

1

7

CODE REG.

2. N

! ! ·' i

! I R

R R

!

• • •

R

R R

N

2. z

! r

!

I

! S

s s I ! ! J

t

1

1

! J J t

î t

J

t

t J

• • • : t 1

t

t

: t Î j

t

: t t t

t

t

I

: 1 t

1

t

z

J_ V

R

R

R R

R R

R

t

t I

R R R

© Φ Φ î

4

4

4

R

R

© © © R

R

R

R

• • • © © © © © © © © © © © © © © © R R

R R

R R R

V

0

C

I

I

I

I

• • • • R R

R

I

J

! S

S

S

© © © ©

J

R R R |

c\

», cleared otherwise

Fig.Al.4 6800 Accumulator and memory instructions (reproduced from Motorola Manual with kind permission of Motorola (UK) Ltd)

Appendix 1 149

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS

POINTER OPERATIONS MNEMONIC

BOOLEAN/ARITHMETIC OPERATION CONO. CODE REG.

I 5141 3 1 2 1 1 | 0 I

BOOLEAN/ARITHMETIC OPERATION

Compare Index Reg

Decrement Index Reg

Decrement Stack Pntr

Increment Index Reg Increment Stack Pntr

Load Index Reg

Load Stack Pntr

Store Index Reg

Store Steck Pntr Indx Reg-»Stack Pntr

Stack Pntr -► Indx Reg

CPX

OEX

DES INX

INS

LDX

LOS

STX

STS TXS

TSX

X H - M. XL- ( M + I) X - 1 - X

SP- 1-SP

X + 1-»X

SP+1-SP

M - XH. (M + 1 ) - XL M - S P H. (M + D - S PL X H- M . XL- (M + 1) S PH- M , S P L - (M + 1) X - 1 - SP

SP + I - X

M®r

J U MP A ND B R A N CH I N S T R U C T I O NS

COND. CODE REG.

Branch Always Branch If Carry Clear

Branch If Carry Set

Branch If = Zero

Branch If > Zero

Branch If > Zero Branch If Higher

Branch If < Zero

Branch If Lower Or Same

Branch If < Zero

Branch If Minus

Branch If Not Equal Zero Branch If Overflow Clear

Branch If Overflow Set Branch If Plus

Branch To Subroutine

Jump

Jump To Subroutine No Operation

Return From Interrupt

Return From Subroutine

Software Interrupt Wait for Interrupt

BRA

BCC

BCS BEQ

BGE BGT

BHI

BLE

BLS

BLT

BMI

BNE

BVC

BVS BPL

BSR JMP

JSR NOP RTI

RTS

SWI WAI

None

C*0

C*1

Z - 1

N ® V - 0

Z + ( N © V ) -0

C + Z «0

Z + ( N © V ) -1

C + Z -1

N ® V »1

N -1

Z = 0

V *0

V »1

N = 0

See Special Operations

Advances Prog. Cntr. Only

See Special Operations

®-

M

C O N D I T I ON C O DE R E G I S T ER M A N I P U L A T I ON I N S T R U C T I O NS

BOOLEAN OPERATION

Clear Carry Clear Interrupt Mask

Clear Overflow Set Carry Set Interrupt Mask Set Overflow

Acmltr A-»CCR CCR-Acmltr A

CLC CLI

CLV SEC SEI SEV TAP TPA

A-CCR CCR-A

-©-»l«l«H«l·

CONDITION CODE REGISTER NOTES:

(Bit set i true and cleared otherwise) (Bit V) Test: Result = 100000007 (Bit 0 Test: Result = 0ΟΌΟΌΟΌ0? (Bit 0 Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set ) (Bit V) Test: Operand = 10000000 prior to execution? (Bit V) Test: Operand = 01111111 prior to execution?

(Bit V) Test: Set equal to result of N®C after shift has occurred. (Bit N) Test: Sign bit of most significant (MS) byte = 1'

(Bit V) Test: 2's complement overflow from subtraction of MS bytes? (Bit N) Test: Result less than zero? (Bit 15 = 1) (All) Load Condition Code Register from Stack. (See Special Operations)

(Bit I) Set when interrupt occurs. If previously set, a Non Maskable Interrupt is required to exit the wait state. (All) Set according to the contents of Accumulator A.

Fig.A1.5 6800 Index, stack, control and condition f lag instructions (reproduced from Motorola Manual with kind permission of Motorola (UK)Ltd)

Appendix 2: Machine Code Representation

OCTAL MACHINE CODE FOR 8008, 8080

The 8008 and 8080 are 8-bit processors with an address word of 14 bits

and 16 bits respectively. Data and instructions are described in octal

notation, which requires 3 digits to represent the 8 binary bits.

Binary

digits 7 6 5 4 3 2 1 0 (The 1st and 2nd octal digits have

a value in the range 0 - 7 ; the

Octal 3rd 2nd 1st 3rd in the range 0 - 3 ) .

digits

To specify an address, two words are concatenated; the representation

is:

(8080) Binary 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(8008) Binary 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(8008) Octal 5th 4th 3rd 2nd 1st

(8080) Octal 6th 5th 4th 3rd 2nd 1st

Page Line

14 bits are represented by 5 octal digits; 16 bits by 6 octal digits.

This division of the address leads to the notion of a 2 or 3 digit

page address and a 3-digit line address.

(Note: the 2 top bits in a word are ignored in the page address of

the 8008, and usually set to zero).

HEXADECIMAL MACHINE CODE FOR 6800

The 6800 is an 8-bit machine with an address word of 16 bits. Data and

instructions are represented in hexadecimal, which requires 2 digits for

8 binary digits.

Binary

digits 7 6 5 4 3 2 1 0

(The two hexadecimal digits are in

Hexadecimal the range 0 - 9, A - F;)

digits 2nd 1st

150

Appendix 2

Addresses are represented by 4 hexadecimal digits.

Binary

digits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Hexadecimal

digits 4th 3rd 2nd 1st

Appendix 3: Peripheral Interfaces

Many manufacturers are producing special large-scale integrated circuits

to perform input-output functions. They usually connect directly to the

address and data bus of the microprocessor concerned, but can be used

in special applications, or even with other microprocessors.

The most common are parallel and serial interface units. The former

have two or three 8-bit ports which can be programmed for either input

or output operations. The serial devices provide the logic to convert

a parallel word to a serial format for communication purposes (e.g.

teletype or modem). Special control registers inside the device, are

used to specify the mode of operation.

When a peripheral unit is connected to the address bus as image memory

(memory mapped), or as special input-output memory, then the input-output

ports and the control registers can be accessed by program.

Before running a program, all input-output channels using a peripheral

device must be programmed for the correct mode of operation. This is

usually done by a special subroutine which initializes the input-output

device. The contents of the input-output routine are unique to a particular

device, and an example of a routine for the MC 6820 peripheral interface

adaptor is shown in Fig. A3.1. The register allocation is shown in

Fig. A3.2.

The detailed operation of these devices is adequately described in the

manufacturer's literature. Examples of devices are:

Parallel interfaces : MC 6820, C 8255, TMS 5501

Serial interfaces : MC 6850, C 8251, TMS 5501

(TMS 5501 has combined parallel and serial facilities)

152

Appendix δ 153

Assembly

LDA STA STA STA STA LDA STA STA LDA STA STA LDA STA STA STA STA RTS

A A A A A A A A A A A A A A A A

Code

#28 8009 800B 800D 800F #00 8008 800C #FF 800A 800E #2C 8009 800B 800D 800F

Comments

SET CONTROL WORDS FOR WRITING DIRECTION TO PORTS 1 to 4.

SET PORTS 3 AND 4 TO INPUT MODE

SET PORTS 1 AND 2 TO OUTPUT MODE

SET CONTROL WORDS FOR NORMAL ACCESS TO PORTS 1 AND 4

Address

0100 0102 0105 0108 010B 010E 0110 0113 0116 0118 011B 01 IE 0120 0123 0126 0129 012C

Machine Code

86 B7 B7 B7 B7 86 B7 B7 86 B7 B7 86 B7 B7 B7 B7 39

28 8009 800B 800D 800F 00 8008 800C FF 800A 800E 2C 8009 800B 800D 800F

(Hexadecimal used throughout)

Fig.A3.1 Subroutine to i n i t i a l i z e two MC 6820 PIA's

Address Hexadecimal

8008 8009 800A 800B 800C 800D 800E 800F

Port A Control Port B Control Port A Control Port B Control

A

B

A

B

Fig.A3.2 Memory map for PIA's

Appendix 4: Peripheral Hardware

In the examples in Chapters 3, 8, and 10, many peripheral hardware

systems are mentioned. The specifications of the modules and their

wiring details are given below (Figs. A4.1-7).

The peripheral components are mounted on printed circuit boards

which are plugged into a card frame mounted on a logic tutor. The

connector numbering refers to the pins on the connector blocks.

Connections between the module and the input output ports are made by

using patchcords.

Pin connections:

Bi t 0

Bank C B

6800

8008,8080 Memory Mapped

Output Port 8 800A

Output Port 12 800E

Input Port 2 8008

Input Port 4 800C

Fig.A4.1 Input-output ports

Input

5 4 3 2 1 0

0 0 0 0 0 0

1 0 0 0 0 0

i i i î i i

Output

V o

* 10V

» 5V

* ov

Fig.A4.2 Digital-to-analogue converter (6 bits)

154

Appendix 4 155

F — · —

U τ

s R — » ■ —

Bit 0 1

DAC TYPE:-

B i t 7

Input

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

Screened Cable

COMP = Logic ' Γ

= Logic Ό '

Output VDAC

~ + 1 0V

0 V

s - 1 0V

Fig.A4.3 Digital-to-analogue converter (8 bits) and comparator

——

Bi t 0

ADC

TYPE:-

B i t 7

1 m Star t

Range ±10 v

End of Conversion(EOC) START -

EOC

Input Vin

lOv

Ov

- l O v

Output

B i t 7 6 5 4 3 2 1 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0

l y s

Fig.A4.4 Analogue-to-digital converter

,1

K -

V i n „

11

S/H

4" I 2 m

13

14

v out r v

- 1 0 v $ V i n < l O v

Max. f r e q u e n c y 3 KHz

TRACK = ΗθΤϋ

TRACK = I 1 . I 2 + I 3 .

Fig.A4.5 Sample hold module

156 Appendix 4

Flying cables from motor.

Motor coils

-v9-P-Q_H

Fig.A4.6 Stepping motor

B D E F H M N P R S T u V

LAMPS

Bank C

GREEN N & S FILTER S GREEN PEDESTRIAN RED FILTER W RED E AMBER E GREEN E RED W AMBER W GREEN W RED N & S AMBER N & S

PUSH BUTTONS

Bank D

J AUTOMATIC CONTROL K PAD L MANUAL R CONTINUE S PAD FILTER S & W T PUSH BUTTON PEDESTRIAN U PAD E - W V PAD N - S

Note: All signals from push buttons are narrow pulses ( < 1 ys)

Fig.A4.7 Traf f ic - l ight board

Appendix 5: Two's Complement

Two's complement is a numbering system used by the CPU to perform

arithmetic operations. The range is:

- 128 < N^ 127 for an 8-bit machine.

Consider 0

Decimal

0

1

2

3

4

5

6

7

to 8:

Binary

000

001

010

011

100

101

110

111

l's compl

111

110

101

100

011

010

001

000

ement 2's compl

000

111

110

101

100

011

010

001

ement Decimal negative and positive

0

-1

-2

-3

-4

3

2

1

To find the two's complement of a number from the binary form, take

the one's complement and add one.

CONVERSION TABLES

The tables below (Figs. A5.1-2) can be used to convert from hexadecimal

to decimal, and back, and from octal to decimal, and back.

Convert to decimal: Taking each digit position in turn, find the decimal

number from the table at the intersection of digit position and digit

value. Sum all the terms for each digit position to obtain the decimal

number.

Convert from decimal: Find the highest number on the table that is less

than, or equal to, the decimal number to be converted. The digit value

and its position are the co-ordinates of the intersection point. (All

the higher digit positions are zero). Subtract the value on the table

from the decimal number and, by using the result as the new decimal

number, repeat the operations from the beginning until all digit values

are found. 157

158 Appendix 5

Hexadecimal D i g it P o s i t i° n

l i t

0 1 2 3 4 5 6 7 8 9 A B C D E F

4th

0 4096 8192

12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440

3rd

0 256 512 768

1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840

2nd

0 16 32 48 64 80 96

112 128 144 160 176 192 208 224 240

Fig.A5.1 Hexadecimal-decimal

Digit Position

Octal d i g i t

0 1 2 3 4 5 6 7

6th

0 16384 32768 49152

----

Page

5th

0 2048 4096 6144 8192

10240 12288 14336

4th

0 256 512 768

1024 1280 1536 1792

3rd

0 64

128 192

----

Line

2nd

0 8

16 24 32 40 48 56

1st

0 1 2 3 4 5 6 7

Fig.A5.2 Octal-decimal

Index

Accumulator, 22,23,82

addressing, 55

Address offset, 56

Addressing modes, 21,50

accumulator, 55

direct, 21,52

immediate, 21,51

indexed, 22,53

indirect, 22,52

inherent, 56

mixed, 60

register, 55

relative, 27,56

Algorithm - design, 41

Analogue-to-digital converter, 132,1

Applications, 39

(see also Worked examples)

Arithmetic instructions, 23

Assembler, 49,90

cross, 91

Assembly -

code, 49,90

directives, 91

Associative store, 13

ATLAS, 68

Bank switching, 65

Base address, 56

Binary operators, 23

Bit, 4

Branch instruction, 56

(see also Jump conditional)

159

Call instruction (see Jump to

subroutine)

Concurrency, 69

Condition -

codes, 28

flags, 24

Conditional jump (see Jump

conditional)

Console, hardware, 111

Content addressable memory, 12

Control circuit, 9

Cross assembler, 91

Debugging, 43, 111

Development system, 111

Digital-to-analogue converter,

132,154,155

interface example, 37

Direct addressing mode, 21,52

Direct memory access, 37,74,70

Dithering staticizers (see

Synchronization glitches)

EAR0M, 67

Flow chart/diagrams, 42,99,129-134

Function, 78

Functional memory, 13

General register, 80

(see also Register

addressing modes) 22,55

Inde Handshake, 35

Hardware -

console, 111

layout, 45

Hexadecimal conversion, 157

High level language, 93

ICE, 113

Image memory, 67

Immediate addressing mode, 21,51,80

In-circuit emulator {see ICE)

Index register, 53,54

Indexed addressing mode, 22,53,81

example, 125

Indirect addressing mode, 22,54

Inherent addressing mode, 56

Input-output, 152

control, 35

data paths, 33

instruction, 30

interface examples, 37

memory mapped,152

[see also Image memory)

Instruction, 50,78,80

format, 20,50

set, 26

Interpreter, 93

Interrupt, 35,70,72

servicing, 59

Jump -

conditional, 28

instructions, 27,50

to subroutine, 28,58

K, 24

Listings, 49

Literal, 80

Load instructions {see Move)

Loader, 92

Look-up table, 40

Machine status, 59

{see also State vector)

Macroprocessor, 93

Macros, 92,94

Memory, 4

mapped input-output, 152

maps, 43,45,121-134

Microcomputer, 17

Microprogramming, 14

Mixed addressing modes, 60

Move operators, 24

Multiple word arithmetic, 24

Nested subroutines, 59

Object code, 49

Octal conversion, 157

Offset, 56

Operand, 78

addressing {see Addressing

modes)

explicit, 82

field, 20

implicit, 62

Operator, 6,78

binary, 23

codes, 24

field, 20

unary, 24

Operators console example, 37

Package pins, 35,62

Peripheral -

interface, 152

hardware, 154

Index Polling, 70

Portability, 90

Problem specification, 43,44,121-134

Processor, 5

basic operation, 19

control signals, 34

data paths, 31

timing, 31

Program -

control instructions, 27

counter, 50,79

design, 41,45,95,97-110,121

listings, 49,121-135

monitor, 113

structuring constructs, 99-100

Programmable logic array, 14

Programmable ROM [see PROM)

Programming languages, 93-95

Projects design, 39,45

PROM, 5,67

Read only memory, 5,11,67

Read write memory, 5,11,67

Re-entrancy, 60

Register addressing modes, 22,55

Relative addressing modes, 56

Return address, 59

store (see Stack)

Return instruction, 28,29

Rotate operators, 24

161 Stack, 57

machine status, 59

operand, 59,82

pointer, 57

return address, 58,84

State vector, 73

Stepping motor, 156

example of, 101

Store operators (see Move)

Structured programming, 97

Subroutine, 28,58,84

Synchronization, 76

glitches (see Dithering

states)

Traffic light board, 156

Truth table, 10

Two's complement, 24,157

ULA, 10

Unary operators, 24

Uncommitted logic array (see

ULA)

V-store, 68

Word length, 5,8,20,77

Worked examples, 43,101,121-135

Sample hold module, 155

Shift operators (see Rotate operators)

Signal processing, 40

Simulator, 92,112

Software support, 38,45

Specifications (see Problem

specifications)

162

6800 Comparison charts, 86,88

Condition codes, 28

Control instructions, 30

Input-output, 31,34,152

Instruction set, 148

Machine code representation, 150

Memory operand addressing, 23

Operator instructions, 26

Operators, 24

Register addressing, 23

Stack, 57

8008 Address format, 21

Comparison charts,85,87

Condition codes, 28

Control instructions, 29

Input-output, 31,33



Memory operand addressing, 22

Operator instructions, 26

Operators, 24

Register addressing, 22

Stack, 57

8080 Comparison charts, 85,87



Stack, 57

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