introduction to digital circuits - jyväskylän...

©Loberg

Introduction to Digital Circuits Basic Logic Circuits The CMOS NOR Gate

A

B

BAY +=

DDV+NMOSPMOS LWN5.2

LW

≈

A

B

BAY +=

DDV+N= number of inputs

1

INTRODUCTION TO DIGITAL CIRCUITS

A

B BAY ⋅=

DDV+ NMOSPMOS LW

N5.2

LW

≈

N= number of inputs

The CMOS NAND Gate Basic Logic Circuits

©Loberg 2


Pull-up network

PMOS devices

Pull-down network NMOS devices

Y

YA

A

B

B

DDV+

Y

A general CMOS logic gate. Both the pull-up and pull-down networks have the same inputs.

The pull-up and pull-down networks must have complementary Boolean functions.

Example function :

( )DCBAY ⋅+⋅=

( ) ( )DCBADCBAY +⋅+=⋅+⋅=

and its complement

For the pull-up

For the pull-down

Complex CMOS Gates Basic Logic Circuits

©Loberg 3


Subnet CD has series connection

Subnet B has parallel connection with CD

Subnet A has series connection with previous parallel net

( )DCB −

( )DC −

( )( )DCBA −−

It can be shown that the pull-up and pull-down networks of a complementary CMOS structure are dual networks.

(De Morgan)

A parallel connection of transistors in the pull-up network corresponds to a series connection of the corresponding devices in pull-down network, and

vice versa.

Pull-up network :

Pull-down network : Subnet CD has parallel connection ( )DCSubnet B has series connection with CD ( )( )DCB −Subnet A has parallel connection with previous net

( )( )DCBA −

A

B

Y

DDV+A

B

C

C

D

D

( )DCBAY ⋅+⋅=Pull-up network

Pull-down network ( )DCBAY +⋅+=

Basic Logic Circuits Complex CMOS Gates

©Loberg 4


Example function :

ABY +=

ABABY ⋅=+=

B A Y 0 0 1 0 1 1 1 0 0 1 1 1

ON

ON OFF

OFF

1Q 2Q 3Q 4Q 5Q 6Q

ON OFF

ON

ON ON ON ON

OFF

OFF

OFF

OFF OFF

OFF PD PU

OFF OFF

OFF

OFF

ON

ON ON ON

OFF

OFF ON

ON ON

ON OFF

PU=Pull-up PD=Pull-down

Basic Logic Circuits Complex CMOS Gates

©Loberg 5

A

DDV+

B

A

A

BABY +=

6Q

5Q

4Q3Q1Q

2QPD

PU


Parallel connected NMOS and PMOS transistor, controlled by the C and comlement of C respectively.

NMOS

PMOS C

C

A B

A B

C

C

S D

CMOS Transmission Gate Basic Logic Circuits

©Loberg 6


Assumption: C = -1- ( )1Vv 1G =( )0Vv 2G =

If A = -1- = V(1) ⇒ ( ) ( ) 01V1Vv 1GS =−= NMOS is cutoff

( ) ( ) TO2GS V0V1Vv >−= PMOS conducts

If A = -0- = V(0)

( ) ( ) TO1GS V0V1Vv >−=⇒ NMOS conducts

( ) ( ) 00V0Vv 2GS =−= PMOS is cutoff

NMOS

PMOS C

C

A B

G1

G2

( )1V

( )0V

( )1VS D

NMOS

PMOS C

C

A B

G1

G2

( )1V

( )0V

( )0VS D

Basic Logic Circuits CMOS Transmission Gate

©Loberg 7


Assumption: C = -0- ( )0Vv 1G =( )1Vv 2G =

If A = -1- = V(1) ⇒ ( ) ( ) 01V0Vv 1GS <−= NMOS is cutoff

( ) ( ) 01V1Vv 2GS =−= PMOS is cutoff

If A = -0- = V(0) ( ) ( ) 00V0Vv 1GS =−=⇒ NMOS is cutoff

( ) ( ) 2G2S vv1V0V <⇒< PMOS is cutoff

NMOS

PMOS C

C

A B

G1

G2

( )0V

( )1V

( )1VS D

NMOS

PMOS C

C

A B

G1

G2

( )1V

( )0V

( )0VS D


©Loberg 8


A B

C

C−−== 1CwhenBA

Transmission gates

ov

A

B

DDV+S

S

S

( )SBSAF ⋅+⋅=

S

1AF

B 0

Example of two-input multiplexer


©Loberg

ov

9


FCT ACL

CD4000 HC

LVC LV CBT

AHC GTLP

VME ALVC

Little Logic AVC

CB3x PCA/PCF

AUC AUP

LVCxT AUP1T

AVCxT

CBTLV TVC

Obsolescence Decline Maturity Growth Introduction

Product Life Cycle

AHC Advanced High-speed CMOS - for example 74AHC30 HCT High-speed CMOS, TTL compatible AHCT Advanced High-speed CMOS, TTL compatible - for example 74AHCT30

1.8V

3.3V

CMOS Families

HC High-speed CMOS - for example 74HC30

AUC Advanced Ultra-low-voltage CMOS : 0.8-2.5V

Basic Logic Circuits

©Loberg 10


inVanywithA1I µ±=Imax

V55.4VCC −=

"Power-supply Standards"

5V 3.3±0.3V 2.5±0.2V 1.8±0.15V 1.5±0.1V 1.2±0.1V

maxILV

minIHV

maxOLI

maxOLV

maxOHI

minOHV

HC AHC HCT 1.35V 1.35V

AHCT 0.8V 0.8V

3.85V 3.85V 2.0V 2.0V

0.02mA 0.02mA 0.05mA 0.05mA

0.1V 0.1V 0.1V 0.1V

-20µA -20µA -50µA -50µA

4.4V 4.4V 4.4V 4.4V

An example of input- and output specifications for CMOS families : HC, AHC and AHCT.

With CMOS load From book : Digital Design John F. Wakerly

Basic Logic Circuits CMOS Families

©Loberg 11


Diode logic Diode-transistor logic (DTL) Transistor-transistor logic (TTL) Emitter-coupled logic (ECL) BiCMOS logic

Bipolar Logic Basic Logic Circuits

©Loberg 12


AND gate

CCV+

A

B

Y

GND

Inputs Output

0 0 0 0 1 0 1 0 0 1 1 1

Truth table : AND gate

If diode gates are cascaded, the gate needs transistor amplifier to restore logic levels.

inverter

Diode Logic

Basic Logic Circuits Bipolar Logic

©Loberg 13


A

B

Y

GND


©Loberg

Diode Logic OR gate

14


Assumptions :

Cut-in voltages :

transistorforV5.0V =γ

diodeforV6.0V =γ

Transistor voltages :

V7.0V )on(BE =V8.0V )sat(BE =V2.0V )sat(CE =

V2.0V)0(V )sat(CE ==

V0.5V)1(V CC ==

NO output load

B

E

Y

D2 D1 P

R1 (5kΩ)

R2 (5kΩ)

I1 I2

RC (2.2kΩ)

B

A

C

IB IC

5V CCV+


©Loberg

Diode-Transistor Logic DTL NAND gate

15


One input, C, is V(0)

⇒V9.0V7.0VV )sat(CEP =+=

V4.1V7.0V7.0VP =+<⇒

Diodes D1 and D2 are cutoff

V0VBE = V5.0V =< γ

⇒Transistor is cutoff

⇒

V0.5V)1(VY CC ===

Other : don't care

B

E

Y

D2 D1 P

R1 (5kΩ)

R2 (5kΩ)

I1 I2

RC 2.2kΩ)

B

A

C

IB IC

5V CCV+

0.2V


©Loberg


16


B

E

Y

D2 D1 P

R1 (5kΩ)

R2 (5kΩ)

I1 I2

RC 2.2kΩ)

B

A

C

IB IC

5V CCV+

5.0V

Inputs A, B and C are V(1)

⇒ All three input diodes are cutoff

⇒ V2.2VV7.0V7.0V )sat(BEP =++=

⇒

All three input diodes are reverse biased, VD = -2.8V

mA560.0k5

V2.2V5R

VVI1

PCC1 =

−=

−=

Ω

mA160.0k5

V8.0R

VI

2

)sat(BE2 ===

Ω

⇒ A400III 21B µ=−=

If current gain is high enough, the transistor is saturated.

⇒ V2.0V)0(VY )sat(CE ===

mA182.2k2.2

VVI )sat(CECC

)sat(C =−

=Ω

46.5A400

I )sat(C(min)F ==

µβ ⇒ Transistor is saturated.


©Loberg


17


B

E

Y

D2 P

R1 (5kΩ)

R2 (5kΩ)

I1 I2

RC 2.2kΩ)

B

A

C

IB IC

5V CCV+

0.2V

NO output load

Assumption : Diode D1 is removed

Input C is V(0) = 0.2V

⇒ V9.0V7.0V2.0VP =+=

⇒ V3.0V6.0V9.0VBE =−=

V5.0VVBE =< γ

⇒ Transistor is cutoff

V2.0VV BE =−γ ⇒ Noise marginal NML is low, because of missing diode D1


©Loberg


⇒

18


B

E

Y

D2 D1 P

R1 (5kΩ)

R2 (5kΩ)

I1 I2

RC (2.2kΩ)

B

A

C

IB IC

5V CCV+

P 5kΩ

5V

A B

I

N=1 equal inputs

I

I

)1(V

0.2V

Ouput is loaded by the standard load.

VVVY satCE 2.0)0( )( ===


⇒

Input current I

mA820.0k5

V9.0V5k5

VVI PCC =−

=−

=ΩΩ

(Standard Load N=1)

If we assume that )(satCEV is independent of collector current

⇒ mANmANIII satCC 82.0182.2)( ×+=+=

DTL NAND gate


©Loberg


19

0.9V


Output is loaded by the N standard load.

Assumption :

30(min)F =β

mA12A40030II B(min)FC =×== µβ

mA82.0NmA182.2mA12NIII )sat(CC

×+=

=+=

⇒

11=N Fan Out


©Loberg


B

E

Y

D2 D1 P

R1 (5kΩ)

R2 (5kΩ)

I1 I2

RC (2.2kΩ)

B

A

C

IB IC

5V CCV+

P 5kΩ

5V

A B

I

N equal inputs

I

I

)1(V

0.2V

DTL NAND gate

⇒

20


Schotky transistor

Transition time

Saturation mode forward active cut off mode

Transition time of BJT is long because of storage time of minority-carriers

The Schottky transistor is used in digital circuits to increase switching speed.

collector

emitter

base

TTL families 74Sxx 74LSxx 74ALSxx


©Loberg 21


TTL NAND gate

One input is V(0) Other : don't care

Input diodes

vi = 0.2V

⇒VVVVP 4.02.02.0 =+=

Transistor Q1 is saturated (VCE = 0.2V)

⇒Transistors Q2 and Q3 are cut off.

V0.5V)1(VY CC ===

⇒Unloaded output voltage is :

Transistor-Transistor Logic

Multiple-emitter transistor Q1

B

E

Y Q2

Q1 P

R1 (4kΩ)

R2 (5kΩ) RC

(4kΩ)

B A

C

5V CCV+

R3 (1kΩ)

Q3

D1 D2

0.2V


©Loberg

TTL NAND gate

22


B

E

Y Q2

Q1 P

R1 (4kΩ)

R2 (5kΩ) RC

(4kΩ)

B A

C

5V CCV+

R3 (1kΩ)

Q3

)1(VInputs A, B and C are V(1)

Transistor Q1 works in the inverted mode

Emitters of Q1 is reverse biased and collector-base junction is forward-biased. ⇒

⇒Transistors Q2 and Q3 are saturated.

VVVY satCE 2.0)0( )( ===

⇒Unloaded ouput voltage is :

To increasing speed :

We replace the passive pull-up resistor RC by an active pull-up circuit.


©Loberg

Transistor-Transistor Logic TTL NAND gate

⇒

23


B3 E3

Y Q2

Q1 DO

100Ω

B A

C

5V CCV+

Q3

B2

B4

1.4kΩ

1kΩ

4kΩ E4

E2 CL

Y = 0.2V

0.8V

0.2V

1.0V

0.8V 5V

Q4

To increasing speed

We replace the passive pull-up resistor RC by an active pull-up circuit.

Totem-pole output

Diode DO keeps Q4 in cut off mode when output Y is V(0) = 0.2V

Transistors Q2 and Q3 are saturated Q4 is cut off mode



©Loberg

Transistor-Transistor Logic TTL NAND gate with totem-pole output

24


TTL gate

Floating input V(1) +5V

A B

Y

Y A

B

<300Ω Unused inputs must be tied up or down. Noise !


©Loberg

Transistor-Transistor Logic

25

26

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