introduction to cmos process integration. 2 overview: product category source:idc 31 21 18 16 9 =...
TRANSCRIPT
Introduction to CMOS Process Integration
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OVERVIEW: PRODUCT CATEGORY
Source: IDC
31
21
18
16
9
= 100
Discrete
Analog
Logic
Memory
MPU
• Design dominated by leading design houses• Scale wins in fabrication, dominated by 3-5 largest global foundries• Heavy R&D on deep sub-micron technology required
• Intense competition, top 5 players have > 70% market share• Low ROIC, large scale require to play
• Dominated by Intel, AMD, Motorola and IBM• Continuous large R&D investment required
2005 Global market size = RM 235 billion
• Exotic processes involved; should reconsider as capability increases5 Opto-electronics
• Low margin and scale wins in discrete market;
%
• Fragmented market with no dominant player
• Higher margin, especially in niche market
• Longer shelf life (~15 years) compared to digital technology
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OVERVIEW: TECHNOLOGY2005 ITRS Conclusions;
Despite significant technology challenges, the industry continued to maintain the pace predicted by Moore's Law - the doubling of transistors every two years.
Transistor speed continued to improve at the historical improvement rate of 17 percent per year, although the challenges became more complex due to a concurrent increase in leakage currents.
Research intensified on major technology innovations like high-k dielectrics, metal gate electrodes, and multiple-gate MOS transistors, which are forecast to enter manufacturing before the end of the decade. These represent major shifts, where some basic device materials and structures will undergo change for the first time in more than 30 years.
Mixed-signal and analog chips continue to grow in importance, driven especially by consumer and communications-related markets.
State-of-the-art microprocessors now run well in excess of several GHz. Memory designs are geared increasingly to specific applications. And new memory technologies based on totally new concept (spin state, molecular and single electron memory are emerging)
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Foundry (TSMC, UMC, Silterra, 1st Silicon) – only manufacture
Design House (Alterra, MyMS) - only design
Integrated Design Manufacturing (Intel, Motorola, IBM, MIMOS)
- design and manufacture
BUSINESS MODEL
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Design Mask info to MASK-SHOP + GDSII
file Mask making Generate runcard Wafer Preparation Front-end Processes (individual
transistor) Deposition Oxidation Diffusion Photolithography Etch (wet and dry) Implantation
Backend Process Deposition (oxide, nitride etc) Metalization Rapid Thermal Process Lithography & Etch
Test (Parametric and Functional)
Packaging
Semiconductor Manufacturing Processes
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CircuitSchematic
Layout Silicon
pMOS
nMOS
VDD
VSS
S
S
D
D
VIN VOUT
Poly gate
VIN
VOUT
p+
drain
n+
drain
vSS
vDD
nMOS
pMOS
n+
source
p+
source
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SILICON COMPONENTS FOR INTEGRATION
• Contacts
• Resistors
• Capacitors
• P-N Junctions
• Bipolar Transistors
• Uni-polar Transistor (FET)
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CONTACTS
• Are made to connect components to the outside world • Bad contacts are
•Non-ohmic, high resistive•Leaky
• Bad contacts can cause circuit failure • Main causes for non-ohmic behavior
•Contaminated interface•Incomplete contact etch •Low dopant concentration (dopant depletion from Si into silicide
• Main cause for leaky behavior is metal penetration (Al spiking) • Characterized by a parameter called contact resistance (ohm per contact) using test structure called contact chain. Several thousands of contact of different sizes running on different topography.
Height of barrierto carrier flowcarriers
GATE
ILD0
Silicon
AlSiCu
GATE
ILD0
Silicon
AlSiCu
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CONTACTS (continue)
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CONTACTS (continue)
• Ohmic Contact• Formed between metal and heavily doped Si• Barrier exist but is very thin• Carriers tunnel through the carrier• Symmetrical I-V characteristics
• Non-ohmic behavior• High contact resistance• Indication of process problem or bad integration
• Schottky barrier• Formed between metal and lightly doped Si• Wide barrier• Diode I-V characteristics
I
V
ohmic
Non-ohmic
I
VVt (0.3-0.8V)
reverse
forward
BV (>20V)
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RESISTORS • Applications
• Analog mixed signal (RF & wireless application), when high precision and matching were needed.• Current limiter• Voltage drop• Diffused layer (nwell ~ 1000 ohm per square) and poly-1 (~ 35 ohm per square) normally used as resistors
• Parasitic resistance• transistor / IC speed degradation: RC delay
• Source and drain region (salicide, halo implant) • Contact and via (silicide)• Metal lines (copper)
substrateLOCOS
Poly as resistor
substrate
Diffused layer as resistor
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Resistivity
• Resistivity of n-type material is inversely proportional to donor concentration, ND
• µn is electron mobility
ρ = 1 / q µn ND
• Resistivity of p-type material is inversely proportional to donor concentration, NA
• µp is hole mobility
ρ = 1 / q µp NA
• As the temperature increases, the mobility decreases and resistivity increases• shorter carriers mean free path due to lattice atoms vibration
• For the same doping and concentration and temperature, electrons are approximately 3 times mobile (faster) than holes – hence NMOS is 3 times faster than PMOS
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Resistance & Sheet Resistance
• The resistance of a resistor depends on its resistivity, length and cross-sectional are
R = ρ L / A
• Sheet resistance is the most widely parameters. Is defined as the resistance between two opposite sides of a square of the layer. Unit: ohm / □
Rs = ρ / t
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Resistance & Sheet Resistance (continue)
RESISTOR
Typical resistor TOP-VIEW (layout)
L
W
R = Rs x L / (W – ΔW) + 2 x Rc / (W – ΔW)
Rs – Sheet resistance of resistor ΔW – width reduction due to litho / etch L - Drawn resistor length Rc - contact resistanceW – Drawn resistor width
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CAPACITORS
• Applications• Memory and logic (DRAM, E/EEPROM memory cell)• Precision analog design• MOS process characterization• Device characterization, SPICE model extraction and etc.
• Parasitic capacitance• transistor / IC speed degradation: RC delay
• Low-k dielectrics • Thick ILD• Good backend planarization (global planarization)
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CAPACITORS
Conductor-1
Conductor-2Insulator
C = A ε0 εi / t
C – capacitance (F)A – area common to plates (cm2)ε0 - universal constant (8.86 x 10-14 F/cm)
εi - dielectric constant (oxide=3.9, nitride=7)t - dielectric thickness (cm)
t
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CAPACITORS (continue)
TiN, Al
TiSi2, AlOxide or nitride
MIM Capacitor (Metal – Insulator – Metal)
t
Poly
FOX
Silicon substrate
TiSi2
TiN
Parasitic capacitance
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CAPACITORS (continue)
MIM Capacitor (Metal – Insulator – Metal)
Poly
FOX
Silicon substrate
TiSi2
TiN
Parasitic capacitance
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CAPACITORS (continue)
Poly, Metal-1
n-type or p-type SiOxide or oxynitride
MIS / MOS Capacitor (Metal – Insulator – Silicon)
t
FOX
substrate
n-wellGateOx
S/D
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PN JUNCTION
• A pn junction is the boundary between p-type and n-type silicon• Region between n and p is depleted from electrons and holes• Xd is width of depleted region• Depletion region is wider in a lighter doped region.
P-type N-type
Xd
+++
---
NO BIAS
Given NA = 1015 cm-3, ND = 1017 cm-3
For n-type region For p-type regionn=1017 cm-3 (why?) p=1015 cm-3 (why?)What is p (hole concentration)? What is n (e concentration) ?
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PN JUNCTION (continue)
I
VVt (0.8-1.0V)
reverse
forward
• forward bias – large current• electrons are injected into p• holes are injected into n
• reverse bias – small current• electrons are extracted from p-side to n-side• holes are extracted from n-side to p-side
I
V-
+
P
N
I
V-
+P
N
reverse
forward
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PN JUNCTION (continue)
Effect of resistance
IF
A
VF
1 2V
10-11
10-14
10-8
10-5
10-2
Threshold swing> 60mV / decade @ 25C
IR
A
VR
10 20V
10-11
10-8
10-5
10-2
leakage
impact ionization
avalanchebreakdown
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PN JUNCTION (continue)
P
N
FOX
substrate
n-well
p+
FOX
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MOSFETs
4 types of MOSFETs• NMOS
• enhancement mode (normally off)• depletion mode (normally on)
• PMOS• enhancement mode• depletion mode
GATE
N-source
N-drain
P-well orP-substrate
NMOS
GATE
P-source
P-drain
n-well orn-substrate
PMOS
• Mode of operation• To turn on: inversion layer connects S and D• To turn off: no inversion between S and D
• Enhancement mode • Inversion layer is initially absent. To turn on, apply
• Positive voltage on gate of NMOS• Negative voltage on gate of PMOS
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MOSFETs
LAYOUT
Active Region
Poly
Metal-1
Contact
WD
LD
DRAIN SOURCE
Poly extension over LOCOS
Important Note: ALL the dimensions must FOLLOW theDesign Rules
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MOSFETs
CROSS SECTION
WD
LD
DRAIN SOURCE
CUT
LOCOS encroachment into active
PMD or ILD0
Leff Spacer – for LDD (to suppressthe hot electron effect)
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MOSFETsHOW AN ENHANCEMENT MODE NMOS WORKS
PMD or ILD0
Leff
N+ Drain N+ Source
A
ground
VD VG
• With 0 or negative bias on gate, there is no S to D current• With +ve voltage on gate, holes are repelled and e attracted to the surface• With sufficient VG, thin sheet of electron forms between S and D• S and D are now connected• Thin sheet of electrons is called inversion layer• Sufficient VG is called Threshold Voltage, VT
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MOSFETsHOW AN ENHANCEMENT MODE PMOS WORKS
PMD or ILD0
Leff
P+ Drain P+ Source
A
ground
VD
VG
• With 0 or positive bias on gate, there is no S to D current• With -ve voltage on gate, electrons are repelled and holes attracted to the surface• With sufficient VG, thin sheet of holes forms between S and D• S and D are now connected• Thin sheet of holes is called inversion layer• Sufficient negative VG is called Threshold Voltage, VT
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MOSFETsTYPICAL CMOS CROSS SECTION
NMOS and PMOS on the same die to form a basic design block for VLSI technology (inverter). Superior thanNMOS or PMOS process technology in terms of;
• Lower power dissipation• Design flexibility• Compact ability• Noise immunity
pwell nwell
NMOS PMOS
nLDD pLDD
FOXDRAIN DRAIN
Vout
VddGround
Vin
When Vin is high• PMOS is off• NMOS is on• Vout is at ground
When Vin is low• PMOS is on• NMOS is off• Vout is at Vdd
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CMOS PROCESS INTEGRATION
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Unit processes, modules, integration
• Unit processes development•Oxidation, deposition, lithography•Etch, diffusion, ion implantation
• Modules development•Gate stacks, well, isolation, source & drain•IMD, contacts / interconnect
• Integrated Process•CMOS, BiCMOS, EEPROM•Flash, SRAM, DRAM
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TYPICAL CMOS PROCESS FLOW
Main Process Modules (CMOS 1P2M 3.3V)1. Wells Formation2. Active Area Definition 3. Device Isolation (LOCOS)4. Vt Adjust5. Polygate Definition6. Source & Drain Formation7. Pre Metal Dielectrics Deposition (PMD)8. Contact Definition9. Metal-1 Deposition & Patterning10. Inter-Metal Dielectrics Deposition (IMD)11. Via Definition12. Metal-2 Deposition & Patterning13. Passivation14. Pad Definition
Full integration may require 300-500 process steps
FRONT END PROCESS(creating an electrically isolated devices)
BACK END PROCESS(connecting the devices to form the desiredcircuit function.)
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DEVICE ISOLATION TECHNOLOGY
• Electric circuit in VLSI technology is implemented by connecting isolated devices through specific conducting path. • To fabricate monolithic ICs, electrically isolated devices must be created in the silicon substrate.• Only later they are connected.• Improper isolated device will result;
• total circuit failure• high leakage (large dc power dissipation)• noise margin degradation• voltage shift, cross talk between transistors and etc.
• The challenge is VLSI device only allows single transistor leakage < 10 pA/um). On the other hand, process integration imposed a stringent requirement on the isolation technology;
• spacing between actives should be as small as possible• to produce the surface topography as planar as possible• isolation process module must be simple to implement and easy to control
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DEVICE ISOLATION TECHNOLOGY
MOS transistors are self isolated as long as;• The source-substrate and drain-substrate pn junctions are held at reverse bias
• Reverse bias drain-substrate leakage should be negligible• Insignificant drain-source current during OFF state
• Parasitic channels are prevented from forming among adjacent devices• Negligible leakage current between adjacent MOS devices
MOS Device Isolation Characteristics
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DEVICE ISOLATION TECHNOLOGY
• VTF is the threshold (minimum) voltage to turn on the parasitic MOS (field transistor)• 2 methods of increasing the VTF;
• making a thicker field oxide• Increase the doping beneath field oxide (channel stop implant)
MOS Device Isolation Characteristics
NMOS#2
DRAIN SOURCE
NMOS#1
M-1
Field transistor
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DEVICE ISOLATION TECHNOLOGY
Isolation technique in CMOS• Grow and etch thick oxide• Semi recessed LOCOS
• Conventional• Poly buffered• SILO and etc
• Fully recessed• Trench
oxidation
nitride removal
oxidation
nitride removal
a) Grow and Etch
b) Semi recessed LOCOSc) Fully recessed LOCOS
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DEVICE ISOLATION TECHNOLOGY
A) Grow and etch (used until late 70s)
• Thick oxide is grown thermally in the furnace• Wafer is patterned and etch
Disadvantages
• Sharp corners, difficult to cover in the latterprocess steps
• Channel stop must be implanted before oxideis grown (active to be aligned with channel stopregion – low packing density)
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DEVICE ISOLATION TECHNOLOGY
B) Semi-recessed LOCOS
Conventional LOCOS• 20-60nm oxide is grown [pad oxide]-to cushion stress
of nitride• 100-200nm CVD nitride is deposited as oxidation
mask. Nitride is very good in this as oxygen andwater vapor diffuse very slow through it. Butvery high tensile stress
• Mask to define active regions• Channel stop implant – desirable to implant after
LOCOS oxidation• Grown thick oxide using wet oxidation
• Boron segregation and lateral diffusion• Bird’s beak
• Strip oxide and nitride using wet etch
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DEVICE ISOLATION TECHNOLOGY
C) Advance Semi recessed LOCOS
a) Etch back LOCOS• The simplest way to reduce bird’s beak• A portion of LOCOS is etched after oxidation
b) Poly buffered LOCOS• Use thinner pad oxide [poly 50nm,oxide 10nm]
and thicker nitride• Solve the bird’s beak issue, do not solve
planarization.
D) Fully recessed LOCOSQuiz: Write an essay on a Fully recessed LOCOS isolation technology used in CMOS wafer fabrication process.
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DEVICE ISOLATION TECHNOLOGY
Integration Issues with Thermally Grown Oxides
• Contamination, ionized impurities• Bulk & interface traps• Pinholes• Uniformity• Thermal budget• Induced defects• Impact on dopant profile• Stress
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DEVICE ISOLATION TECHNOLOGY
E) Trench Technology4 major applications• Locos replacement for isolation within the well• Isolation in bipolar• Latch prevention in CMOS• Trench capacitor in DRAM
3 categories• Shallow trench <1 um• Moderate 1-3 um• Deep >3um deep
AdvantagesIncrease the packing density tremendously
DisadvantagesComplex to fabricate, very expensive machinesPoor uniformityLow throughput
Trench etched
CVD oxide deposited
Oxide polished to surfaceby CMP
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MULTI LEVEL INTERCONNECT TECHNOLOGY
The requirement is to connect the device electrically at the later stages of wafer fabrication in order to implement the desired circuit functionality.
2 major components• Multilevel Metallization• Multilevel Dielectrics
Contribute to ~75% low yield problem
WHY MULTILEVEL INTERCONNECT???
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MULTI LEVEL INTERCONNECT TECHNOLOGY
gate
passivation metal
BPSG FOX
Nomenclature in IC Application
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MULTI LEVEL INTERCONNECT TECHNOLOGY
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MULTI LEVEL INTERCONNECT TECHNOLOGY
MULTILEVEL METALIZATION
Low resistance materials Low contact resistance Electrically stable Good step coverage (bottom and sidewall) for non plug process Process compatibility and cost effective
Stress Adhesion to oxide Electro migration Easiness to pattern and etch
General Requirement
W
Film
good
bad
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MULTI LEVEL INTERCONNECT TECHNOLOGY
Materials and Application
Material Application Technology(m)
Al, AlSiCu Interconnect 1.0, 0.5, 0.35 2.65
Cu Interconnect 0.25, 0.18 1.67
Ti Adhesion (Al, Cu)0.5, 0.35, 0.25 43
TiN Barrier, ARC 0.5, 0.35, 0.25 25
TiW Adhesion (W) 0.5, 0.35, 0.25 75
W Via Plug 0.5, 0.35 6
ρ (-cm)5000A
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MULTI LEVEL INTERCONNECT TECHNOLOGY
Aluminum still the metal of choice High conductivity Process compatibility
Al drawback Electro migration due to small grain size. Add copper (1-1.5%) Incompatible with >500C process
Copper Higher conductivity than Al Better electro migration resistance Difficult to etch. To use other difficult technique (damascene process)
General Conclusions
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MULTI LEVEL INTERCONNECT TECHNOLOGY
MULTILEVEL DIELECTRICS
Ability to electrically isolate two levels of metal Ability to planarise, minimize the possibility of open circuits for the subsequent metal Chemical and thermal stability during subsequent process step Repeatable and reliable Good adhesion to underlying layers Ability to produce layers of varying thickness Process compatibility Deposition temperature Low k
General Requirement
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MULTI LEVEL INTERCONNECT TECHNOLOGY
MULTILEVEL DIELECTRICS
CVD oxide 400C PECVD oxide / nitride 200C SOG 27C , 450C cure Polyimide 27C, 400C cure
Dielectric Materials
Deposit and etch-back Deposit and CMP
Planarization Methods
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MULTI LEVEL INTERCONNECT TECHNOLOGY
Major Reliability Issues
Metalization ESD• electro migration Latch-up• stress• corrosion
Transistors• hot carrier effects
Junctions• leakage, shorts
Dielectrics• leakage • breakdown, surface states, traps
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FUTURE TRENDS/ISSUES IN INTEGRATION
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FUTURE TRENDS/ISSUES IN INTEGRATION
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