introduction ee603

8/9/2019 Introduction EE603

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EE603

CMOS INTEGRATED CIRCUIT DESIGN

COURSE : EE603 CMOS INTEGRATED CIRCUIT DESIGN

INSTRUCTIONAL DURATION : 15 WEEKS

CREDIT(S) : 2

PRE REQUISITE(S) : NONE

SYNOPSIS

CMOS INTEGRATED CIRCUIT DESIGN course exposes the students to the basic

principles of CMOS interated circuit desin! "ith co#prehensi$e o$er$ie" of theMOS%ET transistor theor&' %urther#ore! the students "ill be e(uipped "ith the

)no"lede to desin nucleus of diital desin! the in$erter! and desinin si#ple to

co#plex diital CMOS ates' %inall&! the students "ill experience de$elopin the ph&sical

la&out of an interated circuit usin CAD tools co#pl&in "ith specific

desin rules'

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Lecturer : E! S"#$%e# N$%$r$&$'P'(e ): 0*+,-.6.//E1$"2 ID: 3"#$%e#45$'((!c(1



COURSE LEARNING OUTCOMES (CLO)

Upo !o"p#$%&o o' %& !o*+$, %*-$% o*#- .$ /.#$ %o:

*' explain correctl& the basic principles of interated circuit desin!

desin #etrics! desin #ethodolo& and desin hierarch& of CMOS

IC desin' +C,-

,' explain clearl& the operation theor& and transistor characteristics of

MOS and CMOS transistors' +C,-

.' construct the basic loic ates usin static and d&na#ic CMOS

techni(ues'+C.-

/' dra" the la&out desin of a CMOS circuit usin la&out desin soft"are

based on specific CMOS la&out desin rules' +0.-

1' perfor# co##unication s)ill throuh oral presentation on a i$en topic' +A,-

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SUMMARY (30 LECTURE : 30 PRACTICAL)

RTA

10 INTRODUCTION TO INTEGRATED CIRCUIT (02 : 00)

E$olution in interated circuit' %unda#ental of desin #etrics that o$ern diital desin'

0erfor#ance e$aluation of a diital circuit' Issues in diital desin'

20 MANUACTURING PROCESS (02 : 00)Manufacturin process re$isited' The concept of desin rules' Issues related to desinin

the la&out of an interated circuit'

30 TE DEICE (06 : 04)

Co#prehensi$e o$er$ie" of the operation of diode and MOS transistor' Issues in

Sub2Micron MOS Transistor desin'

0 TE WIRE (0 : 00)

I#pact of Interconnect 0arasitic3 capacitances! resistance and inductance on interated

circuit desin'

50 TE CMOS INERTER (06 : 10)

4oltae Transfer Characteristic of an in$erter' Desin for 0erfor#ance' In$erter Si5in'

0o"er Dissipation' I#pact of Technolo& Scalin'

60 DESIGNING COMINATIONAL LOGIC CIRCUITS (04 : 12)

Static CMOS Circuit' Co#ple#entar& CMOS 6oic St&le' Cell Desin' Rationed 6oic'

D&na#ic 6oic

70 DESIGN METODOLOGY (02 : 00)

Desin hierarch& and #ethodolo&3 standard IC! specific custo# IC! %ull2custo# IC!

se#i2custo# IC! ate2arra&! standard cell! and prora##able loic de$ice +06D-'



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ASSESSMENT

The course assess#ent is carried out in t"o sections3

& Co*+$8o+9 (CA) 50;

Course"or) is continuous assess#ent that #easures )no"lede!technical s)ills and soft s)ills'

&& &/# E</"&/%&o (E) = 50;

%inal exa#ination is carried out at the end of the se#ester'



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REERENCES

Adel S' Sedra and 7enneth Carless' S#ith+,88.-' Microelectronic Circuits. Oxford

Uni$ersit& 0ress

Rabae&! 9' M! Anantha Chandra)asan! :ori$o;e Ni)olic' +,88.-' Digital Integrated Circuit, 0rentice <all! Inc'

U&e#ura! 9' 0' +,88=-' Chip Design for Submicron VLSI ' Nelson! Tho#pson of

Canada 6td'

4'S':aad +,88>-' VLSI Design' Technical 0ublications'

?este! N! Eshrahian'7' +,888-' Principles of CMOS VLSI Design' Addison2?esle&

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introduction ee603

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