international technology roadmap for semiconductors metrology roadmap 2001 update europealain...

International Technology Roadmap for Semiconductors

Metrology RoadmapMetrology Roadmap2001 Update2001 Update

EuropeEurope Alain Deleporte (ST)Alain Deleporte (ST) 4/014/01Alec Reader (Philips Analytical)Alec Reader (Philips Analytical)Vincent Vachellerie (ST)Vincent Vachellerie (ST) 4/014/01Mauro Vascone (ST)Mauro Vascone (ST)

JapanJapan Fumio Mizuno (MEISEI University)Fumio Mizuno (MEISEI University)Mashiko Ikeno (NEW)Mashiko Ikeno (NEW)

KoreaKorea

Taiwan Taiwan Henry Ma (EPISIL)Henry Ma (EPISIL)

USUS Steve Knight (NIST)Steve Knight (NIST)Bob Scace (Klaros Corporation)Bob Scace (Klaros Corporation)Jack Martinez (NIST)Jack Martinez (NIST)Alain Diebold (Int. SEMATECH)Alain Diebold (Int. SEMATECH)


AGENDAAGENDA• Overview 2001

• 2001 Difficult Challenges

• Lithography Metrology

• FEP Metrology

• Interconnect Metrology

• Materials & Contamination Characterization

• Grand Metrology Challenges


New to – New to – Five Difficult Challenges Five Difficult Challenges 65nm / Before 2007 65nm / Before 2007

• Key requirement for Cu/Damascene metrology is void detection in Cu lines and pore size distribution (find killer voids and pores)

• Scribe line shrinkage reduce test structure area making high precision measurements difficult in scribe lines.


SCOPE

• Microscopy

• Control of Statistical Processes

• Lithography Metrology

• FEP Metrology

• Interconnect Metrology

• Materials and Contamination Metrology

• Integrated Metrology

• Standards and Reference Materials


• Determination of manufacturing Metrology when device and interconnect technology remain undefined.

New to – New to – Five Difficult Challenges Five Difficult Challenges 65nm / After 2007 65nm / After 2007


GAPS in FAB Ready Metrology

• 3D CD for Mask and Wafer for lines and

contact/via and long term capability for CD

• Optical and Electrical Metrology that

controls high k plus interface

• Void detection in copper Lines

• Killer Pores in low k

• Sidewall barrier layer control below seed Cu


Difficult Challenges before 65 nm / 2007Difficult Challenges before 65 nm / 2007

• Factory level and company-wide metrology integration

• Impurity detection (especially particles) at levels of interest for starting materials & reduced edge exclusion for metrology tools.

• Control of high-aspect ratio technologies such as Damascene challenges all metrology methods. Key requirements are void detection in copper lines and pore size distribution in patterned low k.

• Measurement of complex material stacks and interfacial

properties including physical and electrical properties.

• Measurement test structures and reference materials.


Difficult ChallengesDifficult Challenges after 65 nm / 2007after 65 nm / 2007

Nondestructive, production worthy wafer and mask level microscopy for critical dimension measurement for 3-D structures, overlay, defect detection, and analysis.

Standard electrical test methods for reliability of new materials, such as ultra-thin gate and capacitor dielectric materials, are not available.

Statistical limits of sub-65 nm process control.

3D dopant profiling.

Determination of manufacturing Metrology when device and interconnect technology remain undefined.


GAPS in Litho Metrology

• Precision of CD-SEM

• Proof of 3D CD for Tilt Beam CD-SEM

• Commercialization of 3D software for top-down CD-SEM

• Depth of Field Issues for CD-SEM

• Reference Materials for 65 nm node and below

• Standard method for Precision of Discrete CD Library

• Probe Tip Technology for CD-AFM

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverLithography MetrologyWafer Gate CD nm post-etch contol 6.5 3.7 2.5 1.8 1.3 0.9 MPU

Wafer CD Tool 3 Precision P/T=0.2 Isolated Lines

1.3 0.75 0.5 0.36 0.26 0.18 MPU

Line Edge Roughness (nm) 4.5 2.7 1.8 1.3 0.9 0.65 MPU

Overlay Control (nm) (mean +3 ) 45 31 26 18 13 9 MPU

Overlay Metrology Precision (nm) P/T=0.1 4.5 3.1 2.6 1.8 1.3 0.9 MPU


Changes to Lithography Metrology Changes to Lithography Metrology

• Accelerated MPU Gate Length dilutes advances in

CD Measurement

– Will 15% Process 3 be adopted??

• Addition of Line Edge Roughness Metrics

• Overlay may face difficulties associated with mixing

exposure tools

– e.g., 2 different 157 nm exposure tools for via & metal

trench (or 157 nm for lines & Electron Projection for Via)


Line Edge Roughness RequirementsLine Edge Roughness Requirements



1.3 0.75 0.5 0.36 0.26 0.18 MPU


Line Edge Roughness Precision 3 (nm) 0.9 0.54 0.36 0.26 0.18 0.13 MPU

Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-1.0 -0.5 .0 .5 1.0 1.5Log Active Width

LER = 10 nmLER = 3 nm

IL @

500

A/

m Id

Line Edge RoughnessCorrelated to

Leakage Current Increase

Patterson, et. al., SPIE 2001

AVE CD = 150 nm


Why are CD Measurement Requirements RED?

• There is no universal metrology solution for all CD measurements.– e.g., Scatterometry meets Focus-Exposure precision

needs to (70 nm node?) for resist lines but not for contacts (yet).

– Can Scatterometry measure LER ?

• 3D info needed for undercut gate, contact, and other structures.

• Precision includes tool matching and near + long term measurement variation.


Gaps in FEP Metrology

• Physical Metrology for high k gate stack– Optical Models for next High k (beyond ZrO2 and HfO2)– Commercial availability of high k optical model in software– Interfacial control for interface between high k and silicon

• Electrical Metrology for high k gate stack– Application of Non-contact C-V to next High k (beyond ZrO2 and

HfO2)– Comparison of non-contact electrical to C-V– USJ Metrology

• Ultra Shallow Junction Metrology (USJ)– Dose/Junction Control– 2D Dopant Profiling with spatial resolution

• Metrology for post CMOS – SOI ; SiGe ; Vertical Transistors

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverFront End Processes MetrologyLogic Dielectric Thick Precision 3 (nm) 0.005 0.004 0.0024 0.0024 0.0016 0.0016 MPU

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

26 14.8 10 7.2 5.2 3.6 MPU


FEP Metrology FEP Metrology

• Optical and Electrical measurement of High can be done for development but needs to be robust for manufacturing

• Metrology for interface below High needs R&D

• USJ Metrology needs development for < 65 nm

• FERAM needs fatigue testing for 1016 read/write cycles


Gaps in Interconnect Metrology

• VOID Detection in Copper lines

• Killer Pore Detection in Low

• Barrier / Seed Cu on sidewalls

• Control of each new Low

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverInterconnect Metrology

Barrier layer thick (nm) process range (±3 ) Precision 1 (nm)

1320%0.04

1020%0.03

720%0.02

520%0.016

420%0.013

MPU

Void Size for 1% Voiding in Cu Lines 32.5 22.5 16.25 11.25 8 5.5 MPU

Detection of Killer Pores at (nm) size 6.5 4.5 3.25 2.25 1.6 1.1 MPU


Interconnect Metrology Interconnect Metrology

• Random isolated void detection (size of 25% of line width) at < 1% in copper lines may not be measurable in-line

• Max Low Pore size of 5% of line width

• Metrology for electrochemical deposition will be included in Metrology Roadmap


Materials Characterization Enables Materials Characterization Enables Process and Metrology DevelopmentProcess and Metrology Development

High Angle - Annular Dark Field STEMHigh Angle - Annular Dark Field STEM

GaAs

EELS Spectrometer

Annular Detector

1.4Å

As Ga

1.3Å Scanning

Probe

Objective Lens

I Z 2

Z=31 Z=33

Electron Beam

Thin Foil Sample

Image Plane

diffracted beammisses annular detector

Enlarged view of Lattice Planes“on axis” to electron beam

scatter from atoms or atomic columns

HA-ADF & EELS

0

500

1000

1500

2000

520 530 540 550 560 570

Interface

7Å from interface

Inte

nsity

(a.u

.)

Energy (eV)

Short term: New Aberration Corrected Lens for STEM/TEM

Long Term: Atom Probe

Dave Muller - Lucent


2001 Grand Challenges2001 Grand Challenges

• Development of Metrology tools in time.

• Rapid non-destructive metrology forCD, overlay, defect detection and line edge roughness that meets ITRS timing and technology requirements.


Will Market Risks allow for innovation?Will Market Risks allow for innovation?

Metrology RoadmapMetrology Roadmap

Metrology Timing Metrology Timing vsvsInfrastructure CapabilitiesInfrastructure Capabilities

Process Tool Supplier Development

Pilot Line FAB Startup & Volume Manufacture

Volume Sales of Metrology Tools

Need for Process Tool

Qualification/Preproduction

Development Underway

Typical Potential Solutions Time Line for Process Tool

Research Required

Need for Metrology Tool

Gap in long term R&D Gap in long term R&D Spending + Development Spending + Development Funding ModelFunding Model


US TWG Writing Team US TWG Writing Team Peter Borden (Boxer-Cross)Peter Borden (Boxer-Cross) FEPFEP

Murray Bullis (SEMI)Murray Bullis (SEMI) IntroIntro

Alain Diebold (Int. SEMATECH)Alain Diebold (Int. SEMATECH) Intro/EditIntro/Edit

Jack Martinez (NIST) Jack Martinez (NIST) StandardsStandards

Cecilia MartnerCecilia Martner (Applied Materials) (Applied Materials) InterconnectInterconnect

Clive HayzeldenClive Hayzelden FEPFEP

Dick Hockett (CEA/PHI Metrics)Dick Hockett (CEA/PHI Metrics) Materials Char.Materials Char.

Steve Knight (NIST)Steve Knight (NIST) Statistical LimitsStatistical Limits

Noel Poduje (ADE)Noel Poduje (ADE) FEPFEP

Michael Postek (NIST)Michael Postek (NIST) MicroscopyMicroscopy

Brad van Eck (Int. SEMATECH)Brad van Eck (Int. SEMATECH) Int. MeterologyInt. Meterology

Andras VladarAndras Vladar MicroscopyMicroscopy


Backup


New Metrology Need: Standardized New Metrology Need: Standardized Statistics for Discretized DataStatistics for Discretized Data

• Some new methods fit measurement to a discrete set of possible results

• This could result in artificially good precision values that do not really evaluate process control capability

89 nm 89.5 nm 90 nm 90.5 nm 91 nm

0

0.1

0.2

0.3

0.7

0.8

0.9

1

0

0.1

0.2

0.3

0.7

0.8

0.9

1

0

0.1

0.2

0.3

0.7

0.8

0.9

1


2001 Metrology Requirements Summary2001 Metrology Requirements Summary



1.3 0.75 0.5 0.36 0.26 0.18 MPU


Line Edge Roughness Precision 3 (nm) 0.9 0.54 0.36 0.26 0.18 0.13 MPU

Overlay Control (nm) (mean +3 ) 45 31 26 18 13 9 MPU

Overlay Metrology Precision (nm) P/T=0.1 4.5 3.1 2.6 1.8 1.3 0.9 MPU

Front End Processes MetrologyLogic Dielectric Thick Precision 3 (nm) 0.005 0.004 0.0024 0.0024 0.0016 0.0016 MPU

Capacitor Thickness Precision 3 (nm) 0.05 0.05 0.11 0.11 0.09 0.07 DRAM

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

26 14.8 10 7.2 5.2 3.6 MPU

Interconnect MetrologyBarrier layer thick (nm) process range (±3 ) Precision 1 (nm)

1820%0.06

1120%0.036

820%0.027

720%0.023

520%0.017

420%0.01

MPU

Void size for 1 % Voiding in Copper Lines 32.5 22.5 16.25 11.25 8 5.5 MPU

Detection of Killer Pore at (nm) Size 6.5 4.5 3.25 2.25 1.6 1.1 MPU


SL

e.g.150 nm lines300 nm pitch

Novel Methods for FEM controlNovel Methods for FEM control

Optical CD using Overlay System

Automatic cross-

sectioning, imaging and

metrology from all sites of the

FEM

Dose

Focu

s

Dualbeam FIBFEI


Leakage Current correlated to Leakage Current correlated to Line Edge RoughnessLine Edge Roughness

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-1.0 -0.5 .0 .5 1.0 1.5Log Active Width

LER = 10 nmLER = 3 nm

IL @

500

A/

m Id

Center of data at 150 nm channel

length with drive current of 500 A/m

Leakage plotted versus active width

of transistor

The two lines show the dependence

for the case of low and high line edge

roughness.

Units for leakage current are A/m,

plotted on a logrithimic scale

Patterson, et. al., SPIE 2001

Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi


CD-SEM a Potential Solution CD-SEM a Potential Solution for for Wafer and Mask / R&D + ProductionWafer and Mask / R&D + Production

Sato and Mizuno, EIPBN 2000, Palm Springs, CA

Barriers and Solutions

193 & 157 nm Resist Damage» lower dose images

Lineshape » tilt beam SEM vs software

Precision Improvements» new nano-tip source

Depth of Focus» new SEM concept needed

Ultimate Limit of CD-SEM» ~ 5 nm for etched poly Si Gate


Interconnect Metrology SolutionsInterconnect Metrology SolutionsBarrier/Seed Cu FilmsBarrier/Seed Cu Films

ZY

X

Wafer Positioning Stage

Sample

Detector

Aperture

Lens

Probe Laser

Excitation Laser

Neutral Density (ND) Filters

Phase Masks (PM)

Lens

Lens

20x 90 mm Spot Size

~1-2 seconds/point (measurement + data analysis + stage motion)

Excitation LaserDiode-Pumped, Pulsed, Frequency-Doubled Nd:YAG microchip laser. 600 ps Pulse

AlGaAs Diode Laser

5 Potential Solutions 5 Potential Solutions all expected to meet precision requirementsall expected to meet precision requirements

some are extendable to patterned waferssome are extendable to patterned wafers

Objective lens

GenerationlaserProbe laser

Beam splitter

Visionsystem

Detector

Detail inwafer

Junction

Beam

Excess carriers

X-Ray Tube

Thin-Film Sample

Monochromator

Spatially ResolvingX-Ray Sensor

0.15 mm 1psec

Pulsed Laser(200 fsec; 90 MHz) 800nm

Servo delay

Lens

FrequencyDoubler

photocell

Wafer

WavelengthSelector

Acoustic ISTSPicosecond acoustics

X-ray reflectivityX-ray fluorescence

Non-contact resistivity


Voids in CopperVoids in CopperPore Size/Killer Pores in Low kPore Size/Killer Pores in Low k

• Random isolated void detection in copper lines may be used in development at levels

above the < 1% metric

• <1% may not be measurable


Metrology & New StructuresMetrology & New Structures

Gate Gate

Drain

Source

Vertical Vertical TransistorTransistor

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