interconnections: copper & low k dielectrics · ee311 notes/stanford univ. prof. saraswat ......

EE311 Notes/Stanford Univ. Prof. Saraswat

Interconnections: Copper & Low K Dielectrics ITRS 2002 Interconnect Scaling Recommendations

Narrow line effects Ref: J. Gambino, IEDM Short Course, 2003

Interconnect Scaling Scenarios

2

3

4

5

6789

10

20

30

40

0.1 0.2 0.3 0.4 0.5 0.6

De

aly

Tim

e (

ps

ec

)

Feature Size (µm)

50

Cu+Low-k(2.0) Interconnect Delay

Gate Delay

Al+SiO2

Interconnect Delay

Cu+Low-k(2.0) Total Delay

Al+SiO2

Total Delay

Scaling need for lower resistivity metal, Low-k

EE 311 Notes/Prof. Saraswat Copper Interconnect

2

1

1

A1

CS1

1

A1/S

1

SCS1

0.5 0.5 Scale Metal Pitch and Height - R and J increase by square of scaling factor - Sidewall capacitance unchanged - Aspect ratio for gapfill / metal etch unchanged - Drives need for very low resistivity metal with significantly improved EM

performance

1

1

A1

CS1

1

0.5

CS1

0.5 0.5

A1/S2

Why Cu?

• Lower resistivity than Al or Al alloys - reduced RC delay. Metal

Ag

Cu

Au

Al

W

Bulk Resistivity [!"•cm]

1.63

1.67

2.35

2.67

5.65


3

0

2

4

6

8

10

12

14

Num

ber

of M

eta

l Layers

Technology Generation (µm)

0.09 0.13 0.18 0.25 0.35

Cu/Low-k

Al/Low-kCu/SiO

2

Al/SiO2

• Better electromigration reliability than Al alloys.

Al Cu

Melting Point 660 ºC 1083 ºC

Ea for Lattice Diffusion 1.4 eV 2.2 eV

Ea for Grain BoundaryDiffusion

0.4 – 0.8 eV 0.7 – 1.2 eV

Ref: S. Luce, (IBM), IEEE IITC 1998

Challenges for Cu Metallization Limited processing methods: Introduction of Cu must be managed carefully. • Obstacles - Line patterning: Poor dry-etchability of Cu - Poor adhesion to dielectrics


4

- Copper is very mobile in SiO2 => Contamination to Si Devices Increased leakage in SiO2 Increased junction leakage Lower junction break down voltage

Cu atoms ionize, penetrate into the dielectric, and then accumulate in the dielectric as

Cu+ space charge.

• Bias temperature stressing is employed to characterize behavior - Both field and temperature affect barrier lifetime - Neutral Cu atoms and charged Cu ions contribute to Cu transport through

dielectrics - Silicon nitride and oxynitride films are better barriers

Ref: A. Loke et al., Symp. VLSI Tech. 1998


5

• Fast diffusion of Cu into Si and SiO2

• Poor oxidation/corrosion resistance

• Poor adhesion to SiO2

Diffusion barrier /adhesion promotor

Passivation

• Difficulty of applying conventional

dry-etching technique

Damascene Process

Typical Damascene Process

Dielectrics

Barrier Layer

Cu

Solutions - Damascene process for patterning - Using diffusion Barriers

Liners TiN, TaN, etc Silicon Nitride, PSG

Barriers/Linears


6

Barrier Requirements: Ultrathin films should be good barriers Low resistance Chemically stable Defect free to high temperatures

Barriers:

Transition metals (Pd, Cr, Ti, Co, Ni, Pt) generally poor barriers, due to high reactivities to Cu <450˚C − Exception: Ta, Mo, W ... more thermally stable, but fail due to Cu diffusion

through grain boundaries (polycrystalline films) Transition metal alloys: Can be deposited as amorphous films (stable up to 500˚C) Transition metal - silicon compounds: Adding Si to Ta, Ti, Mo, W yields amorphous

refractory barriers with stability to 700˚C Amorphous ternary alloys: Very stable due to high crystallization temperatures (i.e.,

Ta36S14,N50, Ti34Si23N43) • Currently PVD (sputtering/evaporation is used primarily to deposit the barrier/liner,

however, step coverage is a problem. ALD is being developed for barrier/liner application.

PVDALD


7

Interconnect Fabrication Options

Metal

Etch

Positive

Pattern

Dielectric

Deposit ion

Dielectric

Planarization

by CMP

Negative

Pattern

Dielectric

Etch

Metal

Depos ition

Metal CMP

Dielectric

Depos ition

Metal

Dielectric

Photoresist

Etch Stop(Dielectric)

Subtractive Etch(Conventional Approach) Damascene

• Conventional approach of metal etch is used for Al • Damascene approach is used for Cu as it can’t be dry etched


8

Cu Damascene Flow

Options

Oxide

Copper

Conductive Barrier

Dielectric Etch Stop/Barrier

Single Damascene Dual Damascene

Barrier

& Cu

Dep

Cu Via

CMP

Nitride

+ Oxide

Dep

Lead

Pattern

& Etch

+

Barrier

& Cu

Dep

Via

Pattern

& Etch

Cu Lead

CMPLead

Via

Via &

Lead

Pattern

& Etch

Barrier

& Cu

Dep

Cu CMPLead

Via

Cu Damascene Flow Options


9

Deposition methods • Physical vapor deposition (PVD) : Evaporation, Sputtering

• conventional metal deposition technique: widely used for Al interconnects

• produce Cu films with strong (111) texture and smooth surface, in general

• poor step coverage: not tolerable for filling high-aspect ratio features Chemical vapor deposition (CVD)

• conformal deposition with excellent step coverage in high-aspect ratio holes and vias

• costly in processing and maintenance

• generally produce Cu films with fine grain size, weak (111) texture and rough surface


10

Electroplating System for Cu

Dissociation: CuSO4 → Cu2+ + SO4

2- (solution) Reduction: Cu2+ + 2e- → Cu (cathode) Oxidation: Cu → Cu2++ 2e- (anode)

Direct electroplating on the barrier gives poor results. Therefore a thin layer of Cu is needed as a seed. It can be deposited by PVD, CVD or ALD.

Good step coverage and filling capability comparable to CVD process (0.25 µm) Compatible with low-K dielectrics Generally produce strong (111) texture of Cu film Produce much larger sized grain structure than any other deposition methods through

self-annealing process


11

Trench Filling PVD vs. Electroplating of Cu non-conformal

"bottom-up filling"("superfilling")

void

PVD Electroplating Trench Filling Capability of Cu Electroplating

0.13µ trenches 0.18µ vias 029µ vias

Ref: Jonathan Reid, IITC, 1999


12

Effect of the seed layer on the properties of the final Cu

Seed Layer Texture

Seed Layer Surface Roughness

Plated Film TexturePlated Film Texture

Plated Film Grain Size

• Strong (111) texture • Smooth surface

• Strong (111) texture• Large grain size

Seed Layer Electroplated Film

(Thin, PVD seed preferred)

Scanning electron micrographs of Damascene trenches of 0.13 µm width showing “bottom-up filling” of Cu electroplating using DC current (demonstrated by Novellus). Electroplating needs a seeding layer of Cu as electroplating does not occur at a dielectric or barrier surface. The deposition of the seed layer can be done by PVD or CVD. The properties of the final Cu layer critically depend upon the characteristics of the seed layer.


13

Additives for Copper ECD Mixture of organic molecules and chloride ion which adsorb at the copper surface during plating to:

enhance thickness distribution and feature fill control copper grain structure and thus ductility, hardness, stress, and surface

smoothness Brighteners • Adsorbs on copper metal during plating, participates in charge transfer reaction.

Determines Cu growth characteristics with major impact on metallurgy Levelers • Reduce growth rate of copper at protrusions and edges to yield a smooth final

deposit surface. • Effectively increases polarization resistance at high growth areas by inhibiting growth

to a degree proportional to mass transfer to localized sites Carriers • Carriers adsorb during copper plating to form a relatively thick monolayer film at the

cathode. Moderately polarizes Cu deposition by forming a barrier to diffusion of Cu2+ ions to the surface.

Chloride • Adsorbs at both cathode and anode. • Accumulates in anode film and increases anode dissolution kinetics. • Modifies adsorption properties of carrier to influence thickness distribution.

Wafers immersed in platingbath. Additives not yetadsorbed on Cu seed.

Additives adsorbed on Cuseed. No current flow.

Conformal plating begins.Accelerators accumulate atbottom of via, displacing lessstrongly absorbed additives.

Accumulation of acceleratordue to reduced surface area innarrow features, causes rapidgrowth at bottom of via.

t = 2 sec

t = 10 sec t = 20 sec

t = 0 sec= Accelerators= Suppressors

c = Chloride ionsL = Levelers

Ref: J. Reid et al., Solid St. Tech., 43, 86 (2000)

D. Josell et al., J. Electrochem. Soc., 148, C767 (2001)


14

Lognormal grain size distribution

electroplating

0

0.02

0.04

0.06

0.08

0.1

0.01 0.1 1 10

annealedS = 2.682µmσ = 0.435

as-depositedS = 0.863µmσ = 0.716

electroless plating

0

0.02

0.04

0.06

0.08

0.1

0.01 0.1 1 10D (µm)

S = 0.150µmσ = 0.318

as-deposited

CVD

0

0.02

0.04

0.06

0.08

0.1

0.01 0.1 1 10D (µm)

as-deposited

annealed

S = 0.161µmσ = 0.372

S = 0.294µmσ = 0.344

(a)

(b)

(c)

D (µm) Comparison of grain size distribution of the films deposited by (a) CVD, (b) electroless plating, and (c) electroplating (S is the median grain size and s is the lognormal standard deviation of the grain size). Ref: H. Lee, PhD Thesis, Stanford University, 2001


15

Electromigration Electroplated Cu has higher resistance to electromigration because of its grain structure (mostly grain size).

104

105

106

107

1.8 1.9 2.0 2.1 2.2 2.3

Tim

e-t

o-F

ail

ure

(s

ec

)

1/T (10-3

/K)

213 °C238263

Electroplated CuE

a = 0.89 eV

CVD CuE

a = 0.82 eV

grain size

eµ

eµ

=1.4 !m

=0.3 !m

Ref: C. Ryu et al., IEEE IRPS 1997

CVD Cu Electroplated Cu

Electromigration in Cu is strongly affected by grain size and texture, which is strongly affected by the linear, seed and the deposition method.


16

103

104

105

106

107

1.8 1.9 2.0 2.1 2.2 2.3

Tim

e-t

o-F

ailu

re (

se

c)

1/T (10-3

/K)

(111) CVD CuE

a = 0.86 eV

(200) CVD CuE

a = 0.81 eV

213238263 188 °C

Ref: C. Ryu etal., Symp. VLSI Tech. 1998

1 µm 5 µm 5 µm

(a) t = 2 hrs (b) t = 1 day (c) t = 60 days

Plan view TEM images showing evolution of grain size as a function of time for Cu films DC-plated with additives; at 10 mA/cm2. Grain size of the electroplated films increases with annealing time. (Ref: H. Lee, PhD Thesis, Stanford University, 2001)


17

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 10 20 30 40 50

gra

in s

ize

(µ

m)

DC plating current density (mA/cm2)

2 hrs

1 day

10 days

60 days

Grain size evolution for Cu films DC-plated at different plating current density. (Ref: Ref: H. Lee, PhD Thesis, Stanford University, 2001)

140

150

160

170

180

190

200

0 50 100 150 200 250

I (111)/I

(200) r

ati

o

Hours

3.5mA/cm2

7.5mA/cm2

20mA/cm2

10mA/cm2

Evolution of texture at room temperature for films DC-plated with different current density and with additives. (Ref: H. Lee, PhD Thesis, Stanford University, 2001)


18

Scaling of Layered Interconnections

W. Steinhögl et al., Phys. Rev. B66 (2002)

Future

• Resistivity increases when barriers/liners are used. The main conductor

(Cu or Al) size is scaled down but the surrounding barrier film size is not scaled to ensure the barrier properties. •Barriers have much higher resistivity • Barrier consumes progressively larger area

• Barrier thickness doesn’t scale rapidly • Higher aspect ratio => larger barrier area (non-conformal deposition technology, e.g., PVD)


19

ALD IPVD C-PVD

• Resistivity increases as grain size decreases, which in turn is a function of the film thickness. Grain boundaries cause electron scattering leading to reduction in mobility. • Electron surface scattering: resistivity increases in future

• Reduced electron mobility as dimensions decrease

• Copper/barrier interface quality further reduces the mobility

Elastic scattering

No Change in Mobility

Diffuse scattering

Lower Mobility

P=0 P=1

w

hAR=h/w

Aint=AR*w2

Cu

Barrier


20

Barrier Effect

Electron Surface Scattering Effect

!

!b

o bA

AR w

=

"

1

12

*

• Important parameter: Ab to Aint ratio • !b increase with Abto Aint ratio

• Future: ratio may increase

P: Fraction of electrons

scattered elastically from

the interfacek= d/ #mfp

#mfp: Bulk mean free path

for electrons

d: Smallest dimension of

the interconnect• Reduced electron mobility

• Operational temperature

• Copper/barrier interface quality

• Dimensions decrease in tiers: local, semiglobal, global

$

!s!o

=1

1"3(1" P)#mfp

2d

1

X3"1

X5

% &

' ( 1" e"kX

1" Pe"kXdX

1

)

*

Technology node (µm)

Al P=0P=0.5P=1

Cu, P=0.5

0.18 0.15 0.12 0.1 0.07 0.05 0.035

PVDC-PVD

I-PVD

ALD: 10nm

ALD: 3nmALD: 1nm

No BarrierEffe

ctiv

e re

sist

ivity

(µ o

hm-c

m)

Year

Global100°C


21


Al P=0P=0.5P=1

Cu, P=0.5

0.18 0.15 0.12 0.1 0.07 0.05 0.035

PVDC-PVD

I-PVDALD: 10nm

ALD: 3nmALD: 1nm

No Barrier

Semiglobal Temp.=100 0C

Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April 2002

Temp.=100 0C


Al P=0P=0.5P=1

Cu, P=0.5

0.18 0.15 0.12 0.1 0.07 0.05 0.035

PVD C-PVD

ALD: 10nm

ALD: 3nmALD: 1nm

No Barrier

Local

Year

Effe

ctiv

e re

sist

ivity

(µ o

hm-c

m)

Local Temp.=100 0C

•With ALD least resistivity rise • Higher P value => higher mobility • Al resistivity rises slower than Cu

• no 4 sided barrier • higher intrinsic resistivity => smaller λmfp => smaller thin film

effect • Cross over with Al resistivity possible


22

Cu Resistivity: Effect of Chip Temperature

2000 2004 2008 2012Year

0.18 0.12 0.07 0.05Technology Node (µm)

0.0353.6

3.2

2.4

1.6Effe

ctiv

e re

sist

ivity

(mic

rooh

m-c

m)

2

2.8

T=100 0C

T=27 0C

Global

Elastic

Diffuse

Elastic

Diffuse

Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April 2002

•Higher temperature ⇒ lower mobility ⇒ higher resistivity •Realistic Values at 35 nm node: P=0.5, temp=100 0C

- local ~ 5 µΩ-cm - semi-global ~ 4.2 µΩ-cm - global ~ 3.2 µΩ-cm

interconnections: copper & low k dielectrics · ee311 notes/stanford univ. prof. saraswat ......

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