interconnect working group - computer science€¦ · interconnect working group 2011 revision 14th...

ITRS 2011 Winter Meeting – 14 December 2011 Seoul. Korea Work in Progress Do Not Publish or Distribute - 1 -

Interconnect Working Group

2011 Revision

14th December 2011

Incheon, Korea


ITWG Regional Chairs

US Paul Zimmerman (temp)

Japan Akira Matsumoto Tomo Nakamura

Europe Hans-Joachim Barth Alexis Farcy

Korea Gil-Hyun Choi Noh-Jung Kwak

Taiwan Douglas CH Yu


Partial List of Contributors

• Nobuo Aoi • Sitaram Arkalgud • Lucile Arnaud • Koji Ban • Hans-Joachim Barth • Eric Beyne • Boyan Boyanov • Christopher Case • Chung-Liang Chang • Hsien-Wei Chen • Gilheyun Choi • Jinn-P. Chu • Mike Corbett • Alexis Farcy • Paul Feeney • Takashi Hayakawa • Cheng-Chieh Hsieh • Masayoshi Imai • Atsunobu Isobayashi

• Raymond Jao • Shin-Puu Jeng • Ajey Joshi • Morihiro Kada • Sibum Kim • Nobuyoshi Kobayashi • Mauro Kobrinsky • Kaushik Kumar • Nohjung Kwak • Hyeon Deok Lee • Scott List • Anderson Liu • Didier Louis • Toshiro Maekawa • David Maloney • Akira Matsumoto • Azad Naeemi • Mehul Naik • Tomoji Nakamura

• Yuichi Nakao • Akira Ouchi • Roger Quon • Rick Reidy • Scott Pozder • Larry Smith • Mark Scannell • Hideki Shibata • Michele Stucchi • Wen-Chih Chiou • Weng Hong Teh • Thomas Toms • Manabu Tsujimura • Kazuyoshi Ueno • Osamu Yamazaki • Paul Zimmerman 1211


Interconnect scope • Conductors and dielectrics

– Starts at contacts

– Metal 1 through global levels

– Includes the pre-metal dielectric (PMD)

• Associated planarization

• Necessary etch, strip and cleans

• Embedded passives

• Global and intermediate TSVs for 3D

• Reliability and system and performance issues

• “Needs” based replaced by – scaled, equivalently scaled or functional diversity drivers.

ITRS 2011 Winter Meeting – 14 December 2011 Seoul. Korea Work in Progress Do Not Publish or Distribute

MPU Cross-Section

Dielectric Capping

Layer

Copper Conductor

with Barrier /

Nucleation Layer

Pre-Metal Dielectric

Tungsten Contact

Plug

Inter- Mediate (=M1x1)

Metal 1

Passivation

Dielectric Etch Stop Layer

ASIC Cross-Section

Semi- Global (=M1x2)

Metal 1 Pitch

Via

Wire

Via

Wire

Via

Wire

Metal 1 Pitch

Global

(=IMx1.5~2µm)

Inter- Mediate (=M1x1)

Metal 1

Global

(=IMx1.5~2µm)

1) MPU: Revised hierarchy

2) ASIC: No drastic change, however semi-global should be kept at 2 x M1

3) Flash: The new technology driver for M1

Hierarchical Cross Sections

Flash Cross-Section

Metal 3

Metal 0 Metal 1

Metal 2

Poly Pitch

Metal 1 Pitch


Technology Requirements

Now restated and organized as • General requirements

– Resistivity – Dielectric constant – Metal levels – Reliability metrics

• Level specific requirements (M1, intermediate, global) – Geometrical

• Via size and aspect ratio • Barrier/cladding thickness • Planarization specs

– Materials requirements • Conductor effective resistivity and scattering effects

– Electrical characteristics • Delay, capacitance, crosstalk, power index


Technology Drivers Expanding

• Traditional geometric scaling – Cost – Necessary to enable transistor scaling

• Performance – Dielectric constant scaling for delay, and power

improvements • Reliability

– EM – Crosstalk

• Increasing value by adding functionality using CMOS-compatible solutions: – 3D, optical components, sensors – Contributing to More than Moore


Difficult challenges (1 of 2)

• Meeting the requirements of scaled metal/dielectric systems – Managing RC delay and power

• New dielectrics (including air gap) • Controlling conductivity (liners and scattering)

– Filling small features • Barriers and nucleation layer • Conductor deposition

– Reliability • Electrical and thermo-mechanical

• Engineering a manufacturable interconnect stack compatible with new materials and processes – Defects – Metrology – Variability


Difficult challenges (2 of 2)

• Meeting the requirements with equivalent scaling – Interconnect design and architecture (includes multi-

core benefits) – Alternative metal/dielectric assemblies

• 3D with TSV – Interconnects beyond metal/dielectrics

• 3D • Optical wiring • CNT/Graphene

– Reliability • Electrical and thermo-mechanical

• Engineering a CMOS-compatible manufacturable interconnect system – Non-traditional materials (for optical, CNT etc.) – Unique metrology (alignment, chirality measurements,

turning radius etc)


Historical Transition of ITRS Low-k Roadmap

Narrowed effective range due to elimination of hybrid stack

2009 Summer Conference

Eff

ecti

ve

Die

lectr

ic C

on

sta

nt;

ke

ff

Year of 1st Shipment

ITRS1999

ITRS2001

ITRS2005

ITRS2003

Before 2001, unreasonable RM

without logical basis

ITRS2007-2010

ITRS2011


2011 Low-k Roadmap Update for MPU/ASIC

1.0

1.5

2.0

2.5

3.0

3.5

Eff

ec

tive

Die

lec

tric

Co

ns

tan

t; k

eff

4.0

11 12

Year of 1st Shipment

Red Brick Wall (Solutions are NOT known)

Manufacturable

solutions

are known

17 16 15 14 13 18

Calculated based on delay time

using typical critical path

Estimated by typical three

kinds of low-k ILD structures

2.82-3.16

2.55-3.00

20 19

2.40-2.78

1.88-2.28

ITR

S2007-8

IT

RS

2011

ITRS2009

26

Manufacturable

solutions exist,

and are being optimized

IT

RS

2009-1

0

21

2.15-2.46

22 25 24 23

1.65-2.09


2011 Low-k Roadmap Update for MPU/ASIC

Year of Production 2011 2012 2013 2014 2015 2016 2017 2018

IS DRAM ½ Pitch (nm) (contacted) 36 32 28 25 23 20.0 17.9 15.9

IS MPU/ASIC Metal 1 ½ Pitch

(nm)(contacted) 38 32 27 24 21 18.9 16.9 15.0

WAS Interlevel metal insulator – effective

dielectric constant (κ)

2.6-2.9 2.6-2.9 2.4-2.8 2.4-2.8 2.4-2.8 2.1-2.5 2.1-2.5 2.1-2.5

IS 2.8-3.2 2.8-3.2 2.5-3.0 2.5-3.0 2.5-3.0 2.1-2.8 2.1-2.8 2.1-2.8

WAS Interlevel metal insulator – bulk


2.3-2.6 2.3-2.6 2.1-2.4 2.1-2.4 2.1-2.4 1.9-2.2 1.9-2.2 1.9-2.2

IS 2.5-2.7 2.5-2.7 2.3-2.6 2.3-2.6 2.3-2.6 2.2-2.5 2.2-2.5 2.2-2.5

WAS Copper diffusion barrier and etch

stop – bulk dielectric constant (κ)

3.5-4.0 3.5-4.0 3.0-3.5 3.0-3.5 3.0-3.5 2.6-3.0 2.6-3.0 2.6-3.0

IS 3.5-4.0 3.5-4.0 3.0-3.5 3.0-3.5 3.0-3.5 2.6-3.0 2.6-3.0 2.6-3.0


IS DRAM ½ Pitch (nm) (contacted) 14.2 12.6 11.3 10.0 8.9 8.0 7.1 6.3

IS MPU/ASIC Metal 1 ½ Pitch

(nm)(contacted) 13.4 11.9 10.6 9.5 8.4 7.5 6.7 6.0

WAS Interlevel metal insulator – effective


2.0-2.3 2.0-2.3 2.0-2.3 1.7-2.0 1.7-2.0 1.7-2.0

IS 2.1-2.4 2.1-2.4 2.1-2.4 1.8-2.2 1.8-2.2 1.8-2.2 1.6-2.2 1.6-2.2 WAS Interlevel metal insulator – bulk


1.7-2.0 1.7-2.0 1.7-2.0 1.5-1.8 1.5-1.8 1.5-1.8

IS 2.0-2.4 2.0-2.4 2.0-2.4 1.8-2.2 1.8-2.2 1.8-2.2 1.8-2.2 1.8-2.2

WAS Copper diffusion barrier and etch

stop – bulk dielectric constant (κ)

2.4-2.6 2.4-2.6 2.4-2.6 2.1-2.4 2.1-2.4 2.1-2.4

IS 2.4-2.6 2.4-2.6 2.4-2.6 2.1-2.4 2.1-2.4 2.1-2.4 2.1-2.4 2.1-2.4

Air gap architectures will be required for keff 2.0 • No viable materials expected to be available. • Mechanical requirements easier to achieve with air-gaps.

• End of the material solution and the beginning of an architecture solution.


Air Gap

Pictures (top left, clockwise): NXP, IBM, Panasonic, TSMC

Approaches •Creation of air gaps with non-conformal deposition •Removal of sacrificial materials after multi-level interconnects


Flash Application K.Prall et al., (Micron & Intel), “25 nm 64Gb MLC NAND Technology and Scaling Challenges”, Tech. Dig. of IEDM2010, pp.102-105 (2010).

Fig. 6 Cross-section of the cell in the WL direction showing the WL airgap and reduction in total FG-FG coupling with airgap (red square) and without (blue diamond). WL bending is caused by sample preparation. A 25% reduction in total interference is achieved with the airgap.

Fig. 7 Cross-section of the cell in the BL direction showing the bit line airgap. A 30% reduction in BL capacitance was achieved.


Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Interim solutions are known Structure (a) Structure (b)

Manufacturable solutions are NOT known

* Set as the same pitch with Poly

** Structure (a) used in calculation of max. effective dielectric constant

*** Structure (b) used in calculation of min. effective dielectric constant

(assuming 1/4 of width on each side and the same amount of height on the bottom are SiO2)

SiO2

SiN

metal

SiO2

metal

metal

SiO2

SiN

SiO2

SiCN

metal

SiO2

metal

metal

airgap

SiCN

SiO2

Table INTC** Flash Interconnect Technology Requirements

Year of Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

Flash ½ Pitch (nm) (un-contacted Poly) 22 20 18 17 15 14.2 13.0 11.9 10.9 10.0 8.9 8.0

DRAM ½ Pitch (nm) (contacted) 36 32 28 25 23 20.0 17.9 15.9 14.2 12.6 11.3 10.0

MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) 38 32 27 24 21 18.9 16.9 15.0 13.4 11.9 10.6 9.5

Number of metal layers 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4

Metal 1wiring 1/2 pitch (nm) * 22 20 18 17 15 14.2 13.0 11.9 10.9 10.0 8.9 8.0

Interlevel metal 1 insulator – max. effective dielectric constant (κ)

**4.61 4.61 4.62 4.62 4.62 4.62 4.63 4.62 4.61 4.61 4.61 4.61

Interlevel metal 1 insulator – min. effective dielectric constant (κ)

***2.68 2.69 2.71 2.68 2.66 2.66 2.67 2.64 2.62 2.63 2.64 2.65

Metal 1 A/R (for Cu) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1

Conductor effective resistivity (µΩ-cm) (for Cu) 6.6 7.0 7.5 7.9 8.5 9.1 9.7 10.4 11.1 11.9 13.1 14.4

Specific via resistance (Ω-cm2) 1.1E-08 9.7E-09 8.9E-09 8.2E-09 7.5E-09 6.9E-09 6.3E-09 5.8E-09 5.3E-09 4.9E-09 4.3E-09 3.9E-09

Contact A/R 26 29 31 34 37 41 44 48 53 57 64 72

Specific contact resistance (Ω-cm2) 5.0E-07 5.0E-07 5.0E-07 5.1E-07 5.1E-07 5.2E-07 5.2E-07 5.2E-07 5.2E-07 5.2E-07 5.3E-07 5.3E-07

Flash interconnect requirements Items in the table • Flash half pitch (nm) • DRAM half pitch (nm) • MPU/ASIC half pitch (nm) • Numbers of metal layers • Metal 1 wiring ½ pitch (nm) • Interlevel metal 1 insulators – max. effective dielectric

constants • Interlevel metal 1 insulators – min. effective dielectric

constants • Metal 1 A/R • Conductor effective resistivity (µ cm) for Cu • Specific via resistance ( cm2) • Contact A/R • Specific contact resistance ( cm2)


2011 Barrier/Nucleation/Resistivity

• Barrier layer requires an appropriate combination of liners and nucleation layers potentially with ALD, and considering low k properties.

• Resistivity increases due to scattering and impact of liners •No known practical solutions


MPU/ASIC Metal 1 ½ Pitch

(nm)(contacted) 38 32 27 24 18.9 16.9 15.0 21

Barrier cladding thickness

Metal 1 (nm) 2.9 2.6 2.4 2.1 1.9 1.7 1.5 1.3

Conductor effective resistivity

(µΩ-cm) Cu Metal 1 4.48 5.00 5.63 6.00 6.61 6.96 7.46 8.09


MPU/ASIC Metal 1 ½ Pitch

(nm)(contacted) 13.4 11.9 10.6 9.5 8.4 18.9 16.9 15.0

Barrier cladding thickness Metal 1

(nm) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5

Conductor effective resistivity

(µΩ-cm) Cu Metal 1 8.81 9.74 10.86 11.71 12.75 14.06 15.02 16.00


0.1

1.0

10.0

2011 2014 2017 2020 2023 2026Year

Jm

ax

(M

A/cm

2)

1.0

10.0

100.0

2011 2014 2017 2020 2023 2026

Year

Fre

qu

en

cy (

GH

z)

Wire current limit – width dependence

Jmax On chip local clock frequency

• Jmax will increase with frequency and reducing cross-section, while JEM will scale with the product w*h according to EM lifetime dependence on wiring width. The color boundaries may actually be width-dependent.

• Jmax is relaxed mainly due to the reduction of clock frequency. • JEM (J limited by EM) is considered to have been improved by EM

enhancement technologies such as CuAl and CoWP cap.

JEM

2010 Update

2011 Revision

2010 Update

2011 Revision


H. Shibata added published data based on Yokogawa et. Al. IEEE Trans on ED.2008

EM

Lif

eti

me Im

pro

vem

en

t R

ati

o

Normalized Resistance Increase Ratio

CuSiN

CuAl

CoWP

CuSiN（1）

CuSiN（2）

CuGeN

CuSi(N)

+ Ti-BM

＜CoWP, or CVD-Co-Cap＞

Si

Si

Si Si

Si Si Si

Si Si

Si

Si

Si Si

Al

Al Al

Al

Al

Al

Al

Al

Al Al

Al

Al Al Al

Al Al

＜CuAl-Alloy＞

＜CuSiN-Cap＞

＜CuGeN-Cap＞

Ge Ge Ge Ge

＜CuSiN-Cap+Ti＞

Metal Capping Various lifetime improvement approaches against the resistivity increase


High Density TSV Roadmap or “enabling terabits/sec at femtojoules/bit”

• The Interconnect perspective - examples:

– High bandwidth/low energy interfaces between memory and logic

– Heterogeneous integration with minimal parasitics (analog/digital, mixed substrate materials, etc.)

– “Re-architect” chip by placing macros (functional units) on multiple tiers (wafers) and connect using HD TSVs

• Defined a 3D interconnect hierarchy

• TSV dimensions

• Minimum contact pitches

• Overlay accuracy

– Described process modules

Table INTC3 Global Interconnect Level 3D-SIC/3D-SOC --Updated

Global Level, W2W,D2W or D2D 3D-stacking 2009-2012 2013-2015

Min. TSV diameter 4-8 µm 2-4µm

Min. TSV pitch 8-16 µm 4-8 µm

Min. TSVdepth 20-50 µm 20-50 µm

Max. TSV aspect ratio 5:1 – 10:1 10:1 – 20:1

Bonding overlay accuracy 1.0-1.5 µm 0.5-1.0 µm

Min. contact pitch (thermocompression) 10 µm 5 µm

Min. contact pitch (solder µbump) 20 µm 10 µm

Number of tiers 2-3 2-4


Emerging Interconnect Changes • Current focus is on transport properties of Cu replacements,

optical and native device interconnects • Research focus in optical in on die-to-die and chip-chip as

the most probable commercial intercept • Rate of introduction of new candidates in research is

decreasing topological insulators is the only 2011

addition Key messages: • Novel state variables are slow relative to repeater-driven

Cu/low-k and require significant area savings to maintain switching speed

• Evaluation of energy efficiency of emerging options

necessitates joint consideration of switch and interconnect options


All roads lead to C?

Al Cu C

- 22 -

Ge Si C


Emerging Interconnect Summary Table Option Potential Advantages Primary Concerns Other metals (W, Ag, silicides)

Potential lower resistance in fine geometries

Grain boundary scattering, integration issues, reliability

Nanowires native

Ballistic conduction in narrow lines

Quantum contact resistance, placement, low density, substrate interactions

CNTs native

Ballistic conduction in narrow lines, EM resistance

Quantum contact resistance, controlled placement, low density, variability

Graphene nanoribbons native

Ballistic conduction in narrow films, planar growth

Control of edges, deposition and stacking, substrate interactions

Optical (interchip)

High bandwidth, low power and latency, noise immunity

Connection and alignment between die and package, optical /electrical conversions

Optical (intrachip)

Latency and power reduction for long lines, high bandwidth with WDM

Benefits only for long lines, need compact components, integration issues, need WDM

Topological Insulators native

Limited elastic scattering, spin polarized transport

No suppression of inelastic backscattering, must use as single layer

Wireless Available with current technology, wireless

Very limited bandwidth, intra-die communication difficult, large area and power overhead

Superconductors Zero resistance interconnect, high Q passives

Cryogenic cooling, frequency dependent resistance, defects, low critical current density


Topological Insulators – an interconnect option beyond Cu/Low k?

Potential

•Graphene-like electron transport

•Elastic scattering protection

•Spin-polarized transport

•Device/interconnect synergy

Cons

•Loss of scattering immunity due to

layer-to-layer coupling and inelastic

scattering

Prognosis: unlikely to be

feasible as conventional

interconnect but holds

potential for spintronics

S. Zhang, Physics (2008)

J.Seo, Nature(2010)


Delay of New State Variables

New state variables are slow compared to conventional CMOS

interconnects and must enable substantial area savings to match

CMOS performance

Ballistic

Interconnect Length (Gate Pitch) Nee

ded

Are

a S

cali

ng

AC

MO

S /A

emer

gin

g

Interconnect Length (Gate Pitch)

Del

ay (

ps)

ITRS 2011 Winter Meeting – 14 December 2011 Seoul. Korea Work in Progress Do Not Publish or Distribute - 26 - - 26 -

Interconnect Summary 2011 • Low-k – slightly changed

– Air gaps expected to be solution for keff £ 2.0 – First implementation will be for Flash

• Jmax current limits updated with relaxed on-chip clock frequency – Moves red zone by one to two years

• Barriers and nucleation layers are a critical challenge – ALD integration is still being investigated including the combination with

appropriate dielectrics and barrier metals. – Approaches of new liners (Co, Ru and others) stacked with barrier layers are

proliferating – Capping metal for reliability improvement nearing production

• Revised 3D TSV roadmap tables • Emerging interconnect solutions are being developed. • All new interconnect variables are slow and will require substantial area savings to

match/exceed the speed of repeated Cu/low-k with CMOS drivers; applications will likely be driven by new functionality enabled by emerging interconnects

• Novel state variables are slow relative to repeater-driven Cu/low-k and require significant area savings to maintain switching speed

• Evaluation of energy efficiency of emerging options necessitates joint consideration of switch and interconnect options

interconnect working group - computer science€¦ · interconnect working group 2011 revision 14th...

Documents