intel x79 express chipset · 2 intel® c600 series chipset and intel® x79 express chipset...

Document Number: 326514-002

Intel® C600 Series Chipset and Intel® X79 Express ChipsetDatasheet

April 2013

2 Intel® C600 Series Chipset and Intel® X79 Express ChipsetDatasheet

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The information here is subject to change without notice. Do not finalize a design with this information. The Intel® C600 Series Chipset described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.Intel® Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/technology/platform-technology/intel-amt/No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see http://www.intel.com/technology/security.Intel® High Definition Audio requires a system with an appropriate Intel chipset and a motherboard with an appropriate codec and the necessary drivers installed. System sound quality will vary depending on actual implementation, controller, codec, drivers and speakers. For more information about Intel® HD audio, refer to http://www.intel.com/.Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.Intel, Xeon, Intel vPro and the Intel logo are trademarks of Intel Corporation in the U. S. and/or other countries.*Other names and brands may be claimed as the property of others.Copyright © 2013, Intel Corporation

Intel® C600 Series Chipset and Intel® X79 Express Chipset 3Datasheet

Contents

1 Introduction ............................................................................................................ 411.1 About This Manual ............................................................................................. 411.2 Overview ......................................................................................................... 44

1.2.1 Capability Overview................................................................................ 451.3 Intel® C600 Series Chipset and Intel® X79 Express Chipset SKU Definition ............... 50

2 Signal Description ................................................................................................... 512.1 Direct Media Interface (DMI) to Host Controller ..................................................... 532.2 PCI Express* .................................................................................................... 532.3 PCI Express* Uplink (Intel® C606, C608 Chipset SKUs Only)................................... 542.4 PCI Interface .................................................................................................... 542.5 Serial ATA Interface........................................................................................... 562.6 SAS Interface (SRV/WS SKUs Only)..................................................................... 582.7 LPC Interface.................................................................................................... 602.8 Interrupt Interface ............................................................................................ 602.9 USB 2.0 Interface.............................................................................................. 612.10 Power Management Interface.............................................................................. 622.11 Processor Interface............................................................................................ 642.12 SMBus Interface................................................................................................ 652.13 System Management Interface............................................................................ 652.14 SAS System Management Interface (SRV/WS SKUs Only)....................................... 652.15 Real Time Clock Interface................................................................................... 662.16 Miscellaneous Signals ........................................................................................ 662.17 Intel® High Definition Audio (Intel® HD Audio) Link ............................................... 672.18 Serial Peripheral Interface (SPI) .......................................................................... 682.19 Thermal Signals ................................................................................................ 682.20 JTAG Signals .................................................................................................... 682.21 Clock Signals .................................................................................................... 692.22 General Purpose I/O Signals ............................................................................... 702.23 GPIO Serial Expander Signals.............................................................................. 732.24 Manageability Signals ........................................................................................ 732.25 Power and Ground Signals.................................................................................. 742.26 Pin Straps ........................................................................................................ 76

2.26.1 Functional Straps ................................................................................... 762.27 External RTC Circuitry........................................................................................ 79

3 PCH Pin States......................................................................................................... 813.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 813.2 Output and I/O Signals Planes and States............................................................. 823.3 Power Planes for Input Signals ............................................................................ 87

4 System Clock Domains............................................................................................. 914.1 System Clock Domains....................................................................................... 914.2 Functional Blocks .............................................................................................. 93

5 Functional Description ............................................................................................. 955.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 95

5.1.1 PCI Bus Interface ................................................................................... 955.1.2 PCI Bridge As an Initiator ........................................................................ 955.1.3 Parity Error Detection and Generation ....................................................... 975.1.4 PCIRST#............................................................................................... 985.1.5 Peer Cycles ........................................................................................... 985.1.6 PCI-to-PCI Bridge Model.......................................................................... 985.1.7 IDSEL to Device Number Mapping ............................................................ 99


5.1.8 Standard PCI Bus Configuration Mechanism................................................995.2 PCI Legacy Mode ...............................................................................................995.3 PCI Express*...................................................................................................100

5.3.1 PCI Express* UpLink Port (Bn:D0:F0) (SRV/WS SKUs Only) .......................1005.3.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..........................106

5.4 Gigabit Ethernet Controller (B0:D25:F0) .............................................................1105.4.1 GbE PCI Express Bus Interface ...............................................................1125.4.2 Error Events and Error Reporting ............................................................1135.4.3 Ethernet Interface ................................................................................1135.4.4 PCI Power Management.........................................................................1135.4.5 Configurable LEDs.................................................................................1155.4.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) ..........................116

5.5 LPC Bridge (with System and Management Functions) (D31:F0).............................1175.5.1 LPC Interface .......................................................................................117

5.6 DMA Operation (D31:F0) ..................................................................................1215.6.1 Channel Priority....................................................................................1225.6.2 Address Compatibility Mode ...................................................................1225.6.3 Summary of DMA Transfer Sizes .............................................................1225.6.4 Autoinitialize ........................................................................................1235.6.5 Software Commands .............................................................................123

5.7 LPC DMA ........................................................................................................1245.7.1 Asserting DMA Requests ........................................................................1245.7.2 Abandoning DMA Requests.....................................................................1245.7.3 General Flow of DMA Transfers ...............................................................1255.7.4 Terminal Count.....................................................................................1255.7.5 Verify Mode .........................................................................................1255.7.6 DMA Request Deassertion ......................................................................1265.7.7 SYNC Field / LDRQ# Rules .....................................................................126

5.8 8254 Timers (D31:F0)......................................................................................1275.8.1 Timer Programming ..............................................................................1275.8.2 Reading from the Interval Timer .............................................................128

5.9 8259 Interrupt Controllers (PIC) (D31:F0)...........................................................1305.9.1 Interrupt Handling ................................................................................1315.9.2 Initialization Command Words (ICWx) .....................................................1325.9.3 Operation Command Words (OCW) .........................................................1335.9.4 Modes of Operation...............................................................................1335.9.5 Masking Interrupts................................................................................1355.9.6 Steering PCI Interrupts..........................................................................135

5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0)...............................1365.10.1 Interrupt Handling ................................................................................1365.10.2 Interrupt Mapping.................................................................................1365.10.3 PCI / PCI Express* Message-Based Interrupts ..........................................1375.10.4 IOxAPIC Address Remapping (SRV/WS SKUs Only) ...................................1375.10.5 External Interrupt Controller Support ......................................................137

5.11 Serial Interrupt (D31:F0)..................................................................................1385.11.1 Start Frame .........................................................................................1385.11.2 Data Frames ........................................................................................1395.11.3 Stop Frame..........................................................................................1395.11.4 Specific Interrupts Not Supported using SERIRQ .......................................1395.11.5 Data Frame Format...............................................................................140

5.12 Real Time Clock (D31:F0) .................................................................................1405.12.1 Update Cycles ......................................................................................1415.12.2 Interrupts............................................................................................1415.12.3 Lockable RAM Ranges............................................................................1415.12.4 Century Rollover...................................................................................1425.12.5 Clearing Battery-Backed RTC RAM...........................................................142


5.13 Processor Interface (D31:F0) ............................................................................ 1435.13.1 Processor Interface Signals and VLW Messages ........................................ 1445.13.2 Dual-Processor Issues........................................................................... 1455.13.3 Virtual Legacy Wire (VLW) Messages....................................................... 145

5.14 Power Management ......................................................................................... 1465.14.1 Features ............................................................................................. 1465.14.2 PCH and System Power States ............................................................... 1465.14.3 System Power Planes............................................................................ 1485.14.4 SMI#/SCI Generation ........................................................................... 1485.14.5 C-States ............................................................................................. 1515.14.6 Sleep States ........................................................................................ 1515.14.7 Event Input Signals and Their Usage....................................................... 1555.14.8 ALT Access Mode.................................................................................. 1585.14.9 System Power Supplies, Planes, and Signals ............................................ 1615.14.10Legacy Power Management Theory of Operation ....................................... 1635.14.11Reset Behavior..................................................................................... 163

5.15 System Management (D31:F0).......................................................................... 1655.15.1 Theory of Operation.............................................................................. 1665.15.2 TCO Modes.......................................................................................... 167

5.16 General Purpose I/O (D31:F0) .......................................................................... 1695.16.1 Power Wells......................................................................................... 1695.16.2 SMI# SCI and NMI Routing.................................................................... 1695.16.3 Triggering ........................................................................................... 1695.16.4 GPIO Registers Lockdown...................................................................... 1695.16.5 Serial POST Codes over GPIO................................................................. 1705.16.6 GPIO Serial Expander (GSX) .................................................................. 172

5.17 SATA Host Controller (D31:F2, F5) .................................................................... 1745.17.1 SATA 6 Gb/s Support ............................................................................ 1745.17.2 SATA Feature Support........................................................................... 1745.17.3 Theory of Operation.............................................................................. 1755.17.4 SATA Swap Bay Support ....................................................................... 1765.17.5 Hot-Plug Operation............................................................................... 1765.17.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) .......................... 1765.17.7 Intel® Rapid Storage Technology Enterprise Configuration ......................... 1775.17.8 Power Management Operation................................................................ 1785.17.9 SATA Device Presence........................................................................... 1795.17.10SATA LED............................................................................................ 1805.17.11AHCI Operation.................................................................................... 1805.17.12SGPIO Signals ..................................................................................... 1815.17.13External SATA...................................................................................... 184

5.18 SAS/SATA Controller Overview (SAS is for SRV/WS SKUs Only)............................. 1855.18.1 SCU Features....................................................................................... 1855.18.2 SCU Configurations............................................................................... 1865.18.3 Storage Controller Unit (SCU) Architecture .............................................. 1885.18.4 SCU Physical Layer/PHY Overview .......................................................... 1965.18.5 Interrupts and Interrupt Coalescing ........................................................ 1985.18.6 SMU Error and Event Generation ............................................................ 1995.18.7 Host Interface Error Conditions .............................................................. 2005.18.8 Host Interface Messages Received .......................................................... 2045.18.9 Reset.................................................................................................. 2045.18.10SGPIO ................................................................................................ 205

5.19 High Precision Event Timers (HPET) ................................................................... 2145.19.1 Timer Accuracy .................................................................................... 2145.19.2 Interrupt Mapping ................................................................................ 2155.19.3 Periodic versus Non-Periodic Modes ........................................................ 2165.19.4 Enabling the Timers.............................................................................. 217


5.19.5 Interrupt Levels....................................................................................2175.19.6 Handling Interrupts...............................................................................2175.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors ..............................217

5.20 USB EHCI Host Controllers (D29:F0 and D26:F0) .................................................2175.20.1 EHC Initialization ..................................................................................2175.20.2 Data Structures in Main Memory .............................................................2185.20.3 USB 2.0 Enhanced Host Controller DMA ...................................................2185.20.4 Data Encoding and Bit Stuffing ...............................................................2185.20.5 Packet Formats ....................................................................................2185.20.6 USB 2.0 Interrupts and Error Conditions ..................................................2195.20.7 USB 2.0 Power Management ..................................................................2205.20.8 USB 2.0 Legacy Keyboard Operation .......................................................2215.20.9 USB 2.0 Based Debug Port.....................................................................2215.20.10EHCI Caching .......................................................................................2255.20.11USB Pre-Fetch Based Pause ...................................................................2255.20.12Function Level Reset Support (FLR) (SRV/WS SKUs Only) ..........................2265.20.13USB Overcurrent Protection....................................................................226

5.21 Integrated USB 2.0 Rate Matching Hub...............................................................2275.21.1 Overview.............................................................................................2275.21.2 Architecture .........................................................................................227

5.22 SMBus Controller .............................................................................................2285.22.1 Host SMBus Controller(D31:F3) ..............................................................2285.22.2 IDF SMbus Controllers (Bus x:Device 0:Function 3,4,5)

(SRV/WS SKUs Only) ............................................................................2285.22.3 Host Controller .....................................................................................2295.22.4 Bus Arbitration .....................................................................................2335.22.5 Bus Timing ..........................................................................................2345.22.6 Interrupts / SMI# .................................................................................2345.22.7 SMBALERT#.........................................................................................2355.22.8 SMBus CRC Generation and Checking ......................................................2355.22.9 SMBus Slave Interface...........................................................................236

5.23 Thermal Management.......................................................................................2415.23.1 Thermal Sensor ....................................................................................2415.23.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1).....243

5.24 Intel® High Definition Audio (Intel® HD Audio) Overview (D27:F0).........................2515.25 PCH Intel® Management Engine Firmware...........................................................251

5.25.1 Intel® Server Platform Services Firmware ................................................2515.25.2 Intel® AMT 7.0 (SRV/WS SKUs Only) ......................................................2535.25.3 Intel® Management Engine Requirements ................................................254

5.26 Serial Peripheral Interface (SPI) ........................................................................2555.26.1 SPI Supported Feature Overview ............................................................2555.26.2 Flash Descriptor ...................................................................................2565.26.3 Flash Access ........................................................................................2585.26.4 Serial Flash Device Compatibility Requirements ........................................2595.26.5 Multiple Page Write Usage Model.............................................................2615.26.6 Flash Device Configurations ...................................................................2625.26.7 SPI Flash Device Recommended Pinout....................................................2635.26.8 Serial Flash Device Package ...................................................................263

5.27 Fan Control/Thermal Management .....................................................................2645.27.1 PWM Outputs .......................................................................................2645.27.2 TACH Inputs ........................................................................................264

5.28 Feature Capability Mechanism ...........................................................................2655.29 Intel® Virtualization Technology (SRV/WS SKUs Only) ..........................................265

5.29.1 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives ..................................................................265

5.29.2 Intel® VT-d features supported on PCH....................................................265


5.29.3 Support for Function Level Reset (FLR) in PCH.......................................... 2665.29.4 Virtualization Support for PCH’s IOxAPIC ................................................. 2665.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 266

6 PCH Ballout Definition ........................................................................................... 267

7 Package Information ............................................................................................. 281

8 Electrical Characteristics ....................................................................................... 2838.1 Thermal Specifications ..................................................................................... 2838.2 Absolute Maximum Ratings............................................................................... 2838.3 PCH Power Supply Range ................................................................................. 2848.4 General DC Characteristics ............................................................................... 2848.5 AC Characteristics ........................................................................................... 2948.6 Power Sequencing and Reset Signal Timings ....................................................... 3028.7 Power Management Timing Diagrams................................................................. 3058.8 AC Timing Diagrams ........................................................................................ 309

9 Register and Memory Mapping............................................................................... 3199.1 PCI Devices and Functions................................................................................ 3209.2 PCI Configuration Map ..................................................................................... 3219.3 I/O Map ......................................................................................................... 322

9.3.1 Fixed I/O Address Ranges ..................................................................... 3229.3.2 Variable I/O Decode Ranges .................................................................. 324

9.4 Memory Map................................................................................................... 3259.4.1 Boot-Block Update Scheme.................................................................... 327

10 Chipset Configuration Registers............................................................................. 32910.1 Chipset Configuration Registers (Memory Space) ................................................. 329

10.1.2 RPC—Root Port Configuration Register .................................................... 33110.1.4 FLRSTAT—FLR Pending Status Register ................................................... 33310.1.6 TRCR—Trapped Cycle Register ............................................................... 33410.1.7 TWDR—Trapped Write Data Register....................................................... 33410.1.9 V0CTL—Virtual Channel 0 Resource Control Register ................................. 33610.1.10V0STS—Virtual Channel 0 Resource Status Register .................................. 33610.1.11V1CTL—Virtual Channel 1 Resource Control Register ................................. 33610.1.12V1STS—Virtual Channel 1 Resource Status Register .................................. 33710.1.13REC—Root Error Command Register ....................................................... 33710.1.14LCAP—Link Capabilities Register ............................................................. 33710.1.15LCTL—Link Control Register ................................................................... 33810.1.16LLSTS—Link Status Register .................................................................. 33810.1.17DLCTL2—DMI Link Control 2 Register ...................................................... 33810.1.18DMIC—DMI Control Register .................................................................. 33810.1.19TCTL—TCO Configuration Register .......................................................... 33910.1.20D31IP—Device 31 Interrupt Pin Register.................................................. 33910.1.21D30IP—Device 30 Interrupt Pin Register.................................................. 34010.1.22D29IP—Device 29 Interrupt Pin Register.................................................. 34010.1.23D28IP—Device 28 Interrupt Pin Register.................................................. 34010.1.25D26IP—Device 26 Interrupt Pin Register.................................................. 34210.1.26D25IP—Device 25 Interrupt Pin Register.................................................. 34210.1.28D31IR—Device 31 Interrupt Route Register ............................................. 34410.1.29D30IR—Device 30 Interrupt Route Register ............................................. 34410.1.37PRSTS—Power and Reset Status Register ................................................ 35110.1.38PM_CFG—Power Management Configuration............................................. 35210.1.39DEEP_S4_POL—Deep S4/S5 From S4 Power Policies ................................. 35310.1.40DEEP_S5_POL—Deep S4/S5 From S5 Power Policies ................................. 35310.1.41RC—RTC Configuration Register ............................................................. 35310.1.42HPTC—High Precision Timer Configuration Register ................................... 35410.1.43GCS—General Control and Status Register............................................... 354


10.1.44BUC—Backed Up Control Register ...........................................................35610.1.45FD—Function Disable Register ................................................................35610.1.46CG—Clock Gating..................................................................................35910.1.47FDSW—Function Disable SUS Well ..........................................................36010.1.48FD2—Function Disable 2 ........................................................................36010.1.49GSXBAR—GPIO Serial Expander Base Address ..........................................36110.1.50GSXCTRL—GPIO Serial Expander Control Register .....................................36110.1.51MISCCTL—Miscellaneous Control Register ................................................36110.1.52USBOCM1—Overcurrent MAP Register 1...................................................36210.1.53USBOCM2—Overcurrent MAP Register 2...................................................36310.1.54RMHWKCTL- Rate Matching Hub Wake Control Register .............................363

11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................36511.1 PCI Configuration Registers (D30:F0) .................................................................365

11.1.1 VID—Vendor Identification Register (PCI-PCI—D30:F0)..............................36611.1.2 DID—Device Identification Register (PCI-PCI—D30:F0) ..............................36611.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) .............................................36611.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0) ..........................................36711.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................36811.1.6 CC—Class Code Register (PCI-PCI—D30:F0).............................................36811.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................36811.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) .................................36911.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ......................................36911.1.10SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................36911.1.11IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)................................................................................37011.1.12SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................37011.1.13MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)................................................................................37111.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) .....................................................37111.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits

Register (PCI-PCI—D30:F0) ...................................................................37111.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits

Register (PCI-PCI—D30:F0) ...................................................................37211.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ..........................37211.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0) ...........................37211.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0)...................................37211.1.20SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)................................................................................37411.1.21DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)................................................................................37411.1.22BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)................................................................................37511.1.23BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)................................................................................37611.1.24SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)................................................................................37711.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) .........................377

12 Gigabit LAN Configuration Registers ......................................................................37912.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0) ...................................................................................37912.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0) ..........................................................................38012.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0) ..........................................................................380


12.1.3 PCICMD—PCI Command Register(Gigabit LAN—D25:F0).......................................................................... 381

12.1.4 PCISTS—PCI Status Register (Gigabit LAN—D25:F0).......................................................................... 382

12.1.5 RID—Revision Identification Register (Gigabit LAN—D25:F0).......................................................................... 382

12.1.6 CC—Class Code Register (Gigabit LAN—D25:F0).......................................................................... 383

12.1.7 CLS—Cache Line Size Register (Gigabit LAN—D25:F0).......................................................................... 383

12.1.8 PLT—Primary Latency Timer Register (Gigabit LAN—D25:F0).......................................................................... 383

12.1.9 HEADTYP—Header Type Register (Gigabit LAN—D25:F0).......................................................................... 383

12.1.10MBARA—Memory Base Address Register A (Gigabit LAN—D25:F0).......................................................................... 384

12.1.11MBARB—Memory Base Address Register B(Gigabit LAN—D25:F0).......................................................................... 384

12.1.12MBARC—Memory Base Address Register C(Gigabit LAN—D25:F0).......................................................................... 385

12.1.13SVID—Subsystem Vendor ID Register(Gigabit LAN—D25:F0).......................................................................... 385

12.1.14SID—Subsystem ID Register(Gigabit LAN—D25:F0).......................................................................... 385

12.1.15ERBA—Expansion ROM Base Address Register(Gigabit LAN—D25:F0).......................................................................... 385

12.1.16CAPP—Capabilities List Pointer Register (Gigabit LAN—D25:F0).......................................................................... 386

12.1.17INTR—Interrupt Information Register(Gigabit LAN—D25:F0).......................................................................... 386

12.1.18MLMG—Maximum Latency/Minimum Grant Register(Gigabit LAN—D25:F0).......................................................................... 386

12.1.19CLIST 1—Capabilities List Register 1(Gigabit LAN—D25:F0).......................................................................... 386

12.1.20PMC—PCI Power Management Capabilities Register (Gigabit LAN—D25:F0).......................................................................... 387

12.1.21PMCS—PCI Power Management Control and StatusRegister (Gigabit LAN—D25:F0) ............................................................. 388

12.1.23CLIST 2—Capabilities List Register 2(Gigabit LAN—D25:F0).......................................................................... 389

12.1.24MCTL—Message Control Register(Gigabit LAN—D25:F0).......................................................................... 389

12.1.25MADDL—Message Address Low Register(Gigabit LAN—D25:F0).......................................................................... 389

12.1.26MADDH—Message Address High Register(Gigabit LAN—D25:F0).......................................................................... 389

12.1.27MDAT—Message Data Register(Gigabit LAN—D25:F0).......................................................................... 390

12.1.28FLRCAP—Function Level Reset Capability(Gigabit LAN—D25:F0).......................................................................... 390

12.1.29FLRCLV—Function Level Reset Capability Length and Version(Gigabit LAN—D25:F0).......................................................................... 390

12.1.301DEVCTRL—Device Control (Gigabit LAN—D25:F0) ................................... 39112.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 391

12.2.1 GBECSR1—Gigabit Ethernet Capabilities and Status Register 1 ................... 39112.2.2 GBECSR2—Gigabit Ethernet Capabilities and Status Register 2 ................... 39212.2.3 GBECSR3—Gigabit Ethernet Capabilities and Status Register 3 ................... 39212.2.4 GBECSR4—Gigabit Ethernet Capabilities and Status Register 4 ................... 39212.2.5 GBECSR5—Gigabit Ethernet Capabilities and Status Register 5 ................... 393


12.2.6 GBECSR6—Gigabit Ethernet Capabilities and Status Register 6....................39312.2.7 GBECSR7—Gigabit Ethernet Capabilities and Status Register 7....................39312.2.9 GBECSR9—Gigabit Ethernet Capabilities and Status Register 9....................394

13 LPC Interface Bridge Registers (D31:F0) ...............................................................39513.1 PCI Configuration Registers (LPC I/F—D31:F0) ....................................................395

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ..............................39613.1.2 DID—Device Identification Register (LPC I/F—D31:F0)...............................39613.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0).................................39713.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)........................................39713.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................39813.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) .............................39813.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) .....................................39813.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)....................................39813.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0) ..................................39913.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0).............................39913.1.12CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ...........................39913.1.15GPIOBASE—GPIO Base Address Register

(LPC I/F — D31:F0) ..............................................................................40113.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ................................................................................40213.1.18SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ................................................................................40313.1.20LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0) ................................................................................40413.1.21LPC_HnBDF – HPET n Bus:Device:Function(LPC I/F—D31:F0) .....................40513.1.22LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ................................................................................40613.1.23LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ................................40713.1.24GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ................................................................................40813.1.25GEN2_DEC—LPC I/F Generic Decode Range 2 Register



(LPC I/F—D31:F0) ................................................................................40913.1.29LGMR — LPC I/F Generic Memory Range

(LPC I/F—D31:F0) ................................................................................41113.1.30BIOS_SEL1—BIOS Select 1 Register

(LPC I/F—D31:F0) ................................................................................41113.1.31BIOS_SEL2—BIOS Select 2 Register

(LPC I/F—D31:F0) ................................................................................41213.1.32BIOS_DEC_EN1—BIOS Decode Enable Register

(LPC I/F—D31:F0) ................................................................................41213.1.33BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0) ................................................................................41413.1.34FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0) ................................................................................41513.1.35FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0) ................................................................................41513.1.36FDVER—Feature Detection Version

(LPC I/F—D31:F0) ................................................................................41513.1.37FVECIDX—Feature Vector Index

(LPC I/F—D31:F0) ................................................................................41613.1.38FVECD—Feature Vector Data

(LPC I/F—D31:F0) ................................................................................41613.1.39Feature Vector Space ............................................................................416


13.1.40RCBA—Root Complex Base Address Register (LPC I/F—D31:F0)................................................................................ 418

13.2 DMA I/O Registers........................................................................................... 41813.2.1 DMABASE_CA—DMA Base and Current Address Registers .......................... 41913.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................. 42013.2.3 DMAMEM_LP—DMA Memory Low Page Registers....................................... 42013.2.4 DMACMD—DMA Command Register ........................................................ 42013.2.6 DMA_WRSMSK—DMA Write Single Mask Register...................................... 42113.2.7 DMACH_MODE—DMA Channel Mode Register ........................................... 42213.2.8 DMA Clear Byte Pointer Register............................................................. 42213.2.9 DMA Master Clear Register .................................................................... 42313.2.11DMA_WRMSK—DMA Write All Mask Register ............................................ 423

13.3 Timer I/O Registers ......................................................................................... 42413.3.1 TCW—Timer Control Word Register......................................................... 42413.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register........................... 42613.3.3 Counter Access Ports Register ................................................................ 426

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 42713.4.1 Interrupt Controller I/O MAP .................................................................. 42713.4.2 ICW1—Initialization Command Word 1 Register........................................ 42713.4.3 ICW2—Initialization Command Word 2 Register........................................ 42813.4.4 ICW3—Master Controller Initialization Command

Word 3 Register ................................................................................... 42913.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register ................................................................................... 42913.4.6 ICW4—Initialization Command Word 4 Register........................................ 42913.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register .............................................................................................. 43013.4.9 OCW3—Operational Control Word 3 Register............................................ 43113.4.10ELCR1—Master Controller Edge/Level Triggered Register ........................... 43113.4.11ELCR2—Slave Controller Edge/Level Triggered Register ............................. 432

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 43213.5.1 APIC Register Map................................................................................ 43213.5.2 IND—Index Register ............................................................................. 43313.5.3 DAT—Data Register .............................................................................. 43413.5.4 EOIR—EOI Register .............................................................................. 43413.5.5 ID—Identification Register ..................................................................... 43413.5.6 VER—Version Register .......................................................................... 43513.5.7 REDIR_TBL—Redirection Table ............................................................... 435

13.6 Real Time Clock Registers................................................................................. 43713.6.1 I/O Register Address Map...................................................................... 43713.6.2 Indexed Registers ................................................................................ 437

13.7 Processor Interface Registers ............................................................................ 44113.7.1 NMI_SC—NMI Status and Control Register............................................... 44113.7.3 PORT92— Init Register.......................................................................... 44213.7.4 COPROC_ERR—Coprocessor Error Register .............................................. 442

13.8 Power Management Registers ........................................................................... 44313.8.1 Power Management PCI Configuration Registers

(PM—D31:F0) ...................................................................................... 44313.8.2 APM I/O Decode................................................................................... 45013.8.3 Power Management I/O Registers........................................................... 451

13.9 System Management TCO Registers................................................................... 46913.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................... 47013.9.2 TCO_DAT_IN—TCO Data In Register ....................................................... 47013.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 47013.9.4 TCO1_STS—TCO1 Status Register .......................................................... 47013.9.5 TCO2_STS—TCO2 Status Register .......................................................... 47213.9.6 TCO1_CNT—TCO1 Control Register......................................................... 473


13.9.7 TCO2_CNT—TCO2 Control Register .........................................................47313.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................47413.9.9 TCO_WDCNT—TCO Watchdog Control Register .........................................47413.9.10SW_IRQ_GEN—Software IRQ Generation Register.....................................47413.9.11TCO_TMR—TCO Timer Initial Value Register .............................................475

13.10 General Purpose I/O Registers (D31:F0) .............................................................47513.10.1GPIO_USE_SEL—GPIO Use Select Register...............................................47613.10.2GP_IO_SEL—GPIO Input/Output Select Register .......................................47613.10.3GP_LVL—GPIO Level for Input or Output Register......................................47713.10.4GPO_BLINK—GPO Blink Enable Register...................................................47713.10.5GP_SER_BLINK—GP Serial Blink .............................................................47813.10.6GP_SB_CMDSTS—GP Serial Blink Command Status ...................................47813.10.7GP_SB_DATA—GP Serial Blink Data.........................................................47913.10.8GPI_NMI_EN—GPI NMI Enable................................................................47913.10.9GPI_NMI_STS—GPI NMI Status ..............................................................47913.10.10GPI_INV—GPIO Signal Invert Register....................................................48013.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register .........................................48013.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register .................................48013.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................48113.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register .................................48113.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................48213.10.17GP_RST_SEL1 — GPIO Reset Select.......................................................48213.10.18GP_RST_SEL2 — GPIO Reset Select.......................................................48313.10.19GP_RST_SEL3 — GPIO Reset Select.......................................................483

13.11 GPIO Serial Expander MMIO Registers ................................................................48413.11.1GSX_CxCAP — GSX Capabilities Register 1...............................................48413.11.2GSX_CxCAP2 — GSX Capabilities Register 2 .............................................48513.11.3GSX_CxGPILVL — GSX Input Level Register DW0......................................48513.11.4GSX_CxGPILVL_DW1 — GSX Input Level Register DW1 .............................48513.11.5GSX_CxGPOLVL — GSX Output Level Register DW0...................................48513.11.6GSX_CxGPOLVL_DW1 — GSX Output Level Register DW1 ..........................48613.11.7GSX_CxCMD — GSX Command Register ..................................................486

14 SATA Controller Registers (D31:F2) .......................................................................48714.1 PCI Configuration Registers (SATA–D31:F2) ........................................................487

14.1.1 VID—Vendor Identification Register (SATA—D31:F2) .................................48814.1.2 DID—Device Identification Register (SATA—D31:F2) .................................48814.1.4 PCISTS — PCI Status Register (SATA–D31:F2) .........................................48914.1.5 RID—Revision Identification Register (SATA—D31:F2) ...............................49014.1.6 PI—Programming Interface Register (SATA–D31:F2) .................................49014.1.7 SCC—Sub Class Code Register (SATA–D31:F2) .........................................49114.1.8 BCC—Base Class Code Register

(SATA–D31:F2) ....................................................................................49114.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2) ....................................................................................49214.1.10HTYPE—Header Type

(SATA–D31:F2) ....................................................................................49214.1.11PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F2)........................................................................49214.1.12PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2) ....................................................................................49214.1.13SCMD_BAR—Secondary Command Block Base Address

Register (IDE D31:F2)...........................................................................49314.1.14SCNL_BAR—Secondary Control Block Base Address

Register (IDE D31:F2)...........................................................................49314.1.15BAR — Legacy Bus Master Base Address Register

(SATA–D31:F2) ....................................................................................493


14.1.16ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index Data Pair Base Address (SATA–D31:F2).......................................... 494

14.1.17SVID—Subsystem Vendor Identification Register (SATA–D31:F2).................................................................................... 495

14.1.18SID—Subsystem Identification Register (SATA–D31:F2) ............................ 49514.1.19CAP—Capabilities Pointer Register (SATA–D31:F2).................................... 49514.1.20INT_LN—Interrupt Line Register (SATA–D31:F2) ...................................... 49514.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................ 49514.1.22IDE_TIM — IDE Timing Register (SATA–D31:F2) ...................................... 49614.1.23SIDETIM—Slave IDE Timing Register (SATA–D31:F2)................................ 49614.1.24SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2).................................................................................... 49614.1.25SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2).................................................................................... 49714.1.26IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2).................................................................................... 49714.1.27PID—PCI Power Management Capability Identification

Register (SATA–D31:F2) ....................................................................... 49814.1.28PC—PCI Power Management Capabilities Register

(SATA–D31:F2).................................................................................... 49814.1.29PMCS—PCI Power Management Control and Status

Register (SATA–D31:F2) ....................................................................... 49914.1.30MSICI—Message Signaled Interrupt Capability Identification

(SATA–D31:F2).................................................................................... 49914.1.31MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) ........ 50014.1.33MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2)............ 50114.1.34MAP—Address Map Register (SATA–D31:F2) ............................................ 50214.1.35PCS—Port Control and Status Register (SATA–D31:F2).............................. 50314.1.36SCLKCG—SATA Clock Gating Control Register .......................................... 50414.1.37SGC—SATA General Configuration Register.............................................. 50514.1.38FLRCID—FLR Capability ID (SATA–D31:F2).............................................. 50714.1.39FLRCLV—FLR Capability Length and Version (SATA–D31:F2) ...................... 50714.1.40FLRC—FLR Control (SATA–D31:F2) ......................................................... 50714.1.41ATC—APM Trapping Control Register (SATA–D31:F2) ................................ 50814.1.42ATS—APM Trapping Status Register (SATA–D31:F2) ................................. 50814.1.43SP Scratch Pad Register (SATA–D31:F2) ................................................. 50814.1.44BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................... 50914.1.45BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................ 51014.1.46BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................ 510

14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 51114.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 51214.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ............................... 51314.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F2) ................................................................................ 51314.2.4 AIR—AHCI Index Register (D31:F2)........................................................ 51414.2.5 AIDR—AHCI Index Data Register (D31:F2) .............................................. 514

14.3 Serial ATA Index/Data Pair Superset Registers .................................................... 51414.3.1 SINDX – Serial ATA Index (D31:F2)........................................................ 51514.3.2 SDATA – Serial ATA Data (D31:F2)......................................................... 515

14.4 AHCI Registers (D31:F2) .................................................................................. 51914.4.1 AHCI Generic Host Control Registers (D31:F2) ......................................... 51914.4.2 Port Registers (D31:F2) ........................................................................ 527

15 SATA Controller Registers (D31:F5)....................................................................... 54115.1 PCI Configuration Registers (SATA–D31:F5)........................................................ 541

15.1.1 VID—Vendor Identification Register (SATA—D31:F5) ................................ 54215.1.2 DID—Device Identification Register (SATA—D31:F5)................................. 54215.1.3 PCICMD—PCI Command Register (SATA–D31:F5)..................................... 543


15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) .........................................54415.1.5 RID—Revision Identification Register (SATA—D31:F5) ...............................54515.1.6 PI—Programming Interface Register (SATA–D31:F5) .................................54515.1.7 SCC—Sub Class Code Register (SATA–D31:F5) .........................................54515.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5).................................................................54615.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5) ....................................................................................54615.1.10PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F5)........................................................................54615.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5) ....................................................................................54615.1.12SCMD_BAR—Secondary Command Block Base Address

Register (IDE D31:F1)...........................................................................54715.1.13SCNL_BAR—Secondary Control Block Base Address

Register (IDE D31:F1)...........................................................................54715.1.14BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5) ....................................................................................54715.1.15SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5) ....................................................................................54815.1.16SVID—Subsystem Vendor Identification Register

(SATA–D31:F5) ....................................................................................54815.1.17SID—Subsystem Identification Register (SATA–D31:F5).............................54815.1.18CAP—Capabilities Pointer Register (SATA–D31:F5) ....................................54815.1.19INT_LN—Interrupt Line Register (SATA–D31:F5).......................................54915.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5) ........................................54915.1.21IDE_TIM — IDE Timing Register (SATA–D31:F5).......................................54915.1.22SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5) ....................................................................................55015.1.23SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5) ....................................................................................55015.1.24IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5) ....................................................................................55115.1.25PID—PCI Power Management Capability Identification

Register (SATA–D31:F5)........................................................................55115.1.26PC—PCI Power Management Capabilities Register

(SATA–D31:F5) ....................................................................................55115.1.27PMCS—PCI Power Management Control and Status

Register (SATA–D31:F5)........................................................................55215.1.28MAP—Address Map Register (SATA–D31:F5)16 .........................................55215.1.29PCS—Port Control and Status Register (SATA–D31:F5) ..............................55315.1.30SATACR0— SATA Capability Register 0 (SATA–D31:F5) .............................55415.1.31SATACR1— SATA Capability Register 1 (SATA–D31:F5) .............................55415.1.32FLRCID— FLR Capability ID (SATA–D31:F5) .............................................55415.1.33FLRCLV— FLR Capability Length and Value (SATA–D31:F5) ........................55515.1.34FLRCTRL— FLR Control (SATA–D31:F5) ...................................................55515.1.35ATS—APM Trapping Status Register (SATA–D31:F5)..................................55515.1.36ATC—APM Trapping Control (SATA–D31:F5).............................................556

15.2 Bus Master IDE I/O Registers (D31:F5)...............................................................55615.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ..........................55715.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)................................55715.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F5).................................................................................55815.3 Serial ATA Index/Data Pair Superset Registers.....................................................558

15.3.1 SINDX—SATA Index Register (D31:F5)....................................................55815.3.2 SDATA—SATA Index Data Register (D31:F5) ............................................559

16 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only)...............................563


16.1 Register Attribute Definitions ............................................................................ 56316.2 SCU Physical Function Configuration Registers..................................................... 565

16.2.1 PCI Standard Header Registers .............................................................. 56716.2.2 PF Power Management Capability Structure ............................................. 57416.2.3 PF MSI-X Capability Structure ................................................................ 57616.2.4 PF PCI Express* Capability Structure ...................................................... 57716.2.5 PF Advanced Error Reporting Extended Capability Structure ....................... 58216.2.6 PF Alternative Routing ID Extended Capability Structure ............................ 58616.2.7 PF SR-IOV Extended Capability Structure................................................. 58716.2.8 PF TPH Requester Extended Capability Structure ...................................... 592

16.3 SCU Virtual Function Configuration Registers....................................................... 59416.3.1 PCI Standard Header Registers .............................................................. 59516.3.2 VF MSI-X Capability Structure ................................................................ 60016.3.3 VF PCI Express* Capability Structure ...................................................... 60216.3.4 VF Advanced Error Reporting Extended Capability Structure ....................... 60616.3.5 Advanced Error Header Log Registers...................................................... 61116.3.6 VF Alternative Routing ID Extended Capability Structure............................ 61216.3.7 VF TPH Requester Extended Capability Structure ...................................... 613

16.4 SCU SGPIO Memory Mapped Registers ............................................................... 61416.4.1 SGICR- SGPIO Interface Control Register ................................................ 61416.4.2 SGPBR- SGPIO Programmable Blink Register............................................ 61516.4.3 SGSDLR- SGPIO Start Drive Lower Register ............................................. 61616.4.4 SGSDUR- SGPIO Start Drive Upper Register............................................. 61716.4.5 SGSIDLR- SGPIO Input Data Lower Register ............................................ 61816.4.6 SGSIDUR- SGPIO Input Data Upper Register............................................ 61816.4.7 SGVSCR- SGPIO Vendor Specific Code Register ........................................ 61816.4.8 SGODSR[0-7]—SGPIO Output Data Select Register[0-7] ........................... 620

17 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 62117.1 USB EHCI Configuration Registers

(USB EHCI—D29:F0, D26:F0) ........................................................................... 62117.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62217.1.2 DID—Device Identification Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62217.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62417.1.6 PI—Programming Interface Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62517.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62517.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62517.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62517.1.10HEADTYP—Header Type Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62617.1.11MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62617.1.12SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62617.1.13SID—USB EHCI Subsystem ID Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62717.1.14CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 62717.1.15INT_LN—Interrupt Line Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 627


17.1.16INT_PN—Interrupt Pin Register (USB EHCI—D29:F0, D26:F0).................................................................627

17.1.17PWR_CAPID—PCI Power Management Capability IDRegister (USB EHCI—D29:F0, D26:F0) ....................................................628

17.1.18NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F0, D26:F0).................................................................628

17.1.19PWR_CAP—Power Management Capabilities Register (USB EHCI—D29:F0, D26:F0).................................................................628

17.1.20PWR_CNTL_STS—Power Management Control/Status Register (USB EHCI—D29:F0, D26:F0) ..........................................629

17.1.21DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F0, D26:F0).................................................................629

17.1.22NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F0, D26:F0).................................................................630

17.1.23DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F0, D26:F0).................................................................630

17.1.24USB_RELNUM—USB Release Number Register (USB EHCI—D29:F0, D26:F0).................................................................630

17.1.25FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F0, D26:F0).................................................................630

17.1.26PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F0, D26:F0).................................................................631

17.1.27LEG_EXT_CAP—USB EHCI Legacy Support ExtendedCapability Register (USB EHCI—D29:F0, D26:F0)......................................632

17.1.28LEG_EXT_CS—USB EHCI Legacy Support ExtendedControl / Status Register (USB EHCI—D29:F0, D26:F0) .............................632

17.1.29SPECIAL_SMI—Intel® Specific USB 2.0 Intel® SMI Register (USB EHCI—D29:F0, D26:F0) ....................................................634

17.1.30ACCESS_CNTL—Access Control Register (USB EHCI—D29:F0, D26:F0).................................................................635

17.1.31EHCIIR1—EHCI Initialization Register 1(USB EHCI—D29:F0, D26:F0).................................................................635

17.1.32EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F0, D26:F0) .........63617.1.33FLR_CID—Function Level Reset Capability ID

(USB EHCI—D29:F0, D26:F0).................................................................63617.1.35FLR_CLV—Function Level Reset Capability Length and Version

(USB EHCI—D29:F0, D26:F0).................................................................63717.1.36FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0).................................................................63717.1.37FLR_STAT—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0).................................................................63817.1.38EHCIIR3—EHCI Initialization Register 3 (USB EHCI—D29:F0, D26:F0) .........63817.1.39EHCIIR4—EHCI Initialization Register 4 (USB EHCI—D29:F0, D26:F0) .........638

17.2 Memory-Mapped I/O Registers ..........................................................................63917.2.1 Host Controller Capability Registers.........................................................63917.2.2 Host Controller Operational Registers ......................................................64217.2.3 USB 2.0-Based Debug Port Registers.......................................................652

18 Intel® High Definition Audio Controller Registers (D27:F0)....................................65518.1 Intel® HD Audio PCI Configuration Space (Intel HD Audio—D27:F0) .......................655

18.1.1 VID—Vendor Identification Register (Intel® HD Audio Controller—D27:F0) .....................................................656

18.1.2 DID—Device Identification Register(Intel® High Definition Audio Controller—D27:F0) .....................................657

18.1.3 PCICMD—PCI Command Register(Intel® HD Audio Controller—D27:F0) .....................................................657

18.1.4 PCISTS—PCI Status Register(Intel® HD Audio Controller—D27:F0) .....................................................658


18.1.5 RID—Revision Identification Register(Intel® HD Audio Controller—D27:F0) ..................................................... 658

18.1.6 PI—Programming Interface Register (Intel® HD Audio Controller—D27:F0) ..................................................... 658

18.1.8 BCC—Base Class Code Register (Intel® HD Audio Controller—D27:F0) ..................................................... 659

18.1.9 CLS—Cache Line Size Register(Intel® HD Audio Controller—D27:F0) ..................................................... 659

18.1.10LT—Latency Timer Register(Intel® HD Audio Controller—D27:F0) ..................................................... 659

18.1.11HEADTYP—Header Type Register(Intel® HD Audio Controller—D27:F0) ..................................................... 659

18.1.13HDBARU—Intel® HD Audio Upper Base Address Register(Intel® HD Audio Controller—D27:F0) ..................................................... 660

18.1.14SVID—Subsystem Vendor Identification Register (Intel® High Definition Audio Controller—D27:F0)..................................... 660

18.1.16CAPPTR—Capabilities Pointer Register (Intel® HD Audio Controller—D27:F0) ..................................................... 661

18.1.17INTLN—Interrupt Line Register (Intel® HD Audio Controller—D27:F0) ..................................................... 661

18.1.18INTPN—Interrupt Pin Register (Intel® HD Audio Controller—D27:F0) ..................................................... 661

18.1.20HDINIT1—Intel® High Definition Audio Initialization Register 1 (Intel® High Definition Audio Controller—D27:F0)..................................... 662

18.1.21PID—PCI Power Management Capability ID Register (Intel® HD Audio Controller—D27:F0) ..................................................... 662

18.1.22PC—Power Management Capabilities Register (Intel® HD Audio Controller—D27:F0) ..................................................... 662

18.1.23PCS—Power Management Control and Status Register (Intel® HD Audio Controller—D27:F0) ..................................................... 663

18.1.24MID—MSI Capability ID Register (Intel® HD Audio Controller—D27:F0) ..................................................... 663

18.1.25MMC—MSI Message Control Register (Intel® HD Audio Controller—D27:F0) ..................................................... 664

18.1.26MMLA—MSI Message Lower Address Register (Intel® HD Audio Controller—D27:F0) ..................................................... 664

18.1.27MMUA—MSI Message Upper Address Register (Intel® HD Audio Controller—D27:F0) ..................................................... 664

18.1.28MMD—MSI Message Data Register (Intel® HD Audio Controller—D27:F0) ..................................................... 664

18.1.30PXC—PCI Express* Capabilities Register (Intel® HD Audio Controller—D27:F0) ..................................................... 665

18.1.31DEVCAP—Device Capabilities Register (Intel® HD Audio Controller—D27:F0) ..................................................... 665

18.1.32DEVC—Device Control Register (Intel® HD Audio Controller—D27:F0) ..................................................... 666

18.1.33DEVS—Device Status Register (Intel® HD Audio Controller—D27:F0) ..................................................... 666

18.1.34VCCAP—Virtual Channel Enhanced Capability Header(Intel® HD Audio Controller—D27:F0) ..................................................... 667

18.1.35PVCCAP1—Port VC Capability Register 1(Intel® HD Audio Controller—D27:F0) ..................................................... 667

18.1.36PVCCAP2 — Port VC Capability Register 2(Intel® HD Audio Controller—D27:F0) ..................................................... 667

18.1.37PVCCTL — Port VC Control Register(Intel® HD Audio Controller—D27:F0) ..................................................... 668

18.1.38PVCSTS—Port VC Status Register(Intel® HD Audio Controller—D27:F0) ..................................................... 668


18.1.39VC0CAP—VC0 Resource Capability Register(Intel® HD Audio Controller—D27:F0) .....................................................668

18.1.40VC0CTL—VC0 Resource Control Register(Intel® HD Audio Controller—D27:F0) .....................................................669

18.1.41VC0STS—VC0 Resource Status Register(Intel® HD Audio Controller—D27:F0) .....................................................669

18.1.42VCiCAP—VCi Resource Capability Register(Intel® HD Audio Controller—D27:F0) .....................................................669

18.1.43VCiCTL—VCi Resource Control Register(Intel® HD Audio Controller—D27:F0) .....................................................670

18.1.44VCiSTS—VCi Resource Status Register(Intel® HD Audio Controller—D27:F0) .....................................................670

18.1.45RCCAP—Root Complex Link Declaration EnhancedCapability Header Register (Intel® HD Audio Controller—D27:F0)................670

18.1.46ESD—Element Self Description Register(Intel® HD Audio Controller—D27:F0) .....................................................671

18.1.47L1DESC—Link 1 Description Register(Intel® HD Audio Controller—D27:F0) .....................................................671

18.1.48L1ADDL—Link 1 Lower Address Register(Intel® HD Audio Controller—D27:F0) .....................................................671

18.1.49L1ADDU—Link 1 Upper Address Register(Intel® HD Audio Controller—D27:F0) .....................................................671

18.2 Intel® HD Audio Memory Mapped Configuration Registers (Intel® HD Audio— D27:F0)................................................................67218.2.1 GCAP—Global Capabilities Register

(Intel® HD Audio Controller—D27:F0).....................................................67518.2.2 VMIN—Minor Version Register

(Intel® HD Audio Controller—D27:F0).....................................................67518.2.3 VMAJ—Major Version Register

(Intel® HD Audio Controller—D27:F0).....................................................67618.2.4 OUTPAY—Output Payload Capability Register

(Intel® HD Audio Controller—D27:F0).....................................................67618.2.5 INPAY—Input Payload Capability Register

(Intel® HD Audio Controller—D27:F0).....................................................67618.2.6 GCTL—Global Control Register

(Intel® HD Audio Controller—D27:F0).....................................................67718.2.8 STATESTS—State Change Status Register

(Intel® HD Audio Controller—D27:F0).....................................................67818.2.9 GSTS—Global Status Register

(Intel® HD Audio Controller—D27:F0).....................................................67818.2.11INSTRMPAY—Input Stream Payload Capability

(Intel® HD Audio Controller—D27:F0).....................................................67918.2.12INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................67918.2.13INTSTS—Interrupt Status Register

(Intel® HD Audio Controller—D27:F0).....................................................68018.2.15SSYNC—Stream Synchronization Register

(Intel® HD Audio Controller—D27:F0).....................................................68118.2.16CORBLBASE—CORB Lower Base Address Register

(Intel® HD Audio Controller—D27:F0).....................................................68118.2.17CORBUBASE—CORB Upper Base Address Register

(Intel® HD Audio Controller—D27:F0).....................................................68218.2.18CORBWP—CORB Write Pointer Register

(Intel® HD Audio Controller—D27:F0).....................................................68218.2.19CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0).....................................68218.2.21CORBST—CORB Status Register

(Intel® HD Audio Controller—D27:F0)...........

intel x79 express chipset · 2 intel® c600 series chipset and intel® x79 express chipset...

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