intel® wireless communications and computing package users guide

Intel® Wireless Communications and Computing Package User’s GuideVersion 1.5

April 2005

Order Number: 253418-005

Intel® Wireless Communications and Computing Package User’s Guide

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Contents1 Packaging Overview .........................................................................................................................1-1

1.1 Handheld Wireless Package Revolution ..............................................................................1-21.2 From CSP to SCSP .............................................................................................................1-21.3 Intel® PCA Processor and Flash Memory ...........................................................................1-4

2 Packaging Technology .....................................................................................................................2-1

2.1 Introduction ..........................................................................................................................2-12.2 Product Packages for Flash Memory ...................................................................................2-1

2.2.1 Intel® UT-SCSP for Flash Memory.........................................................................2-22.2.2 SCSP for Flash Memory .........................................................................................2-42.2.3 VF-BGA Package for Flash Memory.......................................................................2-62.2.4 Easy BGA Package for Flash Memory ...................................................................2-7

2.3 Product Packages for Intel® PCA Cellular Processors .....................................................2-102.3.1 Intel® Folded-SCSP for Intel® PCA Cellular Processors .....................................2-102.3.2 SCSP for Intel® PCA Cellular Processors............................................................2-132.3.3 VF-BGA Package for Intel® PCA Cellular Processors .........................................2-152.3.4 PBGA Package for Intel® PCA Cellular Processors.............................................2-20

3 Shipping Media Information ..............................................................................................................3-1

3.1 Overview ..............................................................................................................................3-13.2 Shipping Media ....................................................................................................................3-1

3.2.1 Tape and Reel ........................................................................................................3-13.2.2 JEDEC Trays ..........................................................................................................3-23.2.3 Electrical Samples ..................................................................................................3-23.2.4 CSP Shipping Media Orientation ............................................................................3-9

3.3 Shipping Media and Socket Ordering Information ...............................................................3-93.3.1 Ordering Information .............................................................................................3-10

3.4 CSP Device Markings and Shipping Labels.......................................................................3-103.4.1 Device Markings ...................................................................................................3-103.4.2 Shipping Labels ....................................................................................................3-10

3.5 Handling and Floor Life ......................................................................................................3-113.5.1 Handling................................................................................................................3-11

3.5.1.1 Manual Handling..................................................................................3-123.5.1.2 PCB Design Considerations ................................................................3-12

3.5.2 Floor Life ...............................................................................................................3-12

4 Thermal Specification Methodology..................................................................................................4-1

4.1 Introduction ..........................................................................................................................4-14.2 Objective of Thermal Management ......................................................................................4-14.3 Thermal Specifications.........................................................................................................4-14.4 Maximum Case Temperature...............................................................................................4-24.5 Case Temperature Measurements ......................................................................................4-2

5 Manufacturing Considerations ..........................................................................................................5-1

5.1 SMT Process .......................................................................................................................5-15.2 PCB Design Guidelines .......................................................................................................5-1

5.2.1 PCB Escape Routing ..............................................................................................5-2

Intel® Wireless Communications and Computing Package User’s Guide 3

5.2.2 PCB Keep-out zones ..............................................................................................5-25.2.3 Land Pad Styles......................................................................................................5-35.2.4 PCB Line Widths and Spaces.................................................................................5-35.2.5 Vias and Land Pads................................................................................................5-55.2.6 Surface Finishes .....................................................................................................5-65.2.7 HDI PCB Technologies...........................................................................................5-65.2.8 Multi-Site Layout Files.............................................................................................5-7

5.3 Package to Board Assembly Process..................................................................................5-85.3.1 Solder Paste ...........................................................................................................5-85.3.2 Solder Stencils ........................................................................................................5-95.3.3 Placement and Alignment .......................................................................................5-95.3.4 Solder Reflow........................................................................................................5-105.3.5 Double-Sided PCB Process..................................................................................5-125.3.6 PCB Cleaning .......................................................................................................5-135.3.7 Inspection..............................................................................................................5-135.3.8 Rework..................................................................................................................5-155.3.9 Flux Only Attachment............................................................................................5-155.3.10 Reballing...............................................................................................................5-155.3.11 Test Accessories...................................................................................................5-16

5.4 Programming Considerations ............................................................................................5-165.4.1 On-Board Programming (OBP).............................................................................5-165.4.2 Off-Board Programmers (OFBP) ..........................................................................5-175.4.3 The Intel® Flash Memory Programmer ................................................................5-175.4.4 Distributors Value-Added Programming Service ..................................................5-185.4.5 Independent Programming Services.....................................................................5-18

6 Tools and Software Support .............................................................................................................6-1

6.1 Introduction and Overview ...................................................................................................6-16.2 Web Tools............................................................................................................................6-16.3 Intel® Flash Memory Software ............................................................................................6-2

6.3.1 Intel® Persistent Storage Manager.........................................................................6-26.3.2 Intel® Flash Data Integrator....................................................................................6-26.3.3 Intel® Virtual Small Block File Manager .................................................................6-2

7 Quality and Reliability Engineering ...................................................................................................7-1

7.1 Introduction ..........................................................................................................................7-17.2 Q&R in Technology Development........................................................................................7-17.3 Q&R in Product Development..............................................................................................7-27.4 Q&R in Manufacturing..........................................................................................................7-37.5 Customer Service & Support ...............................................................................................7-3

8 Lead-Free Program Overview ..........................................................................................................8-1

8.1 Introduction ..........................................................................................................................8-18.2 Direction...............................................................................................................................8-18.3 Higher Peak Temperature Reflow........................................................................................8-18.4 Lead-Free Package Moisture Sensitivity Level....................................................................8-28.5 Lead-Free Alloy Selection....................................................................................................8-28.6 Lead-Free Process Recommendations ...............................................................................8-28.7 Halogen-Free Overview .......................................................................................................8-38.8 References...........................................................................................................................8-3

A Appendix ........................................................................................................................ A-1

4 Intel® Wireless Communications and Computing Package User’s Guide

Figures

Figure 1-1 Growth of Density Requirements ................................................................................. 1-2Figure 1-2 Wireless Memory Package Trends .............................................................................. 1-3Figure 1-3 SCSP Evolution ........................................................................................................... 1-4Figure 1-4 Intel® PCA Processor ................................................................................................. 1-5Figure 1-5 Leadership Packaging Technologies ........................................................................... 1-6Figure 2-1 Intel® UT-SCSP BT for Flash Memory (Example) ....................................................... 2-2Figure 2-2 Intel® UT-SCSP BT Substrate Package for Flash Memory (Example) ........................ 2-3Figure 2-3 SCSP for Flash Memory (Example) ............................................................................ 2-4Figure 2-4 SCSP Drawing and Dimensions for Flash Memory (Example) ................................... 2-5Figure 2-5 VF-BGA Package for Flash Memory (Example) .......................................................... 2-6Figure 2-6 VF-BGA Package Drawing and Dimensions for Flash Memory (Example) ................. 2-7Figure 2-7 Easy BGA Package for Flash Memory (Example) ....................................................... 2-8Figure 2-8 Easy BGA Package Drawing and Dimensions for Flash Memory (Example) .............. 2-9Figure 2-9 Intel® Folded-SCSP Package for Intel® PCA Cellular Processors (Example) ........... 2-10Figure 2-10 Intel® Folded-SCSP for Intel® PCA Cellular Processor (8x11 Top Example) .......... 2-11Figure 2-11 Intel® Folded-SCSP for Intel® PCA Cellular Processor (11x13 Top Example) ........ 2-12Figure 2-12 SCSP for Intel® PCA Cellular Processors (Example) ............................................... 2-13Figure 2-13 SCSP (Typical 0.65 Pitch) Drawing for Intel® PXA26X (Example) ........................... 2-14Figure 2-14 VF-BGA Package (0.50 Pitch) for Intel® PCA Cellular Processors (Example) ......... 2-15Figure 2-15 VF-BGA Drawing (0.50 Pitch) for Intel® PCA Cellular Processors (Example) .......... 2-16Figure 2-16 VF-BGA Package (0.65 Pitch) for Intel® PCA Cellular Processors (Example) ......... 2-17Figure 2-17 VF-BGA (0.65 Pitch) Drawing for the Intel® PXA800F Processor (Example) ........... 2-18Figure 2-18 VF-BGA Package (0.50 Pitch) for Intel® PCA Cellular Processors (Example) ......... 2-18Figure 2-19 VF-BGA (0.50 Pitch) Drawing for an Intel® X-Scale Processor (Example) ............... 2-19Figure 2-20 PBGA Package (1.0 Pitch) for Intel® PCA Cellular Processors (Example) .............. 2-20Figure 2-21 PBGA Drawing for the Intel® PXA255 Processor (Example) .................................... 2-21Figure 3-1 Tape-in-Tube Example ................................................................................................ 3-2Figure 3-2 Carrier Tape Diagram .................................................................................................. 3-3Figure 3-3 Carrier Tape Reel Diagram (All Packages) ................................................................. 3-5Figure 3-4 Injection Molded Thin JEDEC Tray ............................................................................. 3-6Figure 3-5 CSP Package Shipping Media Orientation .................................................................. 3-9Figure 3-6 Typical Device Mark .................................................................................................. 3-10Figure 3-7 Moisture Barrier Bag (MBB) ...................................................................................... 3-11Figure 4-1 Case Temperature Equation ....................................................................................... 4-2Figure 4-2 Technique for Measuring Tcase with Zero Degree Angle Attachment ........................ 4-3Figure 4-3 Technique for Measuring Tcase with Ninety Degree Angle Attachment ..................... 4-3Figure 5-1 Escape Routing Diagram ............................................................................................. 5-2Figure 5-2 Land Pad Style Profiles ............................................................................................... 5-3Figure 5-3 Single Track Routing PCB Design Guidelines: 0.65 mm to 1.0 mm Packages ........... 5-4Figure 5-4 Single Track Routing PCB Design Guidelines: 0.5 mm Packages .............................. 5-5Figure 5-5 Sample Multi-Site Layout Diagram .............................................................................. 5-8Figure 5-6 Solder Stencil Design Guidelines ................................................................................ 5-9Figure 5-7 Package Self-Alignment at Solder Reflow ................................................................. 5-10Figure 5-8 Reflow Profile Guidelines: Pb/Sn Paste .................................................................... 5-11Figure 5-9 Reflow Profile Guidelines: Sn, Ag, and Cu Lead-Free Paste .................................... 5-12Figure 5-10 Cross Section of Double-Sided PCB using CSP Packages ...................................... 5-13Figure 5-11 Results of Typical Transmission X-Ray ..................................................................... 5-13Figure 5-12 Cross-section X-Ray of an Intel® Folded-SCSP ....................................................... 5-14Figure 5-13 Signal Traces Designed for Package Alignment ....................................................... 5-14


Figure 7-1 Finite Element Analysis ............................................................................................... 7-1Figure 7-2 Example of Temperature Cycling Data ........................................................................ 7-2

Appendix-Figures

Figure 1 Dual Image Overlaid Alignment of CSP Solder Bumps and Flux Paste Pattern of PCB ............................................................................................................... 3

Figure 2 Stage 1: Gel Flux Transfer from Dip Block to Solder Ball ............................................... 3Figure 3 Stage 2: Component is Dipped into Gel Flux ................................................................. 4Figure 4 Stage 3: Component is Dipped into Gel Flux ................................................................. 4Figure 5 Squeegee Printing of Solder Paste ................................................................................ 5Figure 6 Good Printing Inspection ................................................................................................ 5Figure 7 Solder-Paste Pre-Reflow of Component after Printing and Placement to PCB .............. 5Figure 8 Standard Reflow Profile .................................................................................................. 7Figure 9 Typical Lead-free Profile ................................................................................................. 8Figure 10 Metcal’s APR-5000 Array Package Rework System ...................................................... 9Figure 11 Solder Removal with Wick and Blade Tip ..................................................................... 10Figure 12 Solder Removal with Wick and Blade Tip ..................................................................... 10Figure 13 Good Solder Joint Shown on Vision System ................................................................ 11Figure 14 Balls Show Evidence of Voids (Left) and Perfect X-Ray of CSP (Right) ...................... 11

Tables

Table 2-1 VF-BGA Dimensions for an X-Scale Processor (Example) ........................................2-19Table 3-1 SCSP Carrier Tape Dimensions...................................................................................3-3Table 3-2 VF-BGA, Easy BGA, PBGA Carrier Tape Dimensions.................................................3-4Table 3-3 SCSP Injection Molded Thin JEDEC Tray Parameters ................................................3-6Table 3-4 VF-BGA, Easy BGA, PBGA, Injected Molded Thin JEDEC Parameters ......................3-7Table 3-5 Discrete VF-BGA / Easy BGA Package Sizes (mm) ....................................................3-8Table 5-1 Essentials for Assembly Quality ...................................................................................5-1Table 5-2 Dimensions: 0.65 mm to 1.0 mm Packages .................................................................5-4Table 5-3 Dimensions for 0.5 mm Packages................................................................................5-5Table 5-4 Typical Design Rules for PCBs.....................................................................................5-6Table 5-5 Dimensions for Solder Stencil Design ..........................................................................5-9Table 5-6 Solder Reflow Profile Targets .....................................................................................5-11Table 5-7 Reflow Profile Targets for Sn/Ag/Cu Solder ...............................................................5-12Table 5-8 Additional Information .................................................................................................5-17Table 8-1 Alloy Selection Considerations .....................................................................................8-2

Appendix-Tables

Table 1 Standard Reflow ..............................................................................................................6Table 2 Lead-free Reflow .............................................................................................................7

Acknowledgement

Intel would like to thank Metcal, an OK International company, for the contributing article in Appendix A.OK International Inc.1530 O’Brien DriveMenlo Park, CA 94025650 325-3291

6 Intel® Wireless Communications and Computing Package User’s Guide

Revision History

Date of Revision Version Description

September 03 -001 Initial Release.

March 04 -002 Updated the package drawings for Intel® PCA Cellular Processor, 8x11 and 11x13 examples.Added Appendix A.

April 04 -003 Updated vendor part numbers in Table 3-3 and 3-4. Updated VF-BGA package sizes in Table 3-5.

May 04 -004 Updated the titles and headings of tables 5-2 and 5-3.

April 05 -005 Changed the Note for Figure 3-4 “Injection Molded Thin JEDEC Tray” on page 3-6 to say “inches” instead of “millimeters.” Revised Figure 3-5 “CSP Package Shipping Media Orientation” on page 3-9.


Chapter 1 Packaging Overview

Packaging Overview 1

The convergence of communication and computing in small handheld wireless devices is driving a handheld wireless revolution across the entire industry and the world. The demand for small handheld wireless devices is increasing at an enormous rate due to new features such as color displays, internet access, games, music, E-mail, digital camera/video capabilities, and more. These small handheld wireless devices provide constant computing connectivity to everyone, anytime and anywhere in the world.

The Intel® Wireless Communications and Computing Group offers a wide range of handheld wireless semiconductor products and packages to meet the needs of this rapidly growing market. The following Intel® Personal Internet Client Architecture (Intel® PCA) and Intel® Flash Memory products are the building blocks for a wide range of high-performance, low-voltage handheld wireless devices in this market segment:

• Intel® PCA Processors using Intel® XScale™ technology

• Intel® Micro Signal Architecture (Intel® MSA)

• Intel® Flash Memory products, plus RAM technologies

This Intel® Wireless Communications and Computing Package User's Guide is intended to help Intel customers understand and implement Intel® PCA and Intel® Flash Memory product packages into their manufacturing process. It is an easy-to-use reference guide that provides information on every stage of the product life cycle, including product definition, design, prototype, and production. The Intel® Wireless Communications and Computing Package User's Guide includes a wide variety of topics such as:

• Product/ Package applications

• Package information

• Shipping media and handling

• SMT (Surface Mount Technology) guidelines

• PCB (Printed Circuit Board) design recommendations

• Lead-free information

• Quality and reliability

• Manufacturing tools and software

• Other application notes

The Intel® Wireless Communications and Computing Package User's Guide is available in both CD and on-line versions. Intel has attempted to provide as much Intel® PCA and Intel® Flash Memory packaging information as possible but since silicon and packaging technology is evolving as rapidly as handheld wireless devices, the contents of this guide will continue to evolve. Please visit Intel's website for the latest updated version.

Intel® Wireless Communications and Computing Package User’s Guide 1-1

Packaging Overview

1.1 Handheld Wireless Package Revolution

The convergence of communication and computing has driven the integration of high performance and features. Both are essential for a computing environment supporting small, low-power, wireless handheld devices with new cellular communication features and long battery life. The need for additional performance and features has driven an increased need for processor performance and total memory density as shown in Figure 1-1.

Source: Intel

The challenge for the industry is to integrate new features while simultaneously reducing the size and weight of wireless handheld devices. Innovation in package technology has made it possible to meet this challenge.

1.2 From CSP to SCSP

The trend in the early 90’s for wireless handheld packages was to reduce the total package area by moving from lead-frame-based Small Outline Packages (SOP) to a very thin, fine pitch ball grid array device (VF-BGA), a move resulting in an eighty percent reduction in package size.

The term Chip Scale Package (CSP) generally refers to a package that is no more than twenty percent larger than the silicon it contains. Intel has introduced many single silicon, discrete CSP flash products in VF-BGA packages. The VF-BGA package model has enabled size reductions for wireless handheld devices until the recent emergence of the Stacked Chip Scale Package (SCSP). And now the SCSP continues to fuel the trend of reducing package size.

SCSP includes Intel® Flash Memory products and various types of RAM dies that are stacked vertically in one package. As shown in Figure 1-2, the emergence of the SCSP in the late 90’s has been key to reducing the size and weight of small handheld devices to allow for increased memory density.

Figure 1-1. Growth of Density Requirements

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1-2 Intel® Wireless Communications and Computing Package User’s Guide

Packaging Overview

The first SCSP from Intel was introduced in 1998 and contained only two dies—one flash die and one SRAM die in a 1.4 mm profile height FBGA package. With increased memory requirements, package technology has improved and a current SCSP device can stack up to five dies in a 1.0 mm profile height Intel® Ultra-Thin Stacked Chip Scale Package (Intel® UT-SCSP), as shown in Figure 1-3.

Figure 1-2. Wireless Memory Package Trends

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Packaging Overview

As the silicon manufacturing lithography process continues to improve by shrinking die sizes from 0.25 µm to 0.18 µm to 0.13 µm and below, the total length and width of the SCSP size decreases accordingly. Added to these silicon process technology improvements and package technology improvements are developments in Intel® Flash technology such as Multi-Level Cell (MLC) technology in products such as Intel StrataFlash® wireless memory. Intel StrataFlash® wireless memory further reduces the size of the silicon cell structure by stacking silicon cells vertically within the array.

RAM memory technology also continues to evolve. In the early stages of the handheld wireless revolution, only SRAM technology was used in the SCSP. As RAM density requirements have grown, Pseudo-SRAM (PSRAM) has been included in SCSPs as well. PSRAM provides higher RAM densities using DRAM core with an interface similar to an SRAM. The trend will continue with integration of low-power SDRAM in the next generation of products.

An early SCSP version contained two dies—8 Mb Flash with a 2 Mb SRAM—in a package measuring 8 x 10 x 1.4 mm. More recently, Intel introduced a SCSP consisting of five dies, with densities of 512 Mb Flash, 128 Mb PSRAM, and 8 Mb SRAM in an 8 x 11 x 1.2 mm Intel® UT-SCSP package—more than sixty times the amount of memory density combined in almost the same package size! This is how Intel® Flash Memory packaging and silicon technology is responding to the explosive growth of memory density requirement in the wireless handheld revolution.

1.3 Intel® PCA Processor and Flash Memory

The Intel® PCA Processor provides performance and low-voltage advantages for small wireless handheld devices, simultaneously enabling even smaller form factor solutions in combinations with Intel® Flash Memory products. Intel® PCA Processors include the Intel® PXA255, the Intel® PXA26x, and the Intel® PXA800F product families.

Figure 1-3. SCSP Evolution

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Packaging Overview

Shown in Figure 1-4, “Intel® PCA Processor” on page 1-5, the Intel® PCA Processor is designed specifically for small wireless handheld devices and can be combined with Intel® Flash Memory products to provide great performance advantages using several approaches such as:

• Intel® Flash Memory device stacked with Intel® PXA26x Processor Family.

• Intel® On-Chip Flash Memory device integrated directly with Intel® PXA800F Cellular Processor silicon.

The PXA26x Processor family stacks either a 128- Mb or a 256-Mb Intel® Flash Memory device within one SCSP, and the Intel® PXA800F Cellular processor integrates a 32-Mb Intel® On-Chip Flash Memory device directly into the processor silicon. These devices complement one another as each provides its specific benefits.

While the total density requirement for the Intel® Flash Memory device (Flash and RAM stacks) continues to grow, smaller memory density requirements for Intel® On-Chip Flash Memory instruction cache can remain constant. There is a balanced trade-off between stacking and silicon integration where performance, size, cost, and flexibility must all align. Packaging provides the required performance, size, cost, and flexibility alignment between the various pieces of silicon.

The Intel® Folded Stacked Chip Scale Package (Intel® Folded-SCSP) package technology uses a flexible, thin, film-based tape substrate and folds the substrate over the top of the lower die to provide open landpads on the top of the package where various Intel® Flash Memory devices can be attached. This approach allows for the best-of-both-worlds where the total package stack is flexible for the various devices to be placed on top of the processor. This approach also provides benefits for test and assembly by allowing individual package testing and assembly prior to the last package-on-package assembly process step. (See Figure 1-5).

Figure 1-4. Intel® PCA Processor

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Packaging Overview

The Intel® Folded-SCSP package paves the way toward total system-in-a-package integration consisting of all aspects of leading edge package technology and silicon technology combined to provide a key solution for the handheld wireless revolution.

Figure 1-5. Leadership Packaging Technologies

Over 150 Million Shipped!!

Sampling Now / Production late 2003

Intel® Ultra-Thin SCSP

Package-to-Package Stacking

Intel® Stacked CSP

Sampling Now / Production 2003


Chapter 2 Packaging Technology

Packaging Technology 2

2.1 Introduction

This chapter describes various Chip Scale Packages (CSPs) from Intel and the wireless products contained inside of them, including examples of the mechanical dimensions, their applications, and other packaging information.

This chapter is in two parts: The first part is dedicated to discrete and stacked packages for Intel® Flash Memory and RAM technologies. The second part is dedicated to packages for Intel® Personal Internet Client Architecture (Intel® PCA) Cellular Processors.

Note: Please refer to specific product datasheets for actual package dimensions. These mechanical dimensions are examples only and actual size may vary depending on product.

2.2 Product Packages for Flash Memory

You can choose the package for your application based on various package criteria such as package size, cost, ease-of-use, and life cycle/migration.

Generally, ease-of-use and life cycle/migration are important package criteria for the traditional embedded application. Typically, an embedded application design goes through very few subsequent design phases and is intended to have a long application product life. The Easy Ball Grid Array (Easy BGA) was the first BGA package designed specifically for embedded applications using an Intel® Flash Memory device.

With emergence of the handheld wireless industry, the trend for packaging has moved from the traditional embedded package to the much smaller Chip Scale Package (CSP) to take advantage of the small form factor. The Very Thin Profile Fine Pitch BGA (VF-BGA) was introduced in the late '90's as the discrete or monolithic one-die CSP of choice for wireless applications.

As the handheld wireless industry grows and new features are added while the form factor continues to shrink, stacking individual dies into one package has become the new packaging revolution. The Stacked Chip Scale Package (SCSP) has begun to emerge and the trend has shifted from the Discrete CSP to the Stacked CSP (SCSP). This trend continues and is advancing quickly as silicon and packaging technologies merge to provide smaller form factor packaging solutions such as the Intel® Ultra-Thin Stacked Chip Scale Package (Intel® UT-SCSP).

The following sections discuss these packages for flash memory, beginning with the most current as follows:

• Section 2.2.1, “Intel® UT-SCSP for Flash Memory”

• Section 2.2.2, “SCSP for Flash Memory”

• Section 2.2.3, “VF-BGA Package for Flash Memory”

• Section 2.2.4, “Easy BGA Package for Flash Memory”


Packaging Technology

2.2.1 Intel® UT-SCSP for Flash Memory

The Intel® Ultra-Thin Stacked Chip Scale Package (Intel® UT-SCSP) for flash memory is created by taking a SCSP and reducing the size through a series of material set changes. These changes include, for example, thinning or back-grinding the die to 3.0 mil (~75 µm) and reducing the size of the solder balls. The initial Intel® UT-SCSP packages use a BT laminate substrate in a family of products that stack flash and SRAM or PSRAM in x16 bus width products. (See Figure 2-1, “Intel® UT-SCSP BT for Flash Memory (Example)” on page 2-2 and Figure 2-2, “Intel® UT-SCSP BT Substrate Package for Flash Memory (Example)” on page 2-3.)

Future variations of Intel® UT-SCSP for high performance products will stack flash memory and low-power SDRAM in x16 and x32 bus width products.

Figure 2-1. Intel® UT-SCSP BT for Flash Memory (Example)

0.8 mm Ball PitchBT Laminate





Figure 2-2. Intel® UT-SCSP BT Substrate Package for Flash Memory (Example)

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2.2.2 SCSP for Flash Memory

The SCSP for flash memory takes advantage of multiple application requirements, including combining flash, SRAM, and PSRAM into one package as shown in Figure 2-3, “SCSP for Flash Memory (Example)” on page 2-4. This type of packaging provides the maximum space savings advantage by eliminating other individual memory packages from the application and stacking them vertically in a single package. Although the package may have a larger ball pitch compared to the VF-BGA package (0.8 mm vs. 0.75 mm), the overall PCB area of the SCSP is much smaller than the combined area of the separate components.

Also, by stacking vertically, a SCSP package allows higher density in a smaller form factor package. This is accomplished by stacking a low-density die as opposed to using a single large- density die that consumes more silicon area.

While the first SCSP packages from Intel contained only two dies (i.e., one flash die and one SRAM die) and measured 1.4 mm in profile height, recent SCSP technology has improved to reduce two stacked dies to 1.2 mm profile height. The total die count has also increased by adding up to four dies while keeping the profile height to only 1.4 mm.

There is also a trend to include only one flash die in a SCSP package, using the same ballout (electrical interface footprint). A departure from designing in the traditional VF-BGA CSP for discrete flash-only requirements, this new approach provides a single ballout and a migration path to future stacking when the application requires it. A single ballout eliminates the need to redesign the PCB when migrating from a discrete VF-BGA package to a SCSP, and it also allows OEMs a single ballout for multiple product platforms.

Figure 2-3. SCSP for Flash Memory (Example)

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Silicon Die


Silicon Die




Figure 2-4. SCSP Drawing and Dimensions for Flash Memory (Example)

Millimeters InchesDimensions Symbol Min Nom Max Notes Min Nom MaxPackage Height A 1.200 0.0472Ball Height A1 0.200 0.0079Package Body Thickness A2 0.860 0.0339Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167Package Body Length D 9.900 10.000 10.100 0.3898 0.3937 0.3976Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189Pitch e 0.800 0.0315Ball (Lead) Count N 88 88Seating Plane Coplanarity Y 0.100 0.0039Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276

Top View - Ball Down Bottom View - Ball Up

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2.2.3 VF-BGA Package for Flash Memory

The flash memory VF-BGA package is a Very Thin, Fine-pitch Ball Grid Array discrete package. As shown in Figure 2-5, “VF-BGA Package for Flash Memory (Example)” on page 2-6, it has a 0.75 mm ball pitch and a smaller ball size than the Easy BGA package. It is also a low profile package, measuring 1.0 mm maximum package height. It is intended for handheld wireless devices where no additional RAM is included in the package. The package drawing and dimensions are shown in Figure 2-6, “VF-BGA Package Drawing and Dimensions for Flash Memory (Example)” on page 2-7.

Figure 2-5. VF-BGA Package for Flash Memory (Example)

Silicon Die

0.75mm Ball PitchBT Laminate

Silicon Die


Silicon DieSilicon Die




2.2.4 Easy BGA Package for Flash Memory

The Easy BGA package, shown in Figure 2-7, “Easy BGA Package for Flash Memory (Example)” on page 2-8, was designed to be the Intel® Flash Memory package of choice for embedded applications. While offering a larger ball pitch and ball size compared to other CSPs, the Easy BGA package also maintains the benefit of smaller size, measuring about one-half the size of the equivalent TSOP package, with a 1.2 mm profile height.

Figure 2-6. VF-BGA Package Drawing and Dimensions for Flash Memory (Example)

E

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Plane

Top View - Ball Side Down Bottom View - Ball Side Up

YA

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87654321 8 7 6 5 4 3 2 1

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Millimeters InchesDimensions Symbol Min Nom Max Notes Min Nom MaxPackage Height A 1.000 0.0394Ball Height A1 0.150 0.0059Package Body Thickness A2 0.665 0.0262Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167Package Body Length (64Mb, 128Mb) D 7.600 7.700 7.800 0.2992 0.3031 0.3071Package Body Width (64Mb, 128Mb) E 8.900 9.000 9.100 0.3504 0.3543 0.3583Pitch e 0.750 0.0295Ball (Lead) Count N 56 56Seating Plane Coplanarity Y 0.100 0.0039Corner to Ball A1 Distance Along D S1 1.125 1.225 1.325 0.0443 0.0482 0.0522Corner to Ball A1 Distance Along E S2 2.150 2.250 2.350 0.0846 0.0886 0.0925



Another advantage of the Easy BGA package is its constant package size/footprint with respect to memory density upgrades and die shrinks. A key element of embedded applications is the need for long product life cycles, from 5 to 7 years, that require the same package size/footprint. Therefore, the package size/footprint must remain constant over time, while memory densities increase and die sizes shrink. This attribute is very beneficial because many embedded applications increase in memory density over time to incorporate additional functionality. The package drawing and dimensions are shown in Figure 2-8, “Easy BGA Package Drawing and Dimensions for Flash Memory (Example)” on page 2-9.

Figure 2-7. Easy BGA Package for Flash Memory (Example)

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1.0mm Ball PitchLarge Solder

Balls

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Balls



Balls 1.0mm Ball PitchLarge Solder

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Figure 2-8. Easy BGA Package Drawing and Dimensions for Flash Memory (Example)

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Millimeters InchesDimensions Symbol Min Nom Max Notes Min Nom MaxPackage Height A 1.200 0.0472Ball Height A1 0.250 0.0098Package Body Thickness A2 0.780 0.0307Ball (Lead) Width b 0.380 0.430 0.480 0.0149 0.0169 0.0189Package Body Width (64Mb, 128Mb, 256Mb) D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976Package Body Length (64Mb, 128Mb) E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157Package Body Length (256Mb) E 14.900 15.000 15.100 1 0.5866 0.5906 0.5945Pitch [e] 1.000 0.0394Ball (Lead) Count N 64 64Seating Plane Coplanarity Y 0.100 0.0039Corner to Ball A1 Distance Along D (64/128/256Mb) S1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630Corner to Ball A1 Distance Along E (64/128Mb) S2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220Corner to Ball A1 Distance Along E (256Mb) S2 3.900 4.000 4.100 1 0.1535 0.1575 0.1614



2.3 Product Packages for Intel® PCA Cellular Processors

This section discusses the following packages for Intel® Personal Internet Client Architecture (Intel® PCA) Cellular Processors:

• Section 2.3.1, “Intel® Folded-SCSP for Intel® PCA Cellular Processors”

• Section 2.3.2, “SCSP for Intel® PCA Cellular Processors”

• Section 2.3.3, “VF-BGA Package for Intel® PCA Cellular Processors”

• Section 2.3.4, “PBGA Package for Intel® PCA Cellular Processors”

2.3.1 Intel® Folded-SCSP for Intel® PCA Cellular Processors

The Intel® Folded Stacked Chip Scale Package (Intel® Folded-SCSP) delivers solutions for multiple applications by providing the ability to combine different products in a single footprint. The package is developed by placing memory or other bus interconnects on the top surface. Then a separate package is mounted to these bus interconnects. This permits a high degree of flexibility by allowing products to be manufactured with different memory configurations. For the end user, this single folded package provides high performance products while reducing parts count and board space. The Intel® Folded-SCSP technology provides the same density advantages as the SCSP. Examples of the Intel® Folded Stacked Chip Scale Package (Intel® Folded-SCSP) are shown in:

• Figure 2-10, “Intel® Folded-SCSP for Intel® PCA Cellular Processor (8x11 Top Example)” on page 2-11

• Figure 2-11, “Intel® Folded-SCSP for Intel® PCA Cellular Processor (11x13 Top Example)” on page 2-12

Figure 2-9. Intel® Folded-SCSP Package for Intel® PCA Cellular Processors (Example)



Figure 2-10. Intel® Folded-SCSP for Intel® PCA Cellular Processor (8x11 Top Example)

Seating

Plane

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Complete Ink Mark Not Shown

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Pacakge Height A 1.550 0.06102Ball Height A1 0.180 0.280 0.00709 0.01102Package Body Thickness A2 1.121 1.158 1.195 0.04413 0.04559 0.04705

Ball (Lead) Width b 0.350 0.400 0.450 0.01378 0.01575 0.01772Bottom Package Body Width D 13.925 14.000 14.075 0.54823 0.55118 0.55413Bottom Package Body Length E 13.925 14.000 14.075 0.54823 0.55118 0.55413Top Package Body Width F 10.950 11.000 11.050 0.43110 0.43307 0.43504Top Package Body Length G 7.950 8.000 8.050 0.31299 0.31496 0.31693Pitch [e] 0.650 0.02559Ball (Lead) Count N 336 336Seating Plane Coplanarity Y 0.150 0.00591Corner to Ball A1 Distance Along D S1 0.825 0.03248Corner to Ball A1 Distance Along E S2 0.825 0.03248

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Figure 2-11. Intel® Folded-SCSP for Intel® PCA Cellular Processor (11x13 Top Example)

Note: English units are for reference only Controlling dimensions: millimeter

Top View - Bottom Package Ball side down


Bottom View -Bottom Package Ball Side Up

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Pacakge Height A 1.550 0.06102Ball Height A1 0.180 0.280 0.00709 0.01102Package Body Thickness A2 1.121 1.158 1.195 0.04413 0.04705

Ball (Lead) Width b 0.350 0.400 0.450 0.01378 0.01575 0.01772Bottom Package Body Width D 13.925 14.000 14.075 0.54823 0.55118 0.55413Bottom Package Body Length E 13.925 14.000 14.108 0.54823 0.55118 0.55543Top Package Body Width F 12.950 13.000 13.050 0.50984 0.51181 0.51378Top Package Body Length G 10.950 11.000 11.050 0.43110 0.43307 0.43504Pitch [e] 0.650 0.02559Ball (Lead) Count N 336 336Seating Plane Coplanarity Y 0.150 0.00591Corner to Ball A1 Distance Along D S1 0.825 0.03248Corner to Ball A1 Distance Along E S2 0.825 0.03248

Seating

PlaneY

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2.3.2 SCSP for Intel® PCA Cellular Processors

The SCSP takes advantage of multiple application requirements, including combining the processor, SRAM, and PSRAM into one package. This package has a 0.65 mm ball pitch and provides a space savings advantage by eliminating other individual memory packages from the application and stacking them vertically in a single package. Therefore, the overall PCB area of the SCSP is much smaller than the combined area of the separate components. An example of a SCSP package includes Figure 2-13, “SCSP (Typical 0.65 Pitch) Drawing for Intel® PXA26X (Example)” on page 2-14.

Figure 2-12. SCSP for Intel® PCA Cellular Processors (Example)

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Figure 2-13. SCSP (Typical 0.65 Pitch) Drawing for Intel® PXA26X (Example)

SeatingPlane

Top View - Ball side down

Complete Ink Mark Not Shown Bottom View - Ball Side Up

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SABCDEFGHjKLMNPRTUV

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EFGHjKLMNPRTUV

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Pacakge Height A 1.400 0.055Ball Height A1 0.300 0.012Package Body Thickness A2 0.990 0.039Ball (Lead) Width b 0.350 0.400 0.450 0.014 0.016 0.018Package Body Width D 12.900 13.000 13.100 0.508 0.512 0.516Package Body Length E 12.900 13.000 13.100 0.508 0.512 0.516Pitch [e] 0.650 0.026Ball (Lead) Count N 294 294Seating Plane Coplanarity Y 0.120 0.005Corner to Ball A1 Distance Along D S1 0.875 0.975 1.075 0.034 0.038 0.042Corner to Ball A1 Distance Along E S2 0.875 0.975 1.075 0.034 0.038 0.042



2.3.3 VF-BGA Package for Intel® PCA Cellular Processors

The VF-BGA package is a very thin, fine pitch discrete package with a reduced ball pitch and small ball size. It is also a low profile package, intended for handheld wireless devices where no additional RAM is included in the package. Examples of VF-BGA packages for Intel® PCA Cellular Processors include those shown in the following paired figures:

• Figure 2-14, “VF-BGA Package (0.50 Pitch) for Intel® PCA Cellular Processors (Example)” on page 2-15 and Figure 2-15, “VF-BGA Drawing (0.50 Pitch) for Intel® PCA Cellular Processors (Example)” on page 2-16

• Figure 2-16, “VF-BGA Package (0.65 Pitch) for Intel® PCA Cellular Processors (Example)” on page 2-17 and Figure 2-17, “VF-BGA (0.65 Pitch) Drawing for the Intel® PXA800F Processor (Example)” on page 2-18

• Figure 2-18, “VF-BGA Package (0.50 Pitch) for Intel® PCA Cellular Processors (Example)” on page 2-18 and Figure 2-19, “VF-BGA (0.50 Pitch) Drawing for an Intel® X-Scale Processor (Example)” on page 2-19

Figure 2-14. VF-BGA Package (0.50 Pitch) for Intel® PCA Cellular Processors (Example)

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Figure 2-15. VF-BGA Drawing (0.50 Pitch) for Intel® PCA Cellular Processors (Example)

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Symbol Min Nom Max Notes Min Nom Max

Pacakge Height A 1.000 0.039Ball Height A1 0.200 0.008

Package Body Thickness A2 0.710 0.028

Ball (Lead) Width b 0.250 0.300 0.350 0.010 0.012 0.014

Package Body Width D 8.900 9.000 9.100 0.350 0.354 0.358Package Body Length E 8.900 9.000 9.100 0.350 0.354 0.358

Pitch [e] 0.500 0.020

Ball (Lead) Count N 156 156Seating Plane Coplanarity Y 0.120 0.005

Corner to Ball A1 Distance Along D S1 0.650 0.750 0.850 0.026 0.030 0.033

Corner to Ball A1 Distance Along E S2 0.650 0.750 0.850 0.026 0.030 0.033




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Figure 2-17. VF-BGA (0.65 Pitch) Drawing for the Intel® PXA800F Processor (Example)


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Pacakge Height A 1.200 0.047Ball Height A1 0.250 0.010Package Body Thickness A2 0.860 0.034Ball (Lead) Width b 0.350 0.400 0.450 0.014 0.016 0.018Package Body Width D 11.900 12.000 12.100 0.469 0.472 0.476Package Body Length E 11.900 12.000 12.100 0.469 0.472 0.476

Pitch [e] 0.650 0.026Ball (Lead) Count N 241 241Seating Plane Coplanarity Y 0.120 0.005Corner to Ball A1 Distance Along D S1 0.700 0.800 0.900 0.028 0.032 0.035Corner to Ball A1 Distance Along E S2 0.700 0.800 0.900 0.028 0.032 0.035

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Figure 2-19. VF-BGA (0.50 Pitch) Drawing for an Intel® X-Scale Processor (Example)

Table 2-1. VF-BGA Dimensions for an X-Scale Processor (Example)

Millimeters Inches

Description Symbol Min Nom Max Min Nom Max Notes

Package Height A — — 1.000 — 0.039 —

Ball Height A1 0.180 — — 0.007 — — —

Package Body Thickness A2 — 0.710 — 0.028 0.028 —

Ball (Lead) Width b 0.250 0.300 0.350 0.010 0.012 0.012 —

Package Body Width D 12.900 13.000 13.100 0.508 0.512 0.512 —

Package Body Length E 12.900 13.000 13.100 0.508 0.512 0.512

Pitch [e] — 0.500 — — — —

Ball (Lead) Count N — 356 — — 356 356 —

Seating Plane Coplanarity Y — — 0.120 — — — —

Corner to Ball A1 Distance along D S1 0.650 0.750 0.850 0.026 0.030 0.033 —

Corner to Ball A1 Distance along E S2 0.650 0.750 0.850 0.026 0.030 0.033 —

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2.3.4 PBGA Package for Intel® PCA Cellular Processors

The plastic ball grid array (PBGA) package is a popular alternative for high I/O devices in the industry. Its advantages over leadframe packages are many. Having no leads to bend, the PBGA greatly reduces coplanarity problems and minimizes handling issues, especially during rework. Its pin count can be much higher than leadframes (i.e., 800 vs. 208), limited by package body size and ball pitch requirements.

During reflow the solder balls are self-centering (up to 50% off the pad), thus reducing placement problems during surface mount. Normally, because of the larger ball pitch (typically 1.27 mm) of a PBGA over a QFP or PQFP, the overall package and board assembly yields can be better.

From a performance perspective, thermals can be enhanced through center thermal balls and a heat slug embedded in mold cap. Electricals can be improved through package plane layers. The PBGA has an improved design-to-production cycle time because it is well understood by the industry. It can also be used in multi-chip module configurations where dies are side-by-side or stacked.

Figure 2-20. PBGA Package (1.0 Pitch) for Intel® PCA Cellular Processors (Example)

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Figure 2-21. PBGA Drawing for the Intel® PXA255 Processor (Example)

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Pacakge Height A 2.000 0.079Ball Height A1 0.300 0.012Package Body Thickness A2 1.410 0.056Ball (Lead) Width b 0.400 0.500 0.600 0.016 0.020 0.024Package Body Width D 16.900 17.000 17.100 0.665 0.669 0.673Package Body Length E 16.900 17.000 17.100 0.665 0.669 0.673Pitch [e] 1.000 0.039Ball (Lead) Count N 256 256Seating Plane Coplanarity Y 0.150 0.150Corner to Ball A1 Distance Along D S1 0.900 1.000 1.100 0.035 0.039 0.043Corner to Ball A1 Distance Along E S2 0.900 1.000 1.100 0.035 0.039 0.043


Chapter 3 Shipping Media Information

Shipping Media Information 3

3.1 Overview

As the industry evolves, taking advantage of smaller packages with more features, the shipping media is evolving also. Ideally, the preferred type of shipping media is defined by the customer's optimized production process.

One consideration when choosing the shipping media type is the programming method used. A recent trend in programming flash memory is on-board programming (OBP), which programs the package after it has been placed on the PCB. One benefit of OBP is that the package remains in the original shipping media until it is placed on the PCB at assembly, therefore eliminating extra handling processes that typically occur during independent package off-board programming.

Off-board automated programming systems may use only certain types of input/output media. Both on-board and off-board programming processes have benefits. Therefore, it is important to consider the various media required for programming and/or assembly processes.

The primary consideration when choosing the type of shipping media is an understanding of the process requirements so that quality and ease-of-use are optimized. Regardless of the means used for programming, chip scale packages (CSPs) ship in two types of shipping media:

• Tape and reel (T/R)

• JEDEC trays

3.2 Shipping Media

Shipping media is gaining more awareness from a total cost of manufacturing perspective. To prevent misplacements and other processing issues, tray and tape/reel quality becomes essential due to the small size of CSPs. Critical design tooling parameters like tray flatness and media pocket tolerance improve device placement, throughput, and yields. Intel has a rigorous shipping media qualification process and exceeds many industry design standards in order to ship CSPs with a high level of quality and reliability.

3.2.1 Tape and Reel

CSPs shipped in Tape and Reel (T/R) use a polystyrene and carbon anti-static carrier tape and a cover tape. CSPs in T/R have two different quantity offerings:

• 2,000 Piece (Production): Preferred high-volume method for shipping the CSPs from Intel to customers.

• 100 Piece (SDC samples): For Silicon Daisy Chain (SDC) samples used for mechanical and system set-up evaluations.

Refer to Figure 3-2, “Carrier Tape Diagram” on page 3-3 and Figure 3-3, “Carrier Tape Reel Diagram (All Packages)” on page 3-5 for detailed carrier tape information.


Shipping Media Information

3.2.2 JEDEC Trays

CSPs shipped in standard JEDEC trays are generally offered in stack multiples of five full trays. Tray quantities vary depending on the type of package being offered. Refer to Figure 3-4, “Injection Molded Thin JEDEC Tray” on page 3-6 and the specific CSP tables for detailed tray information.

3.2.3 Electrical Samples

CSPs can be ordered for samples in two-piece Tape-in-Tube shipping media. This approach consists of a standard two-piece carrier and cover tape, which is then placed into a tube for added protection as shown in Figure 3-1, “Tape-in-Tube Example” on page 3-2. The customer removes the packages by peeling the cover tape back. Some electrical samples may also be offered in 100 piece Tape and Reel. Consult your local Intel Sales Office or Representative for additional information.

Figure 3-1. Tape-in-Tube Example

CSP-03211



Note: All carrier tape dimensions are in millimeters.

Figure 3-2. Carrier Tape Diagram

Table 3-1. SCSP Carrier Tape Dimensions

Package Size (mm)

Supplier Vendor Part# W (mm)

P1 (mm)

Po(mm)

E1(mm)

R(mm)

Meters /Reel

8 x 10 Advantek INCS07 24 12 4.0 1.75 50 Min 78

8 x 11 Sumicarrier PZ338DN8750 24 12 4.0 1.75 50 Min 105






12 x 12.5 Advantek INCS11 24 16 4.0 1.75 50 Min 105

9 x 11 Sumicarrier PZ260DN8750 24 12 4.0 1.75 50 Min 105

11 x 13 Advantek INCS21 24 16 4.0 1.75 50 min 105



Table 3-2. VF-BGA, Easy BGA, PBGA Carrier Tape Dimensions

Product Supplier Vendor Part# W (mm)

P1 (mm)

Po(mm)

E1(mm)

R(mm)

Meters /Reel

1.8 Volt Intel StrataFlash® Wireless Memory VF-BGA (L18/L30)

GE28F256L18/30 Sumicarrier PZ260DN8750 24 12 4.0 1.75 50 Min 78

GE28F128L18/30 Advantek INCS05 24 12 4.0 1.75 50 Min 105

GE28F640L18/30 Advantek INCS18 24 12 4.0 1.75 50 Min 105

1.8 Volt Intel® Wireless Flash Memory VF-BGA (W18/W30)

GE28F128W18/30 Advantek INCS11 24 16 4.0 1.75 50 Min 105



3.0 Volt Synchronous Intel StrataFlash® Memory VF-BGA (K18/K30)

GE28F256K18/3 Sumicarrier PZ276DN8750 24 12 4.0 1.75 50 Min 105

GE28F128K18/3 Sumicarrier PZ260DN8750 24 12 4.0 1.75 50 Min 78

GE28F640K18/3 Advantek INCS05 24 12 4.0 1.75 50 Min 105

3.0 Volt Intel StrataFlash® Memory VF-BGA (J3)

GE28F640J3 Advantek INCS09 24 12 4.0 1.75 50 Min 78

GE28F320J3 Advantek INCS09 24 12 4.0 1.75 50 Min 78

3.0 Volt Intel® Boot Block Flash Memory VF-BGA (C3/B3)

GE28F640B3/C3 Advantek INCS05 24 12 4.0 1.75 50 Min 105



GE28F800C3GE28F008B3/C3

Advantek INCS14 24 12 4.0 1.75 50 Min 105

Easy BGA Products

Easy BGA 10x13 3M USO48641 24 12 4.0 1.75 50 Min 105

Easy BGA 10x15 Sumicarrier PZ263DN8750 24 12 4.0 1.75 50 Min 105

NOTES:Supplier Contact Information1. Advantek contact info: USA 1-952-938-6800 www.advantek.com2. Sumicarrier contact info: USA 1-408-243-8402, Singapore 65-752-88003. 3M contact info: USA 1-800-666-8273



Note: Dimensions are in millimeters per the following table:

Figure 3-3. Carrier Tape Reel Diagram (All Packages)

Millimeters 16 mm 24 mm

A Max. 330 330

D Min 20.2 20.2

W2 Max. 22.4 30.4



Note: Dimensions are in inches.

Figure 3-4. Injection Molded Thin JEDEC Tray

Table 3-3. SCSP Injection Molded Thin JEDEC Tray Parameters (Sheet 1 of 2)

Package size Supplier Vendor Part# Row Column # of Pockets M M1 M2 M3

10 X 8 RD28F1602 Daewon 12R-0810-213 8 25 200 20 14.7 11.9 13.7

8 x 10 Daewon 12R-0810-119 10 30 300 13.5 11.05 10.1 12.1

8 x 11 Daewon 12R-0811-119 8 22 176 13.70 10.50 14.00 15.50

8 x 12 Daewon 12R-0812-219 8 25 200 14.4 14.7 11.9 15.3

8 x 14 Daewon 12R-1408-E19 8 30 240 11.6 11.05 10.1 16.1

10 x 14 Daewon 12R-1410-E19 10 19 190 13.5 12.6 16.1 12.1

10 x 12 Daewon 12R-1012-219 10 21 210 13.5 16.5 14.1 12.1

12 x 12 Daewon 12C-1212-113 8 20 160 14.75 13.10 15.20 15.20

12 x 12.5 Daewon 12E-1212-F19 8 22 176 18.6 14.7 13.6 14.1

9 x 11 Daewon 12E-1109-F19 10 29 290 11.25 9.1 10.6 12.6

11 x 13 Daewon 12R-1113-219 7 18 184 15.10 13.40 13.10 15.10



13 x 13 Daewon Contact supplier 7 18 126 19.35 19.80 16.20 16.20

Folded SCSP Products

Intel® Folded-SCSP BGA 14 x 14

Daewon IFR-1414-A19 7 18 126 19.35 19.80 16.20 16.20

NOTES:1. Daewon contact info: USA 1-408-213-6200 WWW.Daewonspic.com.2. Dimensions are in millimeters.

Table 3-4. VF-BGA, Easy BGA, PBGA, Injected Molded Thin JEDEC Parameters (Sheet 1 of 2)

Product Supplier P/N Row Column Qty M M1 M2 M3


GE28F256L18/30 Daewon 12E-1109-F19 10 29 290 11.25 9.1 10.6 12.6

GE28F128L18/30 Daewon 12E-7790-C19 12 28 336 15.7 11.7 10.8 9.5

GE28F640L18/30 Daewon 12E-7762-C19 12 38 456 15.7 9.5 8.0 9.5


GE28F128W18/30 Daewon 12E-1212-F13 8 22 176 18.6 14.7 13.6 14.1

GE28F640W18/30 Daewon 12E-7790-C19 12 28 336 15.7 11.7 10.8 9.5

GE28F320W18/30 Daewon 12E-7790-C19 12 28 336 15.7 11.7 10.8 9.5


GE28F256K18/3 Daewon 12E-1409-F19 7 28 196 19.65 14.4 10.6 16.1

GE28F128K18/3 Daewon 12E-1109-F19 10 29 290 11.25 9.1 10.6 12.6

GE28F640K18/3 Daewon 12E-7790-C19 12 28 336 15.7 11.7 10.8 9.5


GE28F640J3 Daewon 12E-0710-C19 12 25 300 15.7 8.7 12.4 9.5

GE28F320J3 Daewon 12E-0710-C19 12 25 300 15.7 8.7 12.4 9.5

3.0 Volt Intel® Boot Block Flash Memory VF-BGA (C3/B3)

GE28F640B3/C3 Daewon 12E-7790-C19 12 28 336 15.7 11.7 10.8 9.5

GE28F320B3/C3 Daewon 12E-0607-C13 10 25 250 18.9 8.7 12.4 10.9

GE28F160B3/C3 Daewon 12E-0607-C13 10 25 250 18.9 8.7 12.4 10.9

GE28F800C3GE28F008B3/C3

3M 21002-373-129 9 20 180 12.31 11.58 15.36 13.91

VF-BGA (Other Products)

9 x 9 Daewon 12C-0909-E19 10 25 250 13.95 13.50 12 12

13 x 13 Daewon Contact supplier 7 18 126 19.35 19.80 16.20 16.20

Easy BGA/PBGA Products

Easy BGA 10x13 Daewon 12B-1013-G13 8 18 144 19.3 14.7 16.8 13.9

Table 3-3. SCSP Injection Molded Thin JEDEC Tray Parameters (Sheet 2 of 2)



Easy BGA 10x15 Daewon 1F6-1015-B19 10 17 170 13.5 20.7 17.1 12.1

PBGA 17x17 Daewon Contact supplier 6 15 90 19.20 21.00 19.50 19.50

NOTES:1. Daewon contact info: USA 1-408-213-6200 WWW.Daewonspic.com.2. 3M contact info: USA 1-800-666-8273.3. Dimensions are in millimeters.

Table 3-5. Discrete VF-BGA / Easy BGA Package Sizes (mm)

Product Name Package size (mm)


GE28F256L18/30 9x11x1.0

GE28F128L18/30 7.7x9.0x1.0

GE28F640L18/30 7.7x6.2x1.0


GE28F128W18/30 12x12.5x1.0

GE28F640W18/30 7.7x9.0x1.0

GE28F320W18/30 7.7x9.0x1.0


GE28F256K18/3 14.5x9x1.0

GE28F128K18/3 9x11x1.0

GE28F640K18/3 7.7x9.0x1.0


GE28F640J3 7.29x10.85x1.0

GE28F320J3 7.29x10.85x1.0

3.0 Volt Intel® Boot Block Flash Memory (C3/B3)

GE28F640B3/C3 7.7x9.0x1.0

GE28F320B3/C3 7.29x6.96x1.0

GE28F160B3/C3 7.29x6.96x1.0

GE28F800C3GE28F008B3/C3

7.91x6.5x1.0

All Easy BGA Packages

Easy BGA Products 10x13

Easy BGA Products 10x15

Table 3-4. VF-BGA, Easy BGA, PBGA, Injected Molded Thin JEDEC Parameters (Sheet 2 of 2)



3.2.4 CSP Shipping Media Orientation

CSP shipping media orientations are displayed in Figure 3-5, “CSP Package Shipping Media Orientation” on page 3-9. Note that the package/shipping media orientation is referenced by the package pin 1 mark. For Tape/Reel, pin 1 can be on either corner of the side facing towards the carrier tape sprocket holes. For JEDEC trays, pin 1 can be on either corner of the side facing towards the tray's chamfered short side. Note that for a given product all devices will have the same pin 1 orientation for the specified shipping media.

3.3 Shipping Media and Socket Ordering Information

Note: Please refer to the Web-Based Mechanical and Shipping Media Specifications for the most up-to-date information at: http://www.intel.com/design/flash/packtech/

Additional programming socket information can be found in the Electronic Tools Catalog (ETC) under the sockets tool type at: http://developer.intel.com/design/flash/swtools/

Figure 3-5. CSP Package Shipping Media Orientation

JEDEC Tray

CSP-03213

Tape and Reel

JEDEC Tray

CSP-03213

Tape and Reel


http://developer.intel.com/design/flash/swtools

http://developer.intel.com/design/flash/swtools


3.3.1 Ordering Information

Shipping media and off-board programming sockets can be purchased directly from the manufacturers. These materials have been designed and qualified by Intel to ensure the optimal quality and reliability and are the same materials used internally for testing and shipping media.

Many CSP socket bases have been designed to accommodate multiple package sizes by replacing removable inserts. This programming socket design approach provides low-cost flexibility for density upgrades and/or multiple package utilization. Refer to the Electronic Tools Catalog Web site at the above URL for additional ordering information.

The following tables list the various materials, manufacturer's part numbers, and U.S. contact information. If outside of U.S., please consult the manufacturer's nearest sales office.

Note: The hardware vendor remains solely responsible for the design, sale, and functionality of its product, including any liability arising from product infringement or product warranty.

3.4 CSP Device Markings and Shipping Labels

3.4.1 Device Markings

CSP packages are laser marked. The typical device mark is shown in Figure 3-6, “Typical Device Mark” on page 3-10. Explanations of markings are as follow:

• Line 1: Represents Marketing name or Product Name.

• Line 2: Represents finish process order information.

• Line 3: Represents Assembly Lot information.

3.4.2 Shipping Labels

All CSP packages are packed into T/R and trays, then sealed in moisture barrier bags (MBB) with a desiccant card and desiccant bags, and finally placed in a cardboard box. Labels are placed on the individual MBB and the cardboard box which list product name, moisture level, lot number, and other pertinent information, as shown in Figure 3-7, “Moisture Barrier Bag (MBB)” on page 3-11.

Figure 3-6. Typical Device Mark

Line 1Line 2Line 3

M C ‘96

CSP-03212



For shipments in T/R and samples shipped in tape-in-tube, additional labels are attached to the individual plastic reels and tubes which provide the same information as the box and MBB bag labels. These are provided for added lot traceability during the OEM manufacturing process.

3.5 Handling and Floor Life

3.5.1 Handling

Although bent lead issues have been eliminated because of the nature of BGA packages, when manually or automatically handling CSPs during the manufacturing process, appropriate care and precautions are essential as with any semiconductor package.

Standard manufacturing processes that use automated pick-and-place systems for component transfer, such as off-board programming and placement systems, do not present any additional risks or concerns for CSPs. As with any package, equipment set-up should be verified for excessive pick/place over-travel.

Figure 3-7. Moisture Barrier Bag (MBB)

(1P) IPN: G28F800B3T120

(S) SPEC: STD

(IT) LOT:

(IT) LOT: T1234567

(Q) QTY:

(Q) QTY: 2000

(9D) DATE:

(9D) DATE: 9732

AS

SE

MB

LED

IN P

HIL

IPP

INE

S

(9D) DATE:

BAG SEAL DATE 08AUG03

LEVEL 2 HOURS 1 YR

(P) CUST PROD:

(V) SUPPLIER: 04195 (1B) BOX ID: RW001104

(M): (C): OF

CSP-03214



However, manual handling practices vary widely among the many manufacturing processes, leading to additional risks of process excursions. Therefore, the majority of handling precautions concern the manual handling process.

3.5.1.1 Manual Handling

When handling CSPs in JEDEC trays, always ensure a cover tray is attached. Avoid abrupt tray movement when removing the cover tray to eliminate the possibility of packages popping out of the tray pockets.

When manually handling CSPs, use of ESD-safe vacuum wands are preferred. However, a pair of non-metallic tweezers is also acceptable. The preferred type of vacuum wand is an AC or battery powered wand that increases vacuum integrity and reduces the risk of dropping the package due to a bad vacuum seal or lack of vacuum. When using non-metallic tweezers, contact only the sides of the package to simplify placement and prevent contact with the eutectic solder balls.

The preferred method of handling PCBs is by the PCB’s edge to minimize any direct component contact. If the PCB must be reworked, use a standard rework station that is equipped with an automatic vacuum nozzle pickup and profiled to lift the component during the liquid state of the solder paste/balls. If the rework station does not have this capability, always use a vacuum wand for component pickup. Avoid using objects such as screwdrivers or other similar instruments to pry the devices off the PCB during the reflow/rework process.

3.5.1.2 PCB Design Considerations

When designing a PCB, avoid designs which require excessive contact to the component as a normal product handling practice, such as installing a connector on the reverse side of the PCB where the CSP is located. This usage model would require the user to depress directly on the CSP package in order to insert the connector.

3.5.2 Floor Life

Although Intel does not specify a maximum length of time for storage shelf life for CSPs, the current floor life varies depending on the type of CSP based on the IPC moisture sensitivity rating as per IPC/JEDEC standard J-STD-020B. However, each package is qualified independently and may vary, and the manufacturing process is constantly being improved so IPC levels are subject to change, therefore, always refer to the MBB label for the exact IPC moisture level as described earlier in this chapter.


Chapter 4 Thermal Specification Methodology

Thermal Specification Methodology 4

4.1 Introduction

In a system environment, the temperature of a component is a function of both system and component thermal characteristics. The component's junction temperature depends on the following factors:

• Component thermal power dissipation

• Component size

• Component packaging materials

• Type of interconnection

• PCB material and size

• Presence of thermal cooling solution

• Power density of PCB

• Power dissipation in neighboring components

In the wireless segment, it has not been typical for memory and logic components to require special thermal management. However, this is no longer the case because multiple components are now stacked inside a single package, the components produce higher sustainable power, and there is an increased need for reliability.

4.2 Objective of Thermal Management

The objective of thermal management is to ensure that the temperature of all components in a system is maintained to equal to or less than the maximum allowable functional limit. The functional temperature limit is a range within which the electrical circuits can be expected to meet specified performance requirements. Operation outside these limits can degrade performance and cause logic errors or component damage, including irreversible changes in the operating characteristics of a component. Therefore, to meet performance and reliability requirements, detailed thermal management must exist at the component and system level to ensure the temperature of all components is maintained within the specified range.

4.3 Thermal Specifications

To ensure proper operation and reliability of an Intel® Wireless Communications and Computing device, the thermal envelope of the component must be such that during normal operation, the junction temperature remains at or below the temperature at which the device has been tested and guaranteed. Since the device is used in a system, it is impossible to measure the junction temperature of a live component; therefore, Intel quantifies the case temperature based on junction temperature. If the case temperature of a component in a system exceeds the specified limit, there is need for increased emphasis on system design to ensure that thermal specification requirements are met.


Thermal Specification Methodology

4.4 Maximum Case Temperature

The case temperature for each product is a function of the local ambient temperature and the junction temperature of the component. The case temperature can be represented by the equation shown in Figure 4-1, “Case Temperature Equation” on page 4-2.

4.5 Case Temperature Measurements

Case temperature is measured at the geometric center of the mold cap. Special care is required when measuring the Tcase temperature to ensure an accurate temperature measurement.

Thermocouples are often used to measure Tcase. Before any temperature measurements are made, the thermocouples must be calibrated.

When measuring the temperature of a surface, which is a different temperature from the surrounding local ambient air, errors could be introduced in the measurements. The measurement errors could be due to:

• Poor thermal contact between the thermocouple junction and the surface of the package

• Heat loss by radiation, convection, or by conduction through thermocouple leads

• Contact between the thermocouple cement and the heat-sink base for those solutions which implement a heat-sink

To minimize these measurement errors, the following approach is recommended for attaching the thermocouple:

• Use a 36 gauge or smaller diameter K-type thermocouple.

• Ensure that the thermocouple has been properly calibrated.

• Attach the thermocouple bead or junction to the top surface of the package (case) in the center of the mold-cap using high thermal conductivity cements.

Figure 4-1. Case Temperature Equation

ψjt

* P max

T c, max = T j, max

WhereT c, max = Maximum allowable case temperature (oC).

T j, max = Maximum allowable junction temperature (oC).

P max = Maximum sustainable device power (W).

ψjt = Thermal parameter characterization junction to top center of package

CSP-03200

( oC/W).



An alternative for tape attach users is to use the tape itself to mount the thermocouple. It is critical that the thermocouple lead be butted tightly against the entire moldcap.

• If there is no interference with the thermocouple attach location or leads, the thermocouple should be attached at a 0° angle, as shown in Figure 4-2, “Technique for Measuring Tcase with Zero Degree Angle Attachment” on page 4-3).

This is the preferred method and is recommended for use with both packages that employ thermal enhancements and those that do not.

• If the thermocouple cannot be attached as previously shown, the thermocouple may be attached at a 90° angle, as shown in Figure 4-3, “Technique for Measuring Tcase with Ninety Degree Angle Attachment” on page 4-3.

• The hole size through the heat sink base to route the thermocouple wires out should be smaller than 0.150 inches in diameter.

• Make sure there is no contact between the thermocouple cement and heat sink base. This contact will affect the thermocouple reading.

Figure 4-2. Technique for Measuring Tcase with Zero Degree Angle Attachment

CSP-03201

Figure 4-3. Technique for Measuring Tcase with Ninety Degree Angle Attachment

CSP-03202


Chapter 5 Manufacturing Considerations

Manufacturing Considerations 5

This chapter includes considerations for manufacturing, including the following major sections:

• “SMT Process”

• “PCB Design Guidelines”

• “Package to Board Assembly Process”

• “Programming Considerations”

5.1 SMT Process

Many factors contribute to a high yielding assembly process. A few of the key focus areas and their contributing factors are highlighted in Table 5-1.

Chip Scale Packages (CSPs) provide manufacturing benefits that contribute to higher assembly yields, including the benefits of self-alignment characteristics and the elimination of coplanarity issues caused by bend leads. As the industry moves to CSPs because of these benefits, focus shifts to additional ways to optimize yields and overall quality.

This section reviews PCB design guidelines that help improve the manufacturing process. However, it is also important to understand how PCB design guidelines help improve CSP quality and solder joint reliability (SJR) to extend an application’s life and use in the field. Chapter 7, “Quality and Reliability Engineering” reviews how Intel certifies its packages and how the qualification process is evolving to meet the application's requirements.

The following PCB design and manufacturing guidelines provide the best known methods for CSP manufacturing while maintaining the demands of long-term application quality and reliability.

5.2 PCB Design Guidelines

Among the many factors to consider when designing the PCB for CSPs, one key factor is the type of CSP selected for the application. This selection is often based on the specific application's packaging values. Just as PCB technology is improving, so too is packaging technology, and the key to success for customers is providing a packaging solution that is compatible with today's technology. In

Table 5-1. Essentials for Assembly Quality

Solder Paste QualityUniform viscosity and texture. Free from foreign material. Solder paste should be used before the expiration date. Shipment and storage temperatures are maintained at the proper temperature. Paste is protected from drying out on the solder stencil.

PCB Quality Clean, flat, plated, or coated solder ball land area. Attachment surface must be clean and free of solder mask residue.

Placement AccuracyTight tolerances are not usually required. CSP packages can self-center themselves as long as a major portion (more than 50 percent) of the solder ball is in contact with the solder paste covered land area on the board. Alignment marks (fiducials) on the PCB are helpful for verifying correct placement of parts.

Solder Reflow Profile

The solder reflow profile will be dependent on PCB design, PCB thickness, type of components, component density, and the recommended profile of the solder paste being used. A reflow profile will need to be developed for each PCB type using various CSP packages. (See Table 5-6, “Solder Reflow Profile Targets” on page 5-11.)


Manufacturing Considerations

addition, Intel customers want new packages to be cost-effective and easily integrated into current PCB and manufacturing infrastructure. The Easy BGA package is the best choice for embedded applications and lowest cost, conventional PCB technology.

The Stacked Chip Scale Package (SCSP) and VF-BGA packages are the best choice for space-constrained applications. They use an average 6-mil spaces/traces, and a range of 0.018-inch to 0.020-inch via pads. This is fairly standard PCB technology in handheld applications and a major driving factor in choosing 0.75-mm and 0.8-mm ball pitch.

5.2.1 PCB Escape Routing

One key element in implementing CSP packages on a PCB, is the escape routing design. Basically, designing the escape routing means determining how to route the signals from underneath the package to other components on the PCB. There are many ways to do escape routing, and this is important since it can define signal trace and space widths, via sizes and number of layers that are used on the PCB. All these are factors in determining the PCB cost. Figure 5-1 shows an example of an escape routing diagram.

Many escape routing files are located on Intel's Electronic Tools Catalog (ETC) and are downloadable Gerber files. Please refer to the ETC by going to the “Flash Memory Tools” link at Intel's Web page:

http://developer.intel.com/design/flash/

5.2.2 PCB Keep-out zones

Another key PCB design element is the keep-out zone area. This is the distance on each side of the CSP component to the nearest adjacent component on the board. This keep-out zone varies depending on the application, and is generally much tighter in handheld applications that require many components in a very small PCB area. While system designers will often design keep-out zones anywhere from 0.100 to 0.050 inches for embedded applications, many handheld applications are trending toward 0.025 inches and smaller. The key factor to consider is how the component will be reworked if it needs to be replaced. Some Original Equipment Manufacturers (OEMs) require rework using a hot air nozzle that isolates the rework area to the specific component being reworked. Special consideration is required to allow adequate area for the hot air

Figure 5-1. Escape Routing Diagram

0.30 mmLand Pads

0.75 mmContact Pitch

0.127 mmTrace Width



nozzle to surround the CSP being reworked. Some rework manufacturers have designed custom rework nozzles that can maintain very tight keep-out zones (See Electronic Tools Catalog [ETC] on Web).

5.2.3 Land Pad Styles

The two basic designs for PCB land pads for CSP packages are Metal Defined design and Solder Mask Defined design. (Refer to Section 5.2.4, “PCB Line Widths and Spaces” on page 5-3 for design guidelines.)

The post-reflow solder profile can be slightly different between these two types of land pads, including differences in the shape of the solder joint after reflow:

• Metal Defined: This land pad design, that is free of mask materials, promotes a uniform tapered slope or column profile of the solder ball as shown in Figure 5-2.

• Solder Mask Defined: This design promotes a controlled collapse of the ball profile as shown in Figure 5-2.

The preferred land pad design is the Metal Defined since it allows maximum flexibility for the PCB design, and the solder mask introduces fewer stress points to the solder joint.

5.2.4 PCB Line Widths and Spaces

PCB line widths and spaces vary depending on the pitch of the CSP. Generally, conventional PCB technology allows for 5-mil or greater line width and spacing, depending on the routing scheme for CSPs, with ball pitches down to 0.75 mm. For the various PCB design guidelines for lines and spaces for all CSPs, refer to the following:

• Figure 5-3, “Single Track Routing PCB Design Guidelines: 0.65 mm to 1.0 mm Packages” on page 5-4 and Table 5-2, “Dimensions: 0.65 mm to 1.0 mm Packages” on page 5-4

• Figure 5-4, “Single Track Routing PCB Design Guidelines: 0.5 mm Packages” on page 5-5 and Table 5-3, “Dimensions for 0.5 mm Packages” on page 5-5

Figure 5-2. Land Pad Style Profiles

PCB

Package

Copper Defined Land Pad

Package

PCB

Solder Mask Defined Land Pad

PCB

Package


PCB

Package

PCB

Package


Package

PCB


Package

PCB

Package

PCB




Note: Stack-ups are for reference only. Specific PCB routing and layer count is dependent upon multiple factors, including package design, dimensions, and pitch.

Figure 5-3. Single Track Routing PCB Design Guidelines: 0.65 mm to 1.0 mm Packages

Table 5-2. Dimensions: 0.65 mm to 1.0 mm Packages

Feature

Dimensions for Various Package Pitches in mm (inches)

0.65 mm SCSP

TF-BGAIntel® Folded-

SCSP BGA

0.75 mm VF-BGA

0.8 mm SCSP

Intel® UT-SCSP

1.0 mm Easy BGA

PBGA

A: Land Pad0.305

(0.012)

0.356

(0.014)

0.356

(0.014)

0.406

(0.016)

B: Solder Mask Opening0.427

(0.0168)

0.478

(0.0188)

0.490

(0.0193)

0.610

(0.024)

C: Metal to Mask Clearance (min) Not recommended to allow solder mask on the land pad.0.0254

(0.001)

D: Typical Trace Width0.102

(0.004)

0.127

(0.005)

0.140

(0.0055)

0.178

(0.007)

E: Typical Space 0.122

(0.0048)

0.127

(0.005)

0.152

(0.006)

0.203

(0.008)

F: Typical Via Pad0.356

(0.014)

0.457

(0.018)

0.508

(0.020)

0.610

(0.024)

G: Typical Via Mechanical Drill Diameter N/A0.254

(0.010)

0.254

(0.010)

0.356

(0.014)

H: Typical Micro Via Diameter0.152

(0.006)NA NA NA

A. Land Pad

B. Solder Mask Opening

C. Metal to Mask Clearance (min)

D. Typical Trace Width

E. Typical Space

F. Typical Via Pad

G. Typical Via Mechanical Drill Diameter

H. Typical Micro Via Diameter Top View

0.65 mm Routing

Interstitial Micro via

1

3

5

7

2

4

6

8

Layers

0.75 mm –1.00 mm Routing

Interstitial via

1

3

5

7

2

4

6

8

LayersA. Land Pad

B. Solder Mask Opening

C. Metal to Mask Clearance (min)

D. Typical Trace Width

E. Typical Space

F. Typical Via Pad

G. Typical Via Mechanical Drill Diameter

H. Typical Micro Via Diameter Top View

0.65 mm Routing

Interstitial Micro via

1

3

5

7

2

4

6

8

Layers

1

3

5

7

2

4

6

8

Layers

1

3

5

7

2

4

6

8

Layers


Interstitial via

1

3

5

7

2

4

6

8

Layers


Interstitial via

1

3

5

7

2

4

6

8

Layers

1

3

5

7

2

4

6

8

Layers



Note: Stack-ups are for reference only. Specific PCB routing and layer count is dependent upon multiple factors, including package design, dimensions, and pitch.

As CSP ball pitches become smaller to take full advantage of package size reductions, PCB costs increase due to the tighter design requirements (See Chapter 1, “Packaging Overview”). For 0.5-mm pitch CSPs, the design requirements for PCB line widths and spaces become more demanding. Your specific finished PCB tolerances may vary depending on application requirements and the abilities of your PCB manufacturing process.

5.2.5 Vias and Land Pads

When using a multi-layer PCB, one method of routing signals from the CSP package is to use one or more vias to drop the signal to another layer of the PCB, and then route the trace. Conventional PCB technology uses mechanical drills to accomplish this during the PCB manufacturing process. Vias that are dropped to other PCB layers within the ball grid array pattern are referred to as interstitial vias.

Generally, using conventional trace widths of 0.005 inches, any fully populated ball grid array pattern greater than 6 x 8 will require interstitial vias. Many CSPs have been designed with depopulated balls within the array to allow for single layer escape routing.

Figure 5-4. Single Track Routing PCB Design Guidelines: 0.5 mm Packages

Table 5-3. Dimensions for 0.5 mm Packages

Feature Dimensions for 0.5 mm Pitch Package in mm (inches)

A. Land Pad 0.254 (0.010)

B. Solder Mask Opening 0.343 (0.0135)

C. Typical Space 0.089 (0.0035)

D. Reduced Trace Width 0.069 (0.0027)

E. Metal to Mask Clearance (min) Not recommended to allow solder mask on the land pad.

F. Typical Trace Width 0.102 (0.004)

G. Typical Via Pad 0.279 (0.011)

H. Typical Micro Via (Via in Pad) Diameter 0.102 (0.004)

Land Pad

Solder Mask Opening

Typical Space

Reduced Trace Width between Lands

Metal to Mask Clearance (min)

Typical Trace Width

Trace on Layer 2

Typical Via Pad

Typical Micro Via DiameterTop View

0.5 mm Routing

Micro via in pad

1

3

5

7

2

4

6

8

Layers

0.5 mm Routing

Micro via in pad

1

3

5

7

2

4

6

8

Layers

1

3

5

7

2

4

6

8

Layers



Various drill sizes can be used to create the vias depending on the CSP ball pitch. This is a significant factor when choosing the best CSP package for your application because the size requirement of the vias is one of the biggest factors contributing to the manufacturing cost of the PCB. For the various PCB design guidelines for lines and spaces for all CSPs, refer to the following:

• Figure 5-3, “Single Track Routing PCB Design Guidelines: 0.65 mm to 1.0 mm Packages” on page 5-4 and Table 5-2, “Dimensions: 0.65 mm to 1.0 mm Packages” on page 5-4

• Figure 5-4, “Single Track Routing PCB Design Guidelines: 0.5 mm Packages” on page 5-5 and Table 5-3, “Dimensions for 0.5 mm Packages” on page 5-5

While much of the industry has moved to conventional drill sizes of 0.014 inches and 0.010 inches, many PCB manufacturers still use drill sizes as large as 0.018 inches. While the Easy BGA package can use a drill bit up to 0.018 inches for vias, the 0.75-mm and 0.8-mm pitch packages generally use 0.010 inches drilled vias. As the ball pitch of the package gets smaller, the cost of PCB manufacturing increases and eventually new types of PCB manufacturing, such as microvia and High Density Interconnect (HDI) will be required. As an example, CSPs with a ball pitch of 0.5 mm generally require this type of PCB technology for interstitial vias.

5.2.6 Surface Finishes

A variety of surface finishes are commonly available. The key factor in selecting an acceptable surface finish is to ensure that the land pads have a uniform, or coplanar, coating. Irregular surface plating, uneven solder paste thickness, and crowning of the solder plating can reduce overall surface mount yields due to solder shorts. Bare Copper with an Organic Solderability Preservative (OSP) coating, or with an electroless nickel/immersion gold finish, or with an electroplated nickel/ gold finish are all known to provide an acceptable land pad surface. If an electroplated nickel or gold finish is chosen, the gold thickness must be less than 5 micro inches to prevent the finished solder joint becoming brittle.

5.2.7 HDI PCB Technologies

Many new and advanced PCB technologies are quickly emerging. The most promising technologies tend to fall into a category called micro-via or High Density Interconnect (HDI), where very small vias can be used to selectively drop the signal to another layer of the PCB, and then route the signals to the other components on the PCB.

HDI has been defined as using blind vias measuring less than 0.006 inches (0.15 mm) in diameter on a 0.014-inch (0.35-mm) or smaller diameter pad. Some of the micro-via technologies being explored are laser drilled, photo-defined, and plasma-etched vias. Some studies have been done that categorize the various PCB technologies. (See Table 5-4, “Typical Design Rules for PCBs” on page 5-6).

Table 5-4. Typical Design Rules for PCBs (Sheet 1 of 2)

Feature (inches) Conventional Advanced Leading Edge State of the Art

Contact Pad Diameter 0.012 0.012 0.006 0.0055

Trace Width 0.005 0.004 0.003 0.002

Space Width 0.005 0.004 0.003 0.002

Mechanical Drill Via Diameter 0.016 0.014 0.010 0.008



Generally, handheld applications use thinner PCBs than do embedded applications. However, as the CSP pitch decreases, via diameter decreases accordingly. This presents new design considerations when the PCB requires less than 0.010-inch vias. The current PCB technology for mechanical drilling reaches a cost and capability cliff for vias requiring less than 0.010-inch holes.

Newer PCB substrate technologies either use HDI or build-up multi-layer boards with microvia to achieve these tighter pitch parameters. The last two categories in Table 5-2, “Dimensions: 0.65 mm to 1.0 mm Packages” on page 5-4 are specific to high-density interconnect PCBs and are the basis of HDI technology.

In many cases, any additional costs associated with advanced technologies are offset by a reduction in metal layers and PCB size.

Smaller pitch packages are beneficial to customers who require the most advanced space saving or weight saving devices. Some of Intel's products are offered in 0.5-mm pitch packages.

5.2.8 Multi-Site Layout Files

Multi-site layouts (also referred to as flex-layouts) are available from Intel for a variety of flash memory components. A sample is shown in Figure 5-5, “Sample Multi-Site Layout Diagram” on page 5-8. Multi-site layouts are PCB land pad designs that allow the user the flexibility to use either a Small Outline Package (TSOP/SSOP) or a CSP package on the same PCB land pad layout. These can be useful for OEMs that plan to phase-in the CSP package to their production line. Multi-site layouts can also make troubleshooting on prototype PCBs easier by allowing test point access to the array. However, there are other tools that provide prototype test point access for CSP. For additional information, refer to the "CSP Signal Access Tools" located in the Test Accessories category in the Electronic Tools Catalog (ETC) under the “Flash Memory Tools” link at the Intel Web page. Multi-site layout files are also available at this link:


Drill Capture Pad 0.026 0.020 0.018 0.014

Microvia Diameter N/A 0.006 0.004 0.0035

Microvia Capture Pad N/A 0.012 0.010 0.008

Availability Most ~65% ~35% ~5%

Table 5-4. Typical Design Rules for PCBs (Sheet 2 of 2)



5.3 Package to Board Assembly Process

5.3.1 Solder Paste

The quality of the paste print is an important factor in producing high-yield assemblies. The paste is the vehicle providing the flux and solder alloy necessary for a reliable and repeatable assembly process. The paste materials tend to dry out when not properly handled and environmentally controlled. A low residue, no-clean solder paste with Sn63/Pb37 is used commonly in mounting CSPs. However, water soluble flux materials are used often too.

Typically the choice of solder paste determines the profile and reflow parameters. Most paste manufacturers provide a suggested thermal profile for their products, and these should be referenced prior to manufacturing. Paste vendors are marketing special BGA-specific solder pastes that exhibit minimized voiding in the solder joint. Intel has experienced excellent surface mount results using low residue, no-clean solder paste.

For lead-free application, Intel selected an Sn/Ag/Cu solder alloy combination. Using lead-free paste should not require any significant changes in the printing process; however, some parameter optimization may be required.

Figure 5-5. Sample Multi-Site Layout Diagram



5.3.2 Solder Stencils

The stencil thickness as well as the etched pattern geometry determine the precise volume of solder paste deposited onto the device land pattern. Stencil alignment accuracy and consistent solder volume transfer are critical for uniform reflow-solder processing. Stencils are made usually of brass or stainless steel, with stainless steel being more durable. A stencil with either a round aperture or a square hole with 5° tapered openings is recommended for CSP applications. In addition, the aperture should be trapezoidal to ensure uniform release of the solder paste and to reduce smearing. Refer to Figure 5-6, “Solder Stencil Design Guidelines” on page 5-9 and Table 5-5, “Dimensions for Solder Stencil Design” on page 5-9.

Thickness of the stencils is usually in the 0.10-mm to 0.15-mm (0.004 inches to 0.006 inches) range. The actual thickness of the stencil is also dependent on other surface mount devices on the PCB. A metal or rubber squeegee durometer of 95 or harder should be used. The blade angle and speed must be fine-tuned to ensure even paste transfer. An inspection of the stenciled board is recommended before placing parts because proper stencil application is the most important factor with regards to reflow yields further on in the process.

5.3.3 Placement and Alignment

The pick-and-place accuracy governs the package placement and rotational (theta) alignment. This is equipment/process dependent. Slightly misaligned parts (less than 50 percent off the pad center) will automatically self-align during reflow as shown in Figure 5-7, “Package Self-Alignment at Solder Reflow” on page 5-10.

Figure 5-6. Solder Stencil Design Guidelines

Table 5-5. Dimensions for Solder Stencil Design

Feature 0.5 mm 0.65 mm 0.75 mm 0.8 mm 1.0 mm

A: Top of Stencil Aperture 0.279 (.011) 0.33 (0.013) 0.33 (0.013) 0.33 (0.013) 0.33 (0.013)

B: Bottom of Stencil Aperture 0.30 (0.012) 0.356 (0.014) 0.356 (0.014) 0.356 (0.014) 0.356 (0.014)

C: Stencil Thickness 0.102 (0.004) 0.127 (0.005) 0.127 (0.005) 0.127 (0.005) 0.127 (0.005)

Round apertures Square apertures

Top View

Stencil AB

PCB

Side View

Stencil apertures should be tapered to produce more uniform release of solder paste.

C

Top View

Round apertures Square apertures

Top View

Stencil AB

PCB

Side View


C

Top ViewTop View

Stencil AB

PCB

Side View


CStencil AB

PCB

Side View


C

Top View



Grossly misaligned packages (greater than 50 percent off pad center) should be removed prior to reflow because they may develop electrical shorts as a result of solder bridges if they are subjected to reflow.

There are two popular methods for package alignment using machine vision:

• Package silhouette: the vision system locates the package outline

• BGA ball recognition: the vision system uses the solder ball array pattern to locate the part

Both methods are acceptable for CSP placement. The ball recognition type alignment tends to be more accurate, but is also slower since more complex vision processing is required of the pick-and-place machine. The package silhouette method allows the pick-and-place system to run faster, but is generally less accurate. Both methods have been successfully demonstrated by major pick-and-place equipment vendors and contract assembly houses.

Lead-free solder balls will have a slightly different appearance than standard Sn/Pb solder spheres. Minor change to vision system may be required from leaded solder balls to lead-free solder balls.

5.3.4 Solder Reflow

In the reflow process, the solder paste must be heated above its melting point and be completely molten to fuse with the molten CSP ball and cause it to collapse and form the desired joint. This solder joint formation mechanism depends on temperature and time which are reflected in the reflow profile.

There are no special requirements necessary when reflowing CSP components. As with all SMT components, it is important that profiles be checked on all new board designs. In addition, if there are multiple packages on the board, the profile should be checked at the different locations on the board. Component temperatures may vary because of surrounding components, location of the part on the board, and package densities. The solder paste type must be considered in reflow profile development. Usually, the recommendation is to follow the paste manufacturer's recommendations. To maximize the self-alignment effect of CSPs, as shown in Figure 5-7, “Package Self-Alignment at Solder Reflow” on page 5-10, the recommendation is not to exceed the maximum reflow temperature specified for the solder paste.

Figure 5-7. Package Self-Alignment at Solder Reflow

Before Reflow

During Reflow

After Reflow



Production and rework profiles for all Intel CSPs are the same as non-BGA Intel SMT devices. The reflow profile guidelines are based on the temperature at the actual solder ball to PCB land pad solder joint location. Table 5-6, “Solder Reflow Profile Targets” on page 5-11 lists solder joint targets to ensure good reflow process.

The actual temperature at the solder joint is different than the temperature settings in the reflow/rework system due to the system efficiency and location of the system thermocouple/RTD used to monitor the temperature. Specific production reflow and rework systems vary depending on manufacturer and model number. Therefore, system-specific profiles should be established using thermocouples at the actual solder joint locations and characterized by using the reflow guidelines shown in Figure 5-8, “Reflow Profile Guidelines: Pb/Sn Paste” on page 5-11.

The maximum temperature most CSPs can be subjected to in Sn/Pb eclectic reflow process is 240 °C for less than 15 seconds. Intel has tested and qualified CSPs for a maximum of three reflow operations. Assuming the use of a double-sided PCB, this allows one reflow operation per side of the PCB and one rework operation if necessary.

In lead-free reflow process a higher reflow temperature is necessary. Intel Corporation selected Sn/Ag/Cu alloy which has a melting point of 217 °C. Intel recommends the lowest possible peak reflow temperatures to maintain quality solder joints. According to several Pb free solder paste

Table 5-6. Solder Reflow Profile Targets

Parameter Description Target Values Unit Measurement.

Ramp Rate (pre-heat) 1 -3 °C / second

Flux activation time (soak time 150-183 °C) 60-120 seconds

Time Above Liquidus (183 °C) 40-90 seconds

Peak Reflow Temperature 205-225 °C

Cooling Rate 2 -4 °C / second

Figure 5-8. Reflow Profile Guidelines: Pb/Sn Paste

Time Above

Liquidus

Target 40 – 90

183 ºC

Slope <3.0 ºC/sec

205-225 ºC Peak Temp

150 ºC



suppliers, 240 °C is the optimized peak reflow temperature for lead-free reflow process. Table 5-7, “Reflow Profile Targets for Sn/Ag/Cu Solder” on page 5-12 lists solder joint targets to ensure good reflow process.

By increasing the mass of electronic parts on the PCB, an increase in peak reflow temperature may be required. The maximum temperature most CSPs can be subjected in a lead-free environment is 260 °C for less than 15 seconds (at MSL 3). The oven environment can be either air or inert such as nitrogen. Inert atmosphere will minimize oxidation of the material in high temperature and may improve the assembly yield. When developing an oven profile for lead-free, the recommendation is to follow the solder paste manufacturer. Figure 5-9, “Reflow Profile Guidelines: Sn, Ag, and Cu Lead-Free Paste” on page 5-12 shows a reflow profile guideline for Sn/Ag/Cu type of lead-free paste.

5.3.5 Double-Sided PCB Process

The double-sided PCB mounting and reflow operation has been demonstrated successfully, and required no special processes. Follow the process above for each side of the PCB.

For example, solder paste is applied to one side of the PCB, units are placed on the PCB, and then the solder reflow operation is performed. The PCB is turned over, and the process is repeated. See Figure 5-10, “Cross Section of Double-Sided PCB using CSP Packages” on page 5-13.

Table 5-7. Reflow Profile Targets for Sn/Ag/Cu Solder

Parameter Description Target Value Unit Measurement.

Ramp Rate 1 -3 °C / second

Time Above Liquidus ( 217 °C) 40-90 seconds

Peak Reflow Temperature 235+/-5 °C

Cooling Rate 2 -4 °C / second

Figure 5-9. Reflow Profile Guidelines: Sn, Ag, and Cu Lead-Free Paste

Time Above

Liquidus

Target 40 – 90 seconds

217 ºC

Slope <3.0 ºC/sec

230-250 ºC Peak Temp Target 235°C +/- 5



5.3.6 PCB Cleaning

If a low residue, no-clean solder paste is used, PCB cleaning is not required, and has little effect on CSPs. With the elimination of materials containing CFC, most companies are moving to a no-clean or aqueous flux-based system. The term no-clean to describe flux or solder means simply that there are no harmful residues left on the board to cause corrosion or damage to the components. Such residue has been known to be a collection point for outside contamination on the board surface. Because so many different types of no-clean solder paste are available, application specific evaluations should be performed to see if any remaining residue needs to be removed from the boards in final application.

5.3.7 Inspection

Inspection of CSPs on a PCB is accomplished typically by using transmission type X-ray equipment. In most cases, 100 percent inspection is not performed. Typically, X-ray inspection is used to establish process parameters, and then to monitor the production equipment and process. transmission

X-ray can detect bridging, shorts, opens, and solder voids, as shown in Figure 5-11, “Results of Typical Transmission X-Ray” on page 5-13. There are many different types of X-ray inspection equipment available with varying functionality. X-ray inspection system features range from manual to automated inspection. Different systems also provide single or multiple dimensional inspection capabilities.

Figure 5-10. Cross Section of Double-Sided PCB using CSP Packages

Figure 5-11. Results of Typical Transmission X-Ray



Inspecting a folded SCSP is possible with traditional transmission type X-ray. However, a cross-section X-ray, also referred to as 3D x-ray, is recommended. A cross-section X-ray can separate the hidden layers of the folded stack and eliminate seeing an image with CSP balls from different layers. Figure 5-12, “Cross-section X-Ray of an Intel® Folded-SCSP” on page 5-14 shows a folded SCSP image through a transmission and cross-section X-ray.

Another relatively quick way to inspect for proper package alignment after the reflow process is to use alignment marks that are printed on the PCB. This is a common practice for BGA packages. The preferred method is to design the alignment marks in the metal layer on the PCB. Figure 5-13, “Signal Traces Designed for Package Alignment” on page 5-14 illustrates how the signal traces were designed to be used for package alignment simply by not covering the traces with solder mask in specific locations.

Note: Solder Mask removed to use traces for alignment.

Figure 5-12. Cross-section X-Ray of an Intel® Folded-SCSP

Figure 5-13. Signal Traces Designed for Package Alignment



As explained in Section 5.3.3, “Placement and Alignment” on page 5-9, CSPs will self align to the land pad using surface tension during the solder reflow process. Because of this, it is very unlikely that a CSP will be misaligned by a small factor. If a misalignment does occur, it is likely to be by an entire row. Because of this, it is possible to do a gross visual alignment check after the reflow. PCB alignment marks are also useful for manually placing units in the rework process.

5.3.8 Rework

Rework equipment continues to progress rapidly to address CSPs. Many manufacturers use a single rework station to incorporate multiple rework process steps, such as component removal, site redress, solder paste/flux application, alignment, component placement, and reflow. The advancement of beam-splitting imaging for alignment/placement and for other areas such as characterizing and storing individual component reflow profiles has greatly simplified the rework process.

With the direction of CSPs allowing more functionality and features on smaller products, one area of concern is thermal separation of adjoining components during the rework process. Some manufacturers have addressed this concern by designing hot gas nozzles that maintain the keep-out zone area around the rework component to thermally isolate adjacent components during the reflow process.

Original Equipment Manufacturers have differing requirements when it comes to solder paste and flux-only applications during the rework process. For those who require solder paste, micro-stencils and squeegees have been developed to correspond with multiple existing CSP sizes and ball array footprints. These micro-stencils are aligned using the same beam-splitting imaging as the component placement. Micro-squeegees allow for a simple, uniform solder paste coverage across the micro-stencil. For additional information on rework, refer to the article entitled, CSP Rework Considerations When Using Flux or Solder Paste.

5.3.9 Flux Only Attachment

The use of solder paste is recommended for best CSP package attachment results. Although the use of flux-only attachment has been a common practice for BGA packages during component rework, there are factors to consider prior to using this method. Since flux-only attachment application reduces the amount of solder within the solder joint, CSP stand-off is reduced, and the solder joint reliability may be compromised. Each manufacturer must evaluate the use of flux-only vs. solder paste in the application, and then determine the feasibility of which process to use. For additional information on rework, refer to the article entitled, CSP Rework Considerations When Using Flux or Solder Paste.

5.3.10 Reballing

Reballing CSPs is not recommended for production applications. This is due primarily to the variation of techniques for removing excess solder (redressing) from the bottom side of the CSP after the CSP has been removed from the PCB. Excessive heat during the redress process can also damage the CSP.

However, when properly controlled, reballing can be done successfully. This is a necessary process and commonly used during the failure analysis process, especially if balls must be re-attached to verify that proper programming of the flash device is completed. Special reball fixtures and tools have been designed to simplify and help control this process. For additional information, refer to the Test Accessories category in the Electronic Tools Catalog (ETC) under the “Flash Memory Tools” link at Intel’s Web page:




5.3.11 Test Accessories

Many test accessories have been developed to aid the system designer during the development and prototype stage of the product development cycle. One such debug tool developed is the CSP Signal Access Tool* (SAT).

The CSP Signal Access Tool was designed to allow test point access to all CSP input/output signals by routing the test points around the perimeter of the CSP while maintaining the required PCB keep-out zones (the required distance of any adjacent component on the PCB). The CSP SAT was designed not only to maintain minimal PCB keep-out zones of 0.025". In addition, its footprint is compatible with the CSP so there is no need to redesign the PCB.

MicroGrippers are designed to connect to the SAT or to devices with lead pitches as small as 0.012 inches using wire tip diameters of 0.003 inches. The thin body design and insulated wire tips allow side-by-side SAT placement of multiple MicroGrippers for test/debug using logic analyzers or oscilloscopes. For additional information, refer to the Test Accessories category in the Electronic Tools Catalog (ETC) under the “Flash Memory Tools” link at Intel’s Web page:


5.4 Programming Considerations

There are many ways to program flash CSPs from Intel. Traditional programming methods have been mainly off-board programming (OFBP), where the individual flash components have been programmed prior to being attached to the PCB. Another method recently being used is on-board programming (OBP) where the flash component is programmed after being attached to the PCB.

There are benefits and trade-offs associated with each type of programming approach and the ultimate decision is a question of which approach provides the most value to the OEM's manufacturing process. Some factors to consider include cost of implementation, maintenance and technical support, product mix flexibility, ease and speed of code changes, and impact to process throughput time.

5.4.1 On-Board Programming (OBP)

There are several On-Board Programming (OBP) methods to select from. Traditional Automatic-Test-Equipment (ATE) or bed-of-nail approaches are generally not practical because, generally, there is no test point access to the balls of the CSP once the CSP is attached to the PCB. One method that is gaining momentum is the use of the IEEE 1149.1 (JTAG) Test Access Port to program the flash memory. This programming method requires only four signal connections to the PCB and JTAG compliant processor. Please work with your company's design, software and manufacturing engineers to determine which method best fits your application requirements.

Intel offers the application notes listed in Table 5-8, “Additional Information” on page 5-17 to provide technical details about the various OBP methods:



New technology creates opportunities for innovative engineers to try new approaches for traditional programming challenges. Intel and our third-party vendors have developed a literature guide entitled, Flash Memory Advanced Programming and Handling that provides information about various on-board-programming techniques and handling solutions. The kit contains application notes providing the technical details required to implement OBP in a manufacturing environment.

The kit is available through the Intel Literature Centers in the United States and Swindon, order number 297787 (U.S. 800-548-4725 or +1-708-296-9333 from overseas. Swindon +44(0)1793-431155). Intel encourages you, after reviewing the information, to contact the vendors listed in the kit. They are willing to help you solve unique flash memory programming and handling challenges for your leading-edge products.

5.4.2 Off-Board Programmers (OFBP)

Off-board programming (OFBP) is widely used and many different programming manufacturers available. There are many different types of OFBP systems ranging from totally automated concurrent, multiple-site systems to manual gang, single or multiple-site systems.

Intel works closely with programming system manufacturers to ensure programmer support is available for all our flash memory products at product introductions. To find out more about the Intel programming advantage and a complete listing of CSP sockets, adapters, and device programmers that support Intel® Flash Memory CSPs, see the programming tools Web site and the Electronic Tools Catalog (ETC) under the “Flash Memory Tools” link at Intel’s Web page:


5.4.3 The Intel® Flash Memory Programmer

The Intel® Flash Memory Programmer enables system designers to program and erase all Intel® Flash Memory. The Intel® Flash Memory Programmer was designed for engineers who want to evaluate any of our flash products. We work with leading companies to ensure all software and hardware is available for your designing requirements

Table 5-8. Additional Information

Order Number Document Title

292179 AP-624 Introduction to On-Board Programming with Intel Flash Memory

292185AP-629 Simplify Manufacturing by Using Automatic-Test-Equipment for On-Board Programming

292186AP-630 Designing for On-Board Programming Using the IEEE 1149.1 (JTAG) Access Port

All Intel application notes are available at:

http://developer.intel.com/design/

Many other tools are available from the Intel Electronic Tools Catalog (ETC) web site at:




5.4.4 Distributors Value-Added Programming Service

Intel works with a variety of distributors that provide value-added programming services for Intel® Flash Memory components. If this programming method appeals to your needs, refer to the Electronic Tools Catalog (ETC) under the “Flash Memory Tools” link at Intel’s Web page:


5.4.5 Independent Programming Services

Intel works with a variety of independent programming services that provide value-added programming service for Intel® Flash Memory components. If this programming method appeals to your needs refer to the Electronic Tools Catalog (ETC) under the “Flash Memory Tools” link at Intel’s Web page:



Chapter 6 Tools and Software Support

Tools and Software Support 6

6.1 Introduction and Overview

Today's competitive flash memory market demands more than just the best products to be successful. Development tools and software for Intel® Flash Memory products help streamline the design process and reduce development time, thereby speeding time to market, saving money, and contributing to success.

Intel® Flash Memory Tools and software can be found on the Web at the Flash Tools and Software page and in the Electronic Tools Catalog.

The Electronics Tools Catalog has hundreds of tools from premier companies that provide solutions for various stages of the development cycle, including definition, design, prototype, and production stages. These tools were developed based on customer requests and industry demands.

6.2 Web Tools

Web tools help the designer by providing interactive software and documentation support, including tools such as the Intel Software Builder, On-line utilities, On-line Documentation, and Packaging Technology and Programming Tools. Definition and Design tools include support for:

• Modeling Simulation tools

• PCB Component Flexible Layout Files

• PCB Escape routing files

• Media/file manager software

• Software Templates and Software Utilities.

Prototyping and production tools include support for:

• PCB contract manufacturer support

• Programmer hardware support

• Programmer handler support

• Automatic test equipment support

• On-Board programming solutions (JTAG)

• Programming sockets and breadboard adapters

• Programming media services

• Tape-and-Reel handlers and services

• Lead inspection equipment

• Rework equipment

• Many other prototype and production tools.


Tools and Software Support

The ETC is being revised and updated constantly to provide you with the latest product support information. Please visit the ETC website for more information and for a compressive list of tools at http://appzone.intel.com/toolcatalog

6.3 Intel® Flash Memory Software

Intel software engineers have worked hard to develop complete and flexible software solutions so you do not have to. For years, OEMs around the world have been taking advantage of this resource, bringing innovative products to market faster and with less development effort than ever before. No matter what the application for Intel® Flash Memory products, it is likely that a solution already exists to simplify integrating flash into your design. The Intel® Flash Memory SOFTWAREBuilder utility provides information on many different software solutions that can be incorporated into a product design. It can be found on the Tool and Software Web page. It has been designed to help you learn more about the software solutions that serve as a companion to the broad line of Intel® Flash Memory components.

6.3.1 Intel® Persistent Storage Manager

Intel® Persistent Storage Manager (Intel® PSM) software simplifies your design by combining all nonvolatile memory functions into a single chip. The solution enables the combination of executable code (WCE XIP code), registry back-up, and fully integrated file storage in a single Intel® Flash Memory product. This optimization reduces power consumption and component count as well as inventory, board, and manufacturing costs. At the same time, it delivers increased system reliability and valuable user storage through the standard WCE file API, while opening new application possibilities.

6.3.2 Intel® Flash Data Integrator

Intel® Flash Data Integrator (Intel® FDI) is an Intel software solution for wireless applications. Many system designers are interested in using flash memory to store system and user data, as well as to manage code in difficult real-time situations. By using a single, high density, NOR-based flash memory device both to directly execute code and store data, applications benefit by eliminating the need for a separate data storage memory device such as EEPROM or battery backed RAM. This saves system cost, power consumption, and board space. Using a flash memory that may be already in the system for data storage is a fraction of the cost of EEPROM and battery-backed SRAM. The solution is a fully tested, debugged, and Intel-supported code and data manager for use in real-time applications, such as base-band data storage in wireless applications, saving many man-months of software engineering effort.

6.3.3 Intel® Virtual Small Block File Manager

Intel® Virtual Small Block File Manager (Intel® VFM) is a flash and file manager designed for simple data store application. It is provided in source form and works on a wide variety of processors and Intel® Flash Memory devices. Simple embedded applications that need sophisticated flash/file management capability are easily enhanced with Intel® VFM.

Please visit the Intel Flash SOFTWAREBuilder site for more details on these and other flash software options.


Chapter 7 Quality and Reliability Engineering

Quality and Reliability Engineering 7

7.1 Introduction

Quality and reliability (Q&R) are core values for Intel Corporation. Intel's extensive network of research and development laboratories combined with more than thirty years of packaging experience has made Intel a world leader in quality and reliability for advanced packaging technology. Intel places great emphasis on quality and reliability during technology development, product development, and manufacturing. From the earliest phases of product definition through high volume manufacturing, quality and reliability are designed in and thoroughly validated.

7.2 Q&R in Technology Development

Technology development involves fundamental understanding of electrical and mechanical properties for new packages. During technology development, package material properties are carefully studied to identify the materials that provide the best combination of performance and reliability while meeting manufacturing needs. Material weight, electrical properties, moisture absorption, resistance to high temperature, and thermal expansion properties are studied.

The most promising materials are used to construct configuration prototype samples. These samples are used to study the effects that package geometry, ball-out, and stacking configurations have on reliability. An exhaustive set of both discrete and board level reliability stresses are conducted using silicon test structures. These results are used to generate coefficients for finite element stress analysis modeling that further optimizes package geometry, stacking configurations, interposer design and ball-out. An example of this analysis is shown in Figure 7-1, “Finite Element Analysis” on page 7-1.

Figure 7-1. Finite Element Analysis

CSP-03204


Quality and Reliability Engineering

Only after a new package technology has been thoroughly characterized and modeled to ensure excellent quality and reliability are products developed and evaluated for that technology. Figure 7-2, “Example of Temperature Cycling Data” on page 7-2 shows an example of the reliability stress data collected during technology development. It contains board level temperature cycling data for the Easy BGA package from Intel.

7.3 Q&R in Product Development

Products using a package technology are evaluated for quality and reliability during product development. The purpose of these evaluations is to identify and resolve quality and reliability issues related to a specific silicon configuration at a specific manufacturing facility. As the underlying package technology is characterized and well understood during the previous technology development phase, quality and reliability issues during the product development phase are rare. The package related product quality and reliability tests/stresses performed during product development are:

• Quality Validation - Units are tested through full datasheet testing at the upper and lower specification limits. This test ensures production test coverage integrity

• Bake - Unbiased temperature stress of 140 °C for 1000 hours. This stress test detects package related passivation integrity or contamination issues.

• Temperature/Humidity/Bias - Stress condition of 130 °C temperature, 85% relative humidity, 2.2 atmospheres of pressure, and odd-even pin voltage bias applied to units for 168 hours. This stress test detects electrolytic corrosion or moisture penetration of the silicon die.

• Temperature Cycling - Performed according to JEDEC temperature cycling specifications at both discrete and board level. This is primarily to detect problems with interconnect integrity inside of the package or at the solder ball connection to the PCB.

Figure 7-2. Example of Temperature Cycling Data

B = 10.17

= 2043.650

R-squared = 0.68

N = 50N fails = 38

Predicted X

o Failures

80% Lower Bound80% Upper Bound

Char. Life Mark

99%

95%90%80%70%60%50%40%

30%

20%15%

10%

5%

1%

0.5%

0.1%

Lot 4: Easy BGA Flash 16 ES

Brd: 30 mil Sup: #1

T/C Cond. -40/125 In progress

Cycle Rej/SS

Readout Amb -40 C

Pre-Stress 0/50

200 0/50 0/50

1 K 0/50 0/50

1.2 K 0/50 0/50

1.5 K 10/50 10/50

2 K 28/40

100 1000 10,000CSP-03205



• Precondition/Reflow - A 3x or 5x simulated SMT reflow preceded by JEDEC standard precondition is conducted before temperature/humidity/bias stress and temperature cycling. Packages are inspected for delamination using acoustic microscopy immediately following reflow and the subsequent stress.

If these stresses and other silicon related stresses show excellent quality and reliability the product is released to production.

7.4 Q&R in Manufacturing

Intel makes extensive use of statistical process control combined with factory automation to ensure the highest levels of manufacturing consistency. After manufacturing, Intel performs one-hundred percent automated electrical testing to ensure the quality of its products.

7.5 Customer Service & Support

Intel maintains an extensive network of worldwide quality support centers to provide fast and professional support in all geographies. Each quality support center is staffed by engineers knowledgeable in Intel® Wireless Communications and Computing product and package technologies that can help address issues quickly. Please contact you local Intel field sales office for more information.


Chapter 8 Lead-Free Program Overview

Lead-Free Program Overview 8

8.1 Introduction

The use of small amounts of lead in electronic products has been common for many years. Lead is found throughout electronic components, component packaging, printed circuit boards (PCBs), and products. Intel estimates that approximately 90% of all electronic components contain some amount of lead.

This use of lead in electronic products is an increasingly visible environmental and political concern. Although significant uncertainties remain about the potential for lead contained in electronic products to have any impact on human health or the environment, Intel has an ongoing initiative to reduce lead in its products. There are many difficult scientific, technological, and economic challenges associated with this initiative that affect the entire electronics industry. The transition to lead-free electronic products is a massive undertaking and will require coordinating efforts by all members of the supply chain from raw material manufacturers to original equipment manufacturers (OEMs). Intel has dedicated its resources to work with suppliers and other companies in the semiconductor and electronics industry to develop lead-free solutions

For additional lead-free program information, please go to the following URL to the Q&A section: http://www.intel.com/research/silicon/leadfree.htm. (Please see Section 8.7, “Halogen-Free Overview” on page 8-3.)

8.2 Direction

Intel is committed to finding appropriate and cost-effective ways to reduce lead in its products and is also proactive in working with other companies in the industry to establish standards and identify compatible technologies to support migration away from tin-lead solder.

8.3 Higher Peak Temperature Reflow

One of the technical challenges that face electronic packaging is the higher reflow temperatures that typically are required by lead-free surface mount processes and package terminals. The lead-free solders typically melt at 35 °C higher than traditional tin/lead solders. This increased temperature affects the moisture sensitivity performance of packages, often raising the moisture sensitivity rating by one level.

At Intel, the conversion to lead-free packages has been a two-phase development process. The first phase evaluated the ability of packages from Intel to withstand the higher reflow temperature requirements often associated with lead-free solder pastes used in surface mount (SMT) processes. The second phase involved the development of lead-free terminals or solder spheres.

Intel recognizes that there are a variety of surface mount assembly applications. It is our goal to provide our customers with the support needed to ensure a successful transition to lead-free assembly.

Wireless Communications and Computing Package User’s Guide 8-1

Lead-Free Program Overview

8.4 Lead-Free Package Moisture Sensitivity Level

Although Intel does not specify a maximum storage shelf life for lead-free packages, the current floor life will vary depending on the type of package based on the IPC moisture sensitivity rating as per IPC/JEDEC standard J-STD-020B. Generally, all lead-free solder CSP packages are targeted for an IPC level 3 (1 week out of the moisture barrier bag (MBB) at = 30 °C and 60% relative humidity).

However, each package is qualified independently and may vary, and the manufacturing process is constantly being improved so IPC levels are subject to change. You should always refer to the MBB label for the exact IPC moisture level rating.

8.5 Lead-Free Alloy Selection

Much research has been conducted by the North American Electronics Manufacturing Initiative (NEMI) consortium consisting of over fifty electronics companies and governmental agencies resulting in the recommendation of the primary Sn-Ag-Cu lead-free alloy group. Other alloys that were initially under consideration by Intel are shown in Table 1.

Several of the industry available Sn-Ag-Cu solder alloy combinations were then chosen and evaluated for their manufacturing and reliability capabilities. Based upon the results of these evaluations, the final alloy chosen for the packages is 95.5 Sn/4.0 Ag/0.5Cu.

This alloy melts at 217 °C to 219 °C providing effective reflow properties while at low enough temperatures to prevent damage to components. The alloy is compatible with current SMT processes used throughout the industry.

8.6 Lead-Free Process Recommendations

Intel Corporation recommends the lowest possible peak reflow temperatures to maintain quality solder joints. According to several lead-free solder paste suppliers, 240 °C is the optimized peak reflow temperature. By increasing the mass of electronic parts on the PCB, an increase in peak reflow temperature may be required.

The maximum temperature most BGAs can be subjected to is 260 °C for less than 15 seconds (at MSL 3). Intel has tested and qualified these packages for a maximum of three reflow operations. This allows one reflow operation per side of the PCB (assuming the use of a double sided PCB), and one rework operation if necessary. The reflow profile guidelines are based on the temperature

Table 8-1. Alloy Selection Considerations

Alloy Material Information Melting Temperature Celsius

Sn - Pb Current Solder Ball Alloy 183

Sn-Ag-Cu NEMI Recommended, ~217

Good Industry Acceptance

Sn-Ag-Cu-Sb Proprietary Alloy ~217

Sn-Bi Incompatible with Pb 140

Sn-Zn Severe oxidation issues 190

Sn-Ag Poor wetting 220

8-2 Wireless Communications and Computing Package User’s Guide


at the actual solder ball to PCB land pad solder joint location. Please see Chapter 5, “Manufacturing Considerations” for a lead-free profile and other surface mount process recommendations.

During the lead-free component transitional period, some customers may be considering a mixture of technologies. The use of a standard eutectic tin/lead component in a lead-free paste surface mount process is called Forward Compatibility. Intel does not recommend the use of its tin/lead components in forward compatible assemblies.

The other type of mixed technologies is that of Backward Compatibility. Backward compatibility refers to using the lead-free version of a component in a standard tin/lead surface mount solder paste and process. Intel does not recommend the use of its lead-free components in backward compatible assemblies.

8.7 Halogen-Free Overview

Products from Intel do not contain polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE). PBB is currently banned and certain PBDEs will be banned by February 2004.

Intel is evaluating the use of bromine-free flame retardants in its products and is also working with suppliers and several industry consortia to drive the development of environmentally safe and technically reliable replacement materials.

Only a select-few bromine-free flame retardant materials are known to be currently available in the industry for use in component and board materials. Their reliability, cost equivalency, and environmental quality and safety are yet to be proven. Intel will continue to assess supplier capabilities and customer requirements for products containing bromine-free flame retardants and communicate its position accordingly.

8.8 References

• RoHS (EU Restriction on Hazardous Substances)

http://europa.eu.int/eur-lex/en/oj/2003/l_03720030213en.html

• NEMI (National Electronics Manufacturing Initiative)

http://www.nemi.org

• HDPUG (High Density Package Users Group)

http://www.hdpug.org

• JEDEC (Joint Electronic Device Engineering Council)

http://www.jedec.org

• IPC

http://www.ipc.org

• JEITA: Japan Electronic Industry Association

http://www.jeita.org

Wireless Communications and Computing Package User’s Guide 8-3


8-4 Wireless Communications and Computing Package User’s Guide

Appendix A

Chip Scale Package Rework Considerations: Using Solder vs. Gel Flux by Paul Wood, OK International

Chip Scale Package Rework Considerations: Using Solder vs. Gel Flux

An Article by Paul Wood, OK International

The decision to use solder paste or gel flux when reworking Chip Scale Packages (CSPs) requires careful manufacturing considerations and is ultimately the decision of the original equipment manufacturer (OEM).You must take into account several considerations prior to deciding, such as application process, reliability, CSP material set (i.e., Pb and Pb free), and rework temperature profile. This article describes these considerations.

1.0 Solder Paste vs. Gel Flux

The rework process should match your SMT (Surface Mount Technology) process as closely as possible to provide the same type of quality and reliability to the end product. However, some rework processes include evaluating some of the following pros and cons of using only gel flux instead of solder paste during the rework process:

1.1 Key Points Regarding Gel Flux

• If the CSP has a solid construction and gets hot in use, the thermal co-efficient (TCE) difference between the part and the PCB may be under stress. If so, the solder joint strength has to be as strong as possible.

• The pad area of the PCB must be coplanar flat to ensure strong adhesion to the circuit PCB.

• For flux only to be used in rework, the CSP must have eutectic solder balls, not gold bump or 90/10 solder compositions.

• The size of the joint will be smaller after rework if flux only is used compared to a part placed with solder paste. For example, when soldered to the PCB, a solder ball that starts off with a 12-mil ball will reduce in diameter if no additional solder is used. One alternative method is to apply solder paste directly to the part or PCB during rework. Also, the specific size will vary depending on pad size and solder mask vs. non-solder mask defined.

• Package stand-off height (distance from PCB surface to bottom of CSP) is greatly reduced when using flux only.

• When a part is soldered with solder paste, the ball size increases in diameter (when using a 12 mil trapezoidal etched stencil 5 mil thick) as in the production assembly process. This can be duplicated in rework if needed.

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• Thermal cycle tests and shear tests should be carried out to check the strength of the joint to verify the need for flux or solder paste in rework. If these tests meet the company requirements for reliability and quality, attachment with flux may be acceptable.

• If liquid flux is used, care must be taken to spread the flux over the pad area when applying with a "paintbrush." Too much flux can hold the part off the PCB and cause openings and voids. Although the quickest method, the paintbrush application is not the most successful method. Too often, flux is left in a tub with no lid, and with brushes dipped in to apply flux, the flux solvents evaporate and create inconsistent amounts of rosin for varied rework results. Flux transfer is a better alternative to this brush method.

• Flux transfer, better known as dip transfer, works well with no clean gel flux and is a better method of applying a consistent, repeatable amount of flux to ensure process control.

2.0 General Gel Flux Application

2.1 Brush Application vs. Flux Transfer Method

Most flux problems occur when numerous operators apply varying amounts of flux on the PCB; Too many operators and various ways of applying the flux cause the results to vary. If it is an activated flux, it must be removed with either a spray or a brush. However, flux residue may not be completely removed when using flux removers, and this creates potential for failure due to contamination and IRL (Insulation resistance leakage / breakdown). One method for transferring a specific amount of flux to the component/PCB is to use a specially made flux dip plate that holds a pocket of flux.

2.2 Gel Flux Compared to Liquid Flux

Gel flux works better during rework because it is designed to have a longer activation time, which is required for reflow. Gel flux is designed to be active in the normal reflow cycle of four to six minutes of heating and cooling; it is used in most reflow oven processes.

Liquid Flux is used during the wave solder process and is a quicker solder process allowing the flux to dry before reflow temperature is reached.

The manufacturing process should be duplicated for rework as closely as possible. If the rework machine is available and is full convection, typical temperatures used in the reflow oven can be transferred to the rework machine for a start point in setting up the reflow parameters on the rework machine. This does not work with radiated IR or hot plate systems.

2.3 How Gel Flux Transfer Works

Gel flux transfer occurs as follows: First, a CSP flux transfer plate is made the same size as the area of the solder balls and machined 6 mils (0.15 mm) deep. Next, the gel flux is dispensed into the machined area and made smooth with a manual squeegee (supplied with the plate). Then, the component pick up block is placed onto the rework machine to allow the component to be picked-up in the center, and the center block is removed and the flux transfer plate is placed into position.

The component is then dipped into the plate until the balls contact the plate. This puts a coating of flux on the bottom half of the solder balls vs. being applied to the PCB.

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The part is then aligned and placed onto the PCB pads with prism alignment of "balls to pads" viewed on a monitor. Finally, reflow takes place and any small amount of flux remaining usually can't be seen due to the minimal amount applied to the solder ball tip and pad. (See Figure 1.)

2.3.1 Basic Methods of Gel Flux Transfer from Dip Block to Solder Ball

Gel flux transfer from dip block to solder ball occurs as follows: In Stage 1, as shown in Figure 2, the component is picked up in vacuum pick up. The flux dip block is inserted in the pick up block. Gel flux is spread onto the working area of flux transfer block. Gel flux is then evenly distributed into the flux transfer block by squeegee, the component is held in vacuum, and then positioned above flux/paste area.

In Stage 2, the component is dipped into a known depth of gel flux. The dipped area has coated the flux onto the balls of the CSP component as shown in Figure 3.

Figure 1. Dual Image Overlaid Alignment of CSP Solder Bumps and Flux Paste Pattern of PCB

Figure 2. Stage 1: Gel Flux Transfer from Dip Block to Solder Ball

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In Stage 3, the component is withdrawn, leaving the deposit on each solder ball, as shown in Figure 4.

2.3.2 Solder Paste Printing on the Component

The rework of high reliability parts or PCBs can be improved by quickly and easily adding solder paste to the component. Older methods of printing on the PCB were successful, but highly skilled operators were required due to the complexity of applying the solder paste.

A tool and method is now available for quickly and easily printing solder paste on the component balls to duplicate the solder deposition originally used in production assembly methods. Different ratios are used to achieve this, and it is usually quick and simple to order plates from Metcal. This method overcomes flatness specification problems with the part and with the PCBs. Also, using this method provides the solder joint strength that existed when the part was originally manufactured. Simple application of solder paste can also improve rework yields.

Good printing can be inspected before assembly on rework machine vision. Deposition is controlled by plate manufacture. See the following:

• Figure 5, “Squeegee Printing of Solder Paste,” on page 5

• Figure 6, “Good Printing Inspection,” on page 5

• Figure 7, “Solder-Paste Pre-Reflow of Component after Printing and Placement to PCB,” on page 5

Figure 3. Stage 2: Component is Dipped into Gel Flux

Figure 4. Stage 3: Component is Dipped into Gel Flux

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3.0 Precise Component Placement

CSP placement is notably similar to that of a BGA. Both types of packages contain connections on the bottom-side array matrix. Therefore, precise alignment between the solder bumps and mating land pattern cannot be achieved by eye. Alignment should be made throughout the utilization of a split-beam optical system, where a dual-image of the CSP solders bumps and mating land pattern can be viewed on a high-resolution monitor. Due to the tight specifications associated with CSPs, alignment should be achieved within the window of (30x - 100x) magnifications. The ideal placement machine should give the operator the ability to make fine adjustments between the overlaid images in the X, Y, and rotational axis. A CSP can properly align itself during reflow even if it is as much as 50% misaligned with the diameter of the mating pads or balls, whichever is the smaller.

Figure 5. Squeegee Printing of Solder Paste

Figure 6. Good Printing Inspection

Figure 7. Solder-Paste Pre-Reflow of Component after Printing and Placement to PCB

5

3.1 CSP Re-Attachment

Since the optimum rework profile parameters were developed during the initial removal process, the same reflow profile can be used for reattachment, as well as for subsequent removal processes. No additional thermocouple feedback or operator dependency is required since all parameters were optimized during the removal profile and stored in the memory of the rework system. Therefore, profiles can be recalled with the touch of a button for both placement and removal. Taking shortcuts by shrinking the duration of the reflow profile should never be done, specifically because the CSP is a small component. The reflow profile parameters employed in the rework process must conform to those specified by the flux manufacturer.

3.2 Reflow

The basic steps to the removal and replacement of CSPs are straightforward:

1. Establish thermal profile.

2. Remove failed component.

3. Clean and prepare site.

4. Replace component with flux or solder paste.

5. Reflow.

6. Inspect.

Convection rather than radiation is the heating method of choice. Using a soldering iron (conduction) is not an option. In addition, convection allows for tight process control, which is essential in establishing a good, repeatable thermal profile that will not overheat the component or hold for too long above reflow. Establishing the correct profile takes experience and patience. The basic requirements for any profile are well understood. (See Table 1 and Figure 8.)

Table 1. Standard Reflow

Zone Time Duration (Seconds) Target Temperature (°C)

Pre-head 60 to 90 100 to 120

Soak 60 to 90 155 to 175

Reflow 30 to 60 200 to 220

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3.3 Differences: Lead-free Solder and Normal Eutectic Solder

This process is particularly critical when working with lead free solder assemblies. The higher temperatures needed for lead-free (up to 225°C) coupled with the thermal sensitivity of CSPs can be problematic without the ability to ramp temperatures at a rate that will not harm packages. The latest technology rework systems are more likely to employ four heating zones and one cooling zone. Older systems work with a more traditional three-zone model and no system for cooling down. The addition of a controllable pre-heater to a rework system helps meet future process demands, including lead-free. Efficient, controlled pre-heating avoids the thermal damage risked when working expensive but sensitive packages unsuitable for heating above 240°C with quick reflow times.

Some lead-free reflow profiles are as short as 15 seconds above specified reflow temperature.

A typical lead-free profile is shown with peak temperatures around 223 °C to 235 °C and at times is as low as 15 seconds in the reflow zone. This means excellent temperature controls and profile controls are essential. (See Table 2 and Figure 9.)

Lead-free material composition varies by product and specific product manufacturer's reflow recommendations should be followed when possible.

Figure 8. Standard Reflow Profile

Table 2. Lead-free Reflow

Zone Time Duration (Seconds) Target Temperature (°C)

Pre-head 100 130 to 140

Soak 90 140 to 170

Ramp 100 170 to 225

Reflow 15 to 30 225 to 235

7

To help protect packages from the increased heat of lead-free processes, independent top and bottom heater control is essential. In short, as lead-free alloys become mainstream, greater care must be taken to develop a thermal profile that can reflow the new alloys without damaging CSP and BGA packages.

Through closed-loop, time, temperature and airflow parameters, contemporary rework systems can help operators adapt to lead-free. In addition, and just as important, enhanced process control features guarantee repeatability, which is critical for companies with multiple locations in various parts of the world. Different voltages and frequencies affect performance of machines in many cases.

On any reflow soldering system that heats both sides of a PCB assembly, the required solder joint temperature is a function of how much heat is applied to both sides. And while it is possible to reach a specific solder joint temperature with a number of heat settings, the incorrect combination can lead to low yields and, in some cases, catastrophic results, including warping due to excess heat on the topside. This often causes bridges in the corners of BGA and CSP packages.

It is here that experienced operators using equipment that allows for precise process control can play a paramount role in successful rework. If minimal warping occurs, for example, a BGA lifted by just 0.1 mm (0.004") across the device is enough to cause an open circuit. Even if the board/component survives this process with no apparent defect, the joint will be constantly under strain as the board returns to its normal shape, causing long term reliability problems.

Eliminating warped generally involves creating a better balance between the bottom and topside of pre-heat temperatures. This is best achieved with full convection, as in the assembly line reflow ovens.

Figure 9. Typical Lead-free Profile

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4.0 Convection and Airflow

Convection systems employ either high or low airflow. For CSP rework, for instance, low airflow systems are preferred. As already stated, CSPs are normally found on high density PCBs. Space is at a premium and adjacent components can be easily reflowed and moved out of place during the rework process. High airflow systems increase the changes of moving adjacent—ruining alignment and creating more rework. Low airflow systems reduce the chance of shifting components, provided airflow levels are below 15 liters per minute and they feature a low velocity reflow nozzle design.

Metcal's APR-5000 Array Package Rework System, shown in Figure 10, uses low airflow forced convection heating, with a patented reflow head to deliver temperature uniformity, ensuring safe and simultaneous reflow of the component being removed without disruption to adjacent devices.

Once reflow is accomplished, component removal is generally accomplished with a vacuum pick-up. Care must be taken as excessive vacuum pressure can cause the solder to collapse and adhere to the PCB, making clean up slower and difficult.

5.0 PCB Clean-up

PCB clean-up is the longest part of the rework process and requires the most skill. There are several ways to clean the PCB: One way is to use a desolder tool or vacuum removal tool. Note that the generic solder iron is a ceramic iron element and can have thermal difficulties if an inferior iron is used.

Another way to clean the PCB is to use a solder wick or blade tip. When using a blade tip, multiple pads can be covered at once to make the suction of solder into the braded wick quicker and easier.

The Metcal iron technology is superior to all other solder irons as it is RF and does not change temperature with high load applications such as solder wick clean up.

The solder iron temperature may cool by as much as half during the clean up process. When this happens, the brade becomes soldered to the PCB, and this can result in pad lift easier than normal. Assuming a good blade tip and iron are used, this is a reliable method of solder removal so a new part can be replaced with flux or solder paste.

The desolder method is often a solution, but this method fills the solder collectors quickly, especially on a high ball-count BGA device. For a CSP, a small amount of solder is used, and this is more popular. The most common method is shown in Figure 11.

Figure 10. Metcal’s APR-5000 Array Package Rework System

9

Different size blades are available for small CSP packages and are quick and easy to use. The blade can be used vertically or horizontal depending on access to work area.

6.0 Rework Inspection

Unlike traditional leaded surface mounted devices, the human eye cannot verify solder joint integrity, as the array of interconnections is hidden beneath the CSP. As with BGA inspection, X-ray equipment was the only way to inspect BGA and CSP packages. Recent introduction of vision inspection systems to look under the components are now more popular and offer a better cost effective solution for inspection compared to X-ray. Although both have advantages, a combination of both systems will allow the user to see all defects. For instance, flux residue cannot be found with an X ray system and solder ball voids cannot be found with a vision system. So to compare the difference between flux application and flux residue "post-rework," a vision system is needed and is a good low-cost process solution tool.

With BGA packages, a simple touch-up of discovered defects is not possible. Rectification of any defect calls for the removal of the entire component followed by the entire rework cycle. But again, the impact can be minimized by strict control of the rework process.

The flux shown at the base of the ball in Figure 12 is insulation between the solder ball and the pad and excessive flux applied by manual brush method, not by flux dip. (See also Figure 13, showing a good solder joint on the Vision System.

Figure 11. Solder Removal with Wick and Blade Tip

Figure 12. Solder Removal with Wick and Blade Tip

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The X-Ray on the left in Figure 14 shows defects shown with a two-dimension X-Ray system; Note the voids in the balls. Reflowing too quickly can cause voids or extended preheating that dries out the flux before reflow takes place. Generally, if there is 25% void, then the solder joint is considered a failure or suspect.

The X-Ray on the right in Figure 14 shows a CSP that passed inspection. Note that all solder joints are uniform in appearance with no evidence of voids or bridging.

7.0 Post Rework CSP Cleaning

Removing contaminants or even inspecting for residue in the very small spacing between the CSP and PCB is possible with a vision system. Consistent use of no-clean fluxes on CSP assemblies is recommended to eliminate the need for cleaning, if this is acceptable to the customer's process. Remember if a gel flux is only used to rework the part, then the stand-off height of the component to PCB is smaller than a pasted joint. If flux dip is used, very little flux residue remains and is local to the pads or balls and does not contaminate the PCB surface as would applying flux with a brush.

Figure 13. Good Solder Joint Shown on Vision System

Figure 14. Balls Show Evidence of Voids (Left) and Perfect X-Ray of CSP (Right)

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8.0 Conclusion

In the rework process, CSP packages share many positive attributes as well as challenges with their larger predecessor, the Ball Grid Array. Solder paste deposition is by far the most challenging aspect of the CSP rework process. One approach to meeting this challenge is the use of single-component rework stencil plates, a simple and quick way to print solder paste onto the package.

Printing the balls with solder paste duplicates the solder paste that would have been on the PCB during original manufacturing. This method actually duplicates the volume of solder at each joint for a repaired CSP, helping maintain high reliability and the strength of the joint to a level equal with production PCBs. The resulting stand-off height can be verified with a vision system that can be easily measured. CSP rework is easy if good process control exists in the rework system.

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intel® wireless communications and computing package users guide

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