intel 28f008-sa interface guide

8/12/2019 Intel 28F008-SA Interface guide

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APPLICATION

NOTE

AP-359

November 1996

28F008SAHardware Interfacing

BRIAN DIPERTMCD MARKETING APPLICATIONS

Order Number 292094-004


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COPYRIGHT INTEL CORPORATION 1996


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28F008SA HARDWARE INTERFACING

CONTENTS PAGE

10 INTRODUCTION 1

20 HARDWARE INTERFACING 2

21 VPP(Byte WriteBlock EraseVoltage) 2

VPPGeneration Circuits 3

Controlling VPPto 28F008SAComponent(s) 3

22 RYBY(ReadyBusy) Output 4

23 RP(ResetPowerdown) Input 4

Deep Powerdown Mode 4

Write Protection 5

Reset Control 5

24 WE(Write Enable) Input 5

25 Power Supply Decoupling 5

26 High Speed Design Techniques 6

27 Example Bus Interfaces 6

CONTENTS PAGE

ADDITIONAL INFORMATION 7

APPENDIX A Intel386TM SL PI BusInterface A-1

APPENDIX B Intel486TM SX Local CPUBus Interface B-1


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AP-359

10 INTRODUCTION

The 28F008SA FlashFileTM Memory is a very highperformance 8 Mbit (8388608 bit) memory organizedas 1 Mbyte (1048576 bytes) of 8 bits each The28F008SA contains sixteen 64 Kbyte (65536 byte)

blocks each block separately eraseable and capable of100000 byte write-block erase cycles On-chip automa-tion dramatically simplifies software algorithms andfrees the system microprocessor to service higher prior-ity tasks during component data update An enhancedsystem interface allows switching the 28F008SA into adeep powerdown mode during periods of inactivity andgives a hardware indication of the status of the internalWrite State Machine High-speed access time allowsminimal wait-state interfacing to microprocessor busesand advanced packaging provides optimum densityin2

Features of the 28F008SA include

High-Density Symmetrically Blocked Architecture

Sixteen 64 Kbyte Blocks

Extended Cycling Capability

100000 Block Erase Cycles

16 Million Block Erase Cycles per Chip

Automated Byte Write and Block Erase

Command User Interface

Status Register

System Performance Enhancements

RYBY Status Output

Erase Suspend Capability

Deep Powerdown Mode

020mA ICC Typical

Very High Performance Read

85 ns Maximum Access Time

SRAM-Compatible Write Interface

Hardware Data Protection Features

EraseWrite Lockout during Power Transitions

Industry Standard Packaging

40 Lead TSOP 44 Lead PSOP

ETOX III Nonvolatile Flash MemoryTechnology

12V Byte WriteBlock Erase

2920941

Figure 1 The 28F008SA Revolutionizes the Architecture of Computing

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Figure 2 28F008SA Block Diagram

Traditional system architectures combine slow highdensity nonvolatile mass storage (such as a disk drive)and fast volatile memory (such as DRAM) to fullyaddress system requirements As Figure 1 illustratesflash memory combines the best features of both theabove memory technologies making a diskDRAMapproach to system architecture unnecessary and ulti-mately wasteful Flash memory is rapidly approachingDRAM in both cost and performance (especially incached systems) while adding capabilities (such as non-volatility) that DRAM cannot claim The 28F008SA

will be the building block memory of choice for emerg-ing computing markets whether integrated in a memo-ry card or disk drive form factor or resident on thesystem motherboard

This application note discusses hardware interfacing ofthe 28F008SA flash memory to system designs The28F008SA datasheet (order number 290429) is a valu-able reference document providing in-depth devicetechnical specifications package pinouts and timingwaveforms AP-364 28F008SA Automation and Algo-rithms discusses in-depth operation of the 28F008SAWrite State Machine and internal algorithms empha-sizing how they interface to system software and hard-ware AP-364 should be reviewed in conjunction withthis application note and the 28F008SA datasheet for acomplete understanding of this device

20 HARDWARE INTERFACING

Figure 2 shows a block diagram of the 28F008SA andits internal contents The CE (chip enable) and OE

(output enable) inputs have comparable enable andread functions to those of other memory technologiessuch as SRAM Similarly VCCis the component powersupply (5V g10%) while GND should be connectedto system ground Address inputs allow the system toselect a specific byte for reading or writingerasing andthe 8-bit data bus transfers information to and from the

28F008SA The other control lines (WE RPRYBY and VPP) are discussed below

21 VPP(Byte WriteBlock EraseVoltage)

The VPP input supplies high voltage to the 28F008SAto enable byte write and block erase VPPis specified at12V g5% (114V126V) Attempting to byte write orblock erase the 28F008SA beyond the 5% 12V toler-ance is not recommended VPPabove 126V can poten-tially result in device damage and VPP below 114Vdramatically lengthens writeerase time and compro-mises data reliability The 28F008SA is guaranteed toprevent byte write and block erase attempts with VPPbelow 65V and in this situation it reports a low VPPerror through the component Status Register (see AP-364 or the 28F008SA datasheet)

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AP-359

VPPGeneration Circuits

12V is often already present in systems used to powerthe hard drive display RS-232 circuitry flash BIOSupdate etc If it meets the tolerance and current capa-bility requirements of the 28F008SA such a power sup-

ply could be used directly as the 28F008SA updatevoltage source However 12V is sometimes not presentor otherwise required and in such cases the 28F008SAVPP must be derived from existing voltages and sup-plies

Fortunately flash memorys rapidly increasing popu-larity has driven ever-improving 12V converter avail-ability in the market These solutions derive a regulated12V from a wide range of input voltages and offer var-ied levels of integration and current delivery capabilityIn general the input for 12V converters should comefrom the unregulated system power source particularlyin battery-powered systems

Table 1 lists and briefly describes several 12V genera-tion solutions available at the time this document was

published This is by no means an exhaustive list anddoes not reflect any specific recommendation by IntelCorporation For in-depth information on power sup-ply solutions for flash memory reference Intel applica-tion note AP-357 (order number 292092) availablethrough your local Intel sales office or distributor

Controlling VPPto 28F008SA Component(s)

Once 12V is available in the system how is it con-trolled One approach is to hard-wire 12V from thesupply directly to the VPP inputs of each 28F008SA inthe system The advantage here is in design simplicityand board space savings The 28F008SA CommandUser Interface architecture and two-step byte writeblock erase command sequences provide protectionfrom unwanted data alteration even with high voltagepresent on VPP All 28F008SA functions are disabledwith VCCbelow lockout voltage VLKO(22V) or when

RP is at VIL (see section 23) This provides dataprotection during system powerup when the minimal-ly-loaded VPP supply often ramps to 12V before VCC(and therefore control inputs to the device) are stable

For additional data protection the system designer can

choose to make the VPP supply switchable via a GPIO(General Purpose InputOutput) line enabling 12V tothe 28F008SA only during byte write or block eraseattempts A switchable VPPalso minimizes power con-sumption by both the flash memory components andthe 12V supply or converter (due to efficiency losses)Many 12V converters integrate an ENABLE inputeliminating external circuitry If such an input is notavailable a low drain-source resistance MOSFETswitch such as the Motorola MTD4P05 can be used atthe 12V supply output An example schematic for thisswitch is shown in Figure 3 The calculations belowshow that the low drain-source resistance of theMTD4P05 will keep a 12V input within the 5% toler-ance required by the 28F008SA

RDS e 06X

IPP e 60 mA

(worst case two components being byte written orblock erased)

DVSWITCHDROP e (60 mA c 06X) e 004V

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Figure 3 VPPSwitch Schematic

Table 1 12V Conversion Solutions for VPP

Part Input Current Total Est

ManufacturerNumber (V)

PackageOutput

Components Cost

Needed (10K)

Maxim MAX732 4 to 75 16 SOIC 120 mA 9 $393

Linear Technology LT1110-12 45 to 55 SO8 120 mA 11 $458

Linear Technology LT1109-12 45 to 55 SO8 60 mA 8 $361

Motorola MC34063A 45 to 55 SO8 120 mA 15 $225

Maxim MAX667 121 to 165 SO8 120 mA 4 $263

Linear Technology LT1111-12 16 to 30 SO8 120 mA 7 $395National Semiconductor LM2940CT-12 13 to 26 TO-220 1A 3 $130

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22 RYBY(ReadyBusy) Output

The 28F008SA offers similar automated byte writeblock erase capabilities to those first seen in the28F001BX Bootblock flash memory family introducedby Intel in May of 1991 It enhances these capabilities

via the RYBY output which provides hardware in-dication of internal Write State Machine (WSM) opera-tion RYBYis a full CMOS output constantly driv-en by the 28F008SA and not tristated if the deviceCE or OE inputs are brought to VIH RYBYsdefault state after device powerup is VOH It transitionslow to VOL when a byte write or block erase sequenceis initiated by system software and RYBYs risingedge (return to VOH) alerts the system to byte write orblock erase completion RYBY also goes to VOHafter the 28F008SA is put in Erase Suspend or DeepPowerdown modes

RYBY is intended to interface the 28F008SA to asystem microprocessor rising-edge-triggered interruptinput In a multiple-chip memory array externalEPLD logic or an interrupt controller can be used to

combine and prioritize RYBYs into one system in-terrupt (see Figure 4) The system can then using aflash memory activity table set up in RAM poll theindividual 28F008SA Status Registers to determinewhich device has returned ready or read theRYBY inputs directly at the EPLD as shown

Figure 5 provides an alternative method for connectingmultiple RYBYs to one interrupt input The dioderesistor combination converts the 28F008SA fullCMOS output into an open-drain wired-OR equiva-lent Any RYBY at VOL will drive the interruptinput low and this input is pulled high by the resistorswhen all RYBYs are at VOH It is important in adesign like this to use diodes with low forward voltagedrops so that the 28F008SA VOL (045V) plus the di-ode voltage drop is still less than or equal to the desti-

nation input VIH (08V) For the schematic shown inFigure 5 the equation is

VOL a VDIODE e 045 VMAX a 03V e 075V s 08V

Note that should the system connect RYBY to aninterrupt disable that interrupt prior to suspendingerase as RYBY will transition to VOH when thedevice is suspended

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Figure 4 EPLD-Based RYBYImplementation

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Figure 5 Wired-OR RYBYImplementation

23 RP(ResetPowerdown) Input

Deep Powerdown Mode

The RP input when driven to VIL by the system

switches the 28F008SA into a deep powerdown modewith negligable power consumption This feature inte-grates the VCC power FET often used with low powerdesigns Power consumption thru VCC is typically1 mW in deep powerdown mode RP-low deselectsthe memory places output drivers for D0 7 in a high-impedence state and turns off a majority of internalcircuits RYBY is driven to VOH while in deeppowerdown mode Depending on the flexibility desiredsystem designers can choose to put either the entireflash device array into deep powerdown mode or anyindividual components via selective input control The28F008SA requires a wakeup time after RP re-turns to VIH before it can be successfully written(tPHWL) or outputs are valid to read attempts (tPHQV)

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AP-359

Write Protection

Since RP e VIL deselects the 28F008SA this inputcan be used not only as a means of entering deep pow-erdown mode but also as an active-high chip enableto block spurious writes during system power tran-

sitions Figure 6 shows one possible RP implementa-tion controlled by a GPIO line for power managementand by a system POWER GOOD for power sequencingprotection In this design the 5V monitoring circuitbegins functioning at VCC e 1V and will enable thedevice only after VCC transitions above 46V (and sys-tem control signals are therefore stable) As VCCdropsbelow 46V during system powerdown RPprotectionis again activated

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Figure 6 RPGating

Reset Control

RP at VIL resets all internal automation within the28F008SA as part of the deep powerdown processUpon exit from deep powerdown the 28F008SA is re-set to Read Array mode This functionality is idealwhen the 28F008SA is the boot memory for the systemRP active transitions reset the Write Status Machineif system reset occurs during flash memory program orerase and allow successful CPU reboot

24 WE(Write Enable) Input

When flash memory is written the result can rangefrom a 28F008SA that is placed in read intelligentidentifier or read Status Register modes to altera-tion of nonvolatile flash memory contents Systemhardware can prevent spurious writes to flash memoryby application software or an operating system by gat-ing the system WE to flash memory components toenable writes only when desired

Figure 7 shows a simple design that gates WEwith aGPIO line enabling writes to the 28F008SA only whenthe GPIO is a 0 The GPIO is initialized to 1 onsystem powerup and the BIOS a dedicated update soft-ware routine a special keyboard sequence switch onthe back of the system or jumper on the system mother-board can then control the GPIO This circuit ensuresthat flash memory contents are as permanent asROM unless alteration is specifically desired

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Figure 7 WEGating

25 Power Supply Decoupling

Both the VCC and VPP inputs to each 28F008SAshould be decoupled at the package leads to providenoise immunity and supply current for transient cur-rent spikes during read byte write and block erase Ad-ditional bulk capacitance for groups of flash memoriesovercomes voltage slump caused by PC board trace in-ductances Calculations for individual component andbulk capacitors (one per 8 devices) are shown below

Basic Equation

I e C dvdt

Assumptions

I e 35 mA per device (VCC) therefore

I e 175 mA per device input (VCC)

I e 30 mA per device (VPP)

dv e 01V (02V peak-peak)

dt e 20 ns

Per-Component-Input Decoupling Capacitor (VCC)

C e I dtdv e (175 mA c 20 ns)01V e 35 nF

4x margin e 4 c 35 nF e 14 nF

Standard Equivalent e 001 mF

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NOTE

Calculations above assume that each 28F008SA isdriving CMOS inputs (with corresponding high im-pedance and negligible input current requirements) If28F008SA outputs are driving non-CMOS inputslarger per-component capacitance may be needed to

supply current while outputs are switching

Bulk Capacitor (VCC)

C e 10 c (Total of Decoupling Capacitors)

Bulk Capacitor (4 Mbyte array) e 10 c (8 c 001 mF)e 08 mF

Standard Equivalent e 1 mF

Per-Component Decoupling Capacitor (VPP)

C e I dtdv e (30 mA c 20 ns)01V e 6 nF

4x margin e 4 c 6 nF e 24 nF

Standard Equivalent e 0033mF

26 High Speed Design Techniques

The 28F008SAs fast read access and command writespecifications make it a natural choice for high per-formance memory arrays The following tips will opti-mize the memory interface for optimum readwritespeed The common recommendation in all instancescenters around minimizing fanout and capacitive busloading to allow highest switching speed lowest riseand fall times and therefore greatest performance

Minimize address bus loading from the microproc-essor to the memory array Multiple address latchesfeeding subsets of the array speed address input toeach 28F008SA and CE decoding by externallogic

Similarly drive the memory array with multipleOEs and WEs Most EPLD and discrete logictiming is specified at a 30 pF load which equates todriving four 28F008SA inputs at maximum inputcapacitance Anything more than this may severelyimpact the logics propagation delay

Finally remember that each 28F008SA when readdrives not only the system microprocessor or trans-ceiver but also any other flash memory componentsconnected to the common data bus Each 28F008SAdata output is specified at 12 pF and the 28F008SAread timings are tested at either 30 pF or 100 pF ofloading depending on the chosen speed bin

For large flash arrays where sequential data can be dis-tributed on many devices hardware interleaving pro-vides additional performance

27 Example Bus Interfaces

Appendix A shows hardware interface to the In-tel386TMSL PI bus and Appendix B shows interface tothe Intel486TMSX local CPU bus Both interfaces in-corporate techniques described in sections 21 26 ofthis document These designs are intended to be exam-ples which can be modified to suit requirements of theend system

ADDITIONAL INFORMATION

Order Number

28F008SA Datasheet 29042928F008SA-L Datasheet 290435

AP-357 Power Supply Solutions for Flash Memory 292092

AP-364 28F008SA Automation and Algorithms 292099

ER-27 The Intel 28F008SA Flash Memory 294011

ER-28 ETOX-III Flash Memory Technology 294012

REVISION HISTORY

Number Description

-003 Renamed PWDas RPto match JEDEC conventions

Updated Figure 6

Added Reset Control discussion for RP(ResetPowerdown) Input

-004 Minor changes throughout document

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APPENDIX A

Intel386TMSL PI BUS INTERFACE

2920949

NOTEThe DRAM interface is not shown for graphic simplicity

A-1


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APPENDIX BIntel486TM SX LOCAL CPU BUS INTERFACE

29209410

NOTEThe DRAM interface is not shown for graphic simplicity

B-1

intel 28f008-sa interface guide

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