integrated circuit chips manufacturing process & testing

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ATMT 4213 Advanced Materials Testing and Evaluation

1.0 Introduction: What is Semiconductor Device? [1]

Semiconductor devices are electronic components that made by semiconductor

materials. These semiconductor materials have electrical conductivity that behaves

intermediately between a conductor and an insulator. Silicon is an example of

common materials that used for the manufacturing of such devices since it is one of

the most abundant resources in the earth. Generally, there are two types of

semiconductors, which are intrinsic semiconductor and extrinsic semiconductor.

An intrinsic semiconductor is a pure semiconductor without any doping atoms

within its crystal lattice. Hence, the electrical conductivity is much poorer compare to

an extrinsic one. In an intrinsic semiconductor such as silicon, the crystal structure is

covalently bonded due to the sharing and pairing of valence electrons among the

atoms. The absence of “free” or mobile electrons causes it is not able to transmit

electrical current in original states. But when the silicon is exposed to certain external

factors such as temperature and light, the valance electrons will be excited out of the

bonds and causes the creation of holes. Holes are the vacant positions left by the freed

electrons. As a result, the holes and the freed electrons act as charge carriers and are

able to conduct current. There is an energy gap needs to be achieved in order to excite

the electrons and holes.

The electrical conductivity of intrinsic semiconductor can be greatly improved

by the adding of impurities through doping process. This doped semiconductor is also

known as extrinsic semiconductor. The difference in the number of valence electrons

between the doping material, or dopant and host semiconductor will determine the

type of doped semiconductor. If a doped semiconductor contains more holes after

doping, it is called ‘p-type’ and if it contains excess free valence electrons, it is called

‘n-type’. P-type semiconductor can be formed by doping with acceptor atoms such as

Boron whereas N-type is doped with donor atoms such as Phosphorus and Arsenic.

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(a) (b)

Figure 1.0: (a) P-type semiconductor that is formed by the doping of Boron atoms. The Boron

atom creates a hole. (b) N-type semiconductor that is formed by the doping of phosphorus

atoms. The phosphorus atom creates an extra electron.

When a p-type semiconductor region is placed adjacent to an n-type region,

they form a region of contact which is called a p-n junction. A diode is a

semiconductor devices made from a single p-n junction. The diode functions as a two

terminals device that conducts in only single direction. Combinations of such

junctions are used to make transistors and other semiconductor devices whose

electrical behavior can be controlled by appropriate electrical stimuli. These

transistors can be further combined with other active components along with passive

ones on a single chip of silicon to form an integrated circuit (IC). IC is a complex

electronic device design to perform certain functions depending on controlling

signals.

Figure 1.1: (a) Diode (inside the red circle) that mounted on the circuit board; (b)

Transistors in various types and forms; (c) An integrated circuit (IC).

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2.0 Manufacturing Process of Semiconductor Devices

Semiconductor devices consist of two major parts: a tiny and fragile silicon chip (die)

together with a package that intended to protect the internal chip. For an integrated

circuit (IC), diodes and transistors are embedded within the silicon chip. The

manufacturing process of all semiconductor devices is basically almost similar. But a

more complex multi-step processes will be involved if the device is designed for a

higher level of functional purpose such as IC.

Figure 2.0: The structure of a semiconductor device.

The manufacturing flow for a semiconductor device is divided into two

phases, which are front-end manufacturing and back-end manufacturing. In front-end

phase, it involved the wafer fabrication process that is extremely sophisticated and

intrinsic in nature to produce the silicon chip. Afterward, the manufactured silicon

chip will be subjected to wafer probing test to ensure its quality and reliability meets

with the required specification. In back-end phase, good chips (die) are assembled

into package via a high precision and automated process. A final test will be done on

the completed semiconductor device before packaging and shipping to customer. [2]

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Figure 2.1: The manufacturing of a semiconductor device can be divided into frond-end

processing and back-end processing.

2.1 Logic Circuit Design and Photomask Creation [3]

Logic circuit design is a very important part for the manufacturing of semiconductor

devices. It must be done before any manufacturing processes could starts. The

expected functions and performances of device are determined and drawn into a logic

circuit diagram. Stimulations are performed multiple times to test the circuit’s

operation. If there is no any faulty with the operations, the actual layout pattern for the

devices and interconnects is designed by using CAD software. This actual layout is

used to create the mask pattern of devices.

The mask pattern functions as a photomask to transcribe the design onto the

surface of wafer during front-end processing. Photomask is simply a copy of designed

circuit pattern that drawn on a glass plate coated with a metallic film. Light is able to

pass through the glass plate, but the metallic film does not. The circuit pattern is

exposed on the photomask by using a state-of-the-art mask drawing system. Due to

the increasingly high integration and miniaturization of the pattern, the size of the

photomask is usually magnified four to ten times the actual size, depending on the

irradiation equipment.

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Figure 2.2: Photomask is used to transcribe the logic circuit design onto the surface of wafer.

2.2 Front-end Processing [2]

Wafer fabrication is carried out in a wafer fab which is isolated from the outside

environment and contaminants. Wafer fab is a cleanroom that air cleanliness is one

million times better than the air we normally breathe in a city, or some orders of

magnitude better than the air in a heart transplant operating theatre. Silicon chip could

be easily spoiled or failed due to the presence of contaminants such as particles,

metallic impurities, organic contaminants, native oxides and electrostatic discharge.

Silicon substrate (wafer) that produced through wafer preparation will

undergoes a series of multi-step processes which consists of deposition,

photolithography, etching, diffusion and ion implantation. Some of the process is

repeated several times at different stages of process. Each step adds a new layer to the

wafer or modifies existing ones. These layer forms the element of individual

electronic circuits. The order shown in Figure 2.3 does not reflect the real order of

fabrication process. It is depend on the predetermined logic circuit design of silicon

chip. But the process flow chart points out the overall major steps involved in the

manufacturing of a die.

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Figure 2.3: The overall flow process of frond-end processing to manufacture the die on

wafer.

2.2.1 Wafer Preparation [4]

Wafer is a thin, circular slice of semiconductor material that made from silicon ingot

with purity as high as 99.999999999% (eleven-nine) through either the Czochralski

(CZ) or the Float Zone (FZ) method. [3] It is a single-crystal silicon substrate with

near-perfect crystalline properties where the logic circuit will build within the silicon

lattice. Quartzite is a type of sand that used as the raw material for wafers. The sand

will undergoes a complicated refining process to become electronic grade polysilicon

(EGS). [5] In Czochralski method, the EGS (silicon chunks) are loaded and heated in a

crucible of furnace at temperature about 1600°C. Once the chunks of silicon are

melted, a seed crystal will be lowered into the furnace until it touches the melt. The

seed will begin to rotate and slowly retracted by CZ crystal puller from the furnace at

a controlled rate. A cylindrical, single crystal silicon ingot is grown from the

withdrawal process.

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Figure 2.4: Process of withdrawing the single-crystal silicon ingot from furnace.

The ingots will subject to a series of routine evaluation to ensure they meet the

quality requirements. It is then ground using diamond wheels to make it a perfect

cylinder with the right diameter. An etching process is done on the ingots to remove

the mechanical imperfections left by the grinding process. The cylindrical ingot will

undergoes another round of grinding to produce one or more ‘flat’ on its surface.

Once these completed, the ingots are sliced into thin wafer with a diamond saw, each

of which will be subjected to further etching to remove damage and contamination,

followed by polishing to create mirror-finish surface on the wafer. The wafer is ready

to be used as the substrate for production of chip. [6]

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Figure 2.5: The ingot is sliced into thin wafer and mirror-finished on one side of its surface.

2.2.2 Deposition

Deposition is a process to introduce a new layer of film on the silicon substrate. It

could be done through three common methods which include Thermal Growing,

Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD).

Thermal growing is a process that involved the growth of oxide layer on a

wafer by providing high purity oxygen in an elevated temperature environment. It is a

chemical reaction between silicon and oxygen that occur in a furnace. A layer of

silicon dioxide, SiO2 will be formed and adhered onto the wafer surface by the

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consumption of original wafer. The silicon dioxide is created with the purpose such as

acts as a protection layer of the device from scratches and contaminations, field

isolation (surface passivation), gate dielectric material, doping barrier and deposited

dielectric layer between metal conductor layers. [7]

Figure 2.6: The growth of oxide layer on the wafer by thermal growing process.

Chemical Vapor Deposition is a process that forms a non-volatile solid film on

a substrate from the reaction of vapor phase chemical reactants containing the right

constituents. The deposition process is done in a reaction chamber in which the

reactant gases are introduced to decompose and react with the substrate to form film.

This process is frequently used to produce amorphous and polycrystalline thin films,

deposition of silicon nitride and SiO2, and growing of single-crystal silicon epitaxial

layers. [8] Epitaxial layer is a deposited film that has the same material as the substrate,

in which functions to minimize latch-up problem as device geometric continue to

shrink and better control of doping concentrations of the devices. [7]

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Figure 2.7: Chemical Vapour Deposition (CVD) is used to produce new layer such as

polycrystalline thin films, silicon nitride, SiO2, and epitaxial layer on the wafer.

Physical Vapor Deposition normally is used in the form of sputtering to

deposit a thin film of conductive metal on the wafer. Actually this is a metallization

process that intended for creating a metal layer to electrically interconnect the various

device structures fabricated on the silicon substrate. The metal layer functions as a

bridge that completes the electric circuit. Thin-film aluminium is the most widely

used material for metallization, with the other two being silicon and SiO2. Sputtering

begins with the generation of high energy ions that used to bombard a target (source

of material for deposition). The ions will sputter or eject atoms from the target. Once

the sputtered atoms reach the substrate, they condense and from a thin metal film over

the substrate. [9]

Figure 2.8: Physical Vapour Deposition (PVD) in the form of sputtering is used to carry out

metallization process on the wafer.

2.2.3 Photolithography

Photolithography is a process that defined the pattern of depositing layers and the

doping region on the substrate. The fabrication of circuit on silicon wafer requires

several different layers. Each of the layers has different pattern where the deposition

is done one at the time on that particular surface. The doping of active regions is

carried out in very controlled amount over tiny regions of precise areas. [10]

In order to create the predetermined pattern on a layer, a layer of photoresist

material is spin-coated on the surface of the wafer. Photomask is placed over the

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photoresist-coated wafer and adjustment is made between them until correct. A

radiation device called stepper is used to radiate UV light through the photomask on

the coated surface of wafer. The exposure causes the designed pattern on photomask

is transcribed onto the wafer surface. Since the photomask is four to ten times larger

than the actual sizes of the circuit, the stepper lens must be adjust to ¼ to 1/10

magnification before being projected onto the wafer. The radiation of UV light causes

a chemical changes to the photoresist material. [3]

Figure 2.9: Schematic diagram of photolithography process.

After exposure, the photoresist layer is subjected to development that destroys

unwanted areas of the photoresist layer, exposing the corresponding areas of the

underlying layer. Depending on the resist type, the development stage may destroy

either the exposed or unexposed areas. The areas with no resist material left on top of

them are then subjected to additive or subtractive processes, allowing the selective

deposition or removal of material on the substrate. The unwanted areas in the

photoresist are dissolved by the developer during development. [10] There are two type

of possibility for the resulting photoresist layer after development, which are positive

photoresist and negative photoresist. Positive photoresist is where the image formed

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in the resist is the same pattern as the photomask whereas negative photoresist

produced a resist image which is negative of the pattern found on the photomask. [7]

Figure 2.10: Two type of photoresist layer is produced after development: positive photoresist

and negative photoresist.

2.2.4 Etching

Etching is the process of removing regions of the underlying material that are no

longer protected by the photoresist after development. It is done by using either

chemical or physical means. There are two types of etching process which are dry

etch and wet etch.

Dry etch exposes the wafer to a plasma (ionized gas) that interacts physically

or chemically (or both) to remove the surface material. It is normally used to deal with

metallic films. Wet etch uses liquid chemicals to chemically remove the wafer surface

material. Wet etch normally is used for oxide films. [7]

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When an etching process is proceed in all directions at the same rate, the

etching process is said to be isotropic. Inversely, if it is proceeds in only one direction,

it is completely anisotropic. Wet etching is generally isotropic whereas dry etching

process is anisotropic in nature. [10]

Figure 2.10: Target layer is removed through etching process.

2.2.5 Diffusion and Ion Implantation

Diffusion and ion implantation are the two major processes where dopants are

introduced into silicon lattice. Phosphorus, Arsenic (N-type) and Boron (P-type) are

the most frequently used dopants in the semiconductor industry.

Diffusion is the movement of one material through another from a region of

relatively higher concentration into a region of lower concentration. Normally, the

dopant is introduced into the silicon lattice by thermal diffusion. There are three steps

involved in thermal diffusion: predeposition, drive in and activation. [7] In

predeposition stages, the dopant gas is arrives at the surface of substrate where the

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concentration gradient of dopant is remains between them. After certain times, the

dopant gases “drive in” into the silicon lattice with the aid of thermal energy. The

concentration gradient of dopant at the surface of the substrate is decreases with time.

The used of thermal diffusion as the doping method has gradually declined nowadays

due to its poor control of doping concentration and depth. [11]

Figure 2.11: Dopant is introduced into silicon substrate through thermal diffusion.

Ion implantation method has steadily replaced thermal diffusion method due to

its superior advantages to doping the silicon substrate. The process is simpler but

more costly as the ion implanters are quite expensive. During ion implantation,

doping atoms are vaporized and accelerated toward the silicon substrate. These high-

energy atoms enter the crystal lattice and lose their energy by colliding with some

silicon atoms before finally coming to rest at some depth. Adjustment on the

acceleration energy could control the average depth of depositing dopants. [12]

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Figure 2.12: Schematic diagram of ion implantation process.

But the introduction of dopant into the lattice could cause the damage to the

lattice. The damage caused by atomic collisions or displacement by both methods

changes the electrical characteristics of the target. Many target atoms are displaced,

creating deep electron and hole traps which capture mobile carriers and increase

resistivity. Annealing is therefore needed to repair the lattice damage and put dopant

atoms in substitutional sites where they can be electrically active again. This is

known as activation where the the crystal lattice disturbances are repaired by making

the dopant as the part of silicon substrate.

Figure 2.13: Annealing is done on wafer to repair the silicon lattice which is damaged by

doping process.

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2.2.6 Passivation

Passivation is a process that involved the deposition of final passivating layer on top

of the wafer to protect the completed chip (die) from mechanical damage and

corrosion. The final layer often is made up of an amorphous insulating material or

glass. Silicon nitride (Si3N4) is one of the common passivating materials because of its

high resistant to diffusion, which is almost impenetrable to moisture and ionic

contaminants. It can be easily deposited with a low residual compressive stress that

making it less prone to cracking. Its interfacing with the underlying metal layers is

also very conformal. Besides that, it can be prepared with very low pinhole density.

Silicon nitride can be deposited using plasma-enhanced chemical vapour deposition

(PECVD) or low-pressure chemical vapour deposition (LPCVD). The overall front-

end processing can be said is totally completed after passivation. [13]

2.2.7 Wafer Probing

Wafer probing is carried out to verify the functionality of chip by performing

thousands of electrical tests. This is done automatically using a wafer probing system,

which the wafer is holds on a stable platform and a set of precision point needles are

drop on the designated probe pads on the die. The probe system is usually connected

to an automatic test equipment (ATE) using special interfacing hardware. Probing is

done on one die at a time. The bad dies are automatically marked with a black dot so

they can be separated from the good die after wafer is cut. Failure analysis is carried

out by the engineer to examine what went wrong with those non-working dies

according to the record obtained. The percentage of good die on an individual wafer is

called as yield. [2]

Figure 2.14: Wafer probing is done to filter out

the bad dies from the complete fabricated wafer.

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2.3 Back-end Processing

Back-end processing is a process that putting the die inside a package as a more

practical and convenient way to deal with external environment. The whole process is

known as die packaging assembly. Nowadays, the trend of assembly technology has

moves toward in developing smaller, cheaper, more reliable and more environmental

friendly packages. The packages provide the die with a structure to operate in and

help in optimize the operation of device. It also protects the die from the environment

while connecting it to the outside world. The back-end processing basically consists

of wafer backgrind, die preparation, die attach, wire bonding and encapsulation.

Figure 2.15: The overall flow process of back-end processing to assembly the dies into

individual package.

2.3.1 Wafer Backgrind

As the technology trend has made the packages thinner and thinner, wafer backgrind

sometimes become indispensable. Wafer backgrind is a process of grinding the

backside of the wafer to the correct wafer thickness prior to assembly. Most package

types in the semiconductor industry today require a wafer thickness ranging from

eight mils to twenty mils. This process is not always been necessary.

Wafers normally undergo a cleaning process and surface lamination process

before the actual grinding process. Surface lamination is a protective tape that applied

over the surface of wafer to protect itself from mechanical damage and contamination

during backgrind. The surface laminated wafer is loaded into cassettes that will go

into the cassettes holder of backgrinding machine. The wafer is picked up by the

machine from its backside (untaped side) with a robotic arm to position the wafer for

backgrinding. The backgrinding process is automatically accomplished with a precise

parameter by a grinding wheel. D/I water is used continuously to remove the debris

produced while backgrinding. The wafer is returned to the cassette after the process

had been completed. The cycle is repeated for the next wafer. [14]

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(a) (b)

Figure 2.16: (a) The wafer is surface laminated by a protective film prior to backgrind

process. (b) Wafer is being backgrinding by the machine.

2.3.2 Die preparation

Die preparation is a process by which the wafer is cut into individual die in

preparation for assembly. Die preparation consists of two major steps, namely,

wafer mounting and wafer sawing.

Wafer mounting is done to provide the support to the wafer to facilitate the

processing of wafer during sawing through die attach. During wafer mounting, the

wafer frame and wafer are loaded subsequently on the machine. The wafer is

mounted on the frames by dicing tape (wafer film). Excess tape is cut off and the

mounted wafer is unloaded after completion of mounting. Dicing tape is just a PVC

sheet with synthetic adhesive on one side to hold the wafer frame and wafer

together. [15]

Figure 2.17: Wafer is mounted on the frames by dicing tape (wafer film).

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Wafer sawing is then carried out to cut the wafer into individual die for

package assembly. The frame-mounted wafer is automatically aligned into position

for cutting. The wafer is cut thru its thickness based on the programmed die

dimensions using a resin bonded diamond wheel rotating at very high rpm. The

wafer goes through a cleaning process using high pressure DI water sprayed on the

rotating workpiece and then dried by air-blowing. [15]

Figure 2.18: Wafer is cut into individual die by the diamond wheel of sawing machine.

2.3.3 Die Attach

Die attach is a process of attaching the chip to a platform called the lead frame. A lead

frame consists of a die pad or cavity for the attachment of the chip and leads for the

connections of chip terminals. There are two common methods for die attach, which

are adhesive die attach and eutectic die attach. Both of these process use special die

attach equipment and die attach tools to attach the die.

2.3.3.1 Adhesive Die Attach

In adhesive die attach, adhesives such as such as polyimide, epoxy and silver-filled

glass are used as die attaching material. The adhesive is first dispensed in controlled

amounts on the die pad or cavity. The die for mounting is then ejected from the wafer

by one or more ejector needles. While being ejected, the die is transferred from the

wafer tape and positioned on the adhesive by a pick-and-place tool (collet). [16]

http://www.siliconfareast.com/datools.htm

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2.3.3.2 Eutectic Die Attach

In eutectic die attach, eutectic alloy is used to attach the die to the cavity. A eutectic

alloy is an alloy with the lowest melting point possible for all the phases within the

alloy coexist. This method is commonly employed in hermetic packages. The Au-Si

eutectic alloy is the most commonly used die attach alloy in semiconductor

packaging.

For Au-Si eutectic alloy, the package is subjected to heating up to a

temperature about 400°C. This is simply because the eutectic temperature for Au-Si

alloy with 2.85% Si is about 363°C. Thus, the die attach temperature must be

reasonably higher than this temperature in order to achieve eutectic melting point. A

gold preform is placed on the top of the cavity during the heating of package. The die

is attached over this gold platform. As the temperature rises, there is more Si diffuse

into the gold preform. The Si-to-Au ratio of the alloy increases until such time

eutectic ratio is achieved. The alloy is melted and attached the die to the cavity once

the eutectic temperature had been reached.

Sometimes, the die is scrubbed into the eutectic alloy for even distribution of

die attach alloy. Eventually the diffusion of silicon atoms into the gold preform

exceeds the eutectic limit, and the die attach alloy begins to solidify once again. The

package is then allowed to cool down to completely solidify the eutectic alloy and

complete the die attaching process. [16]

2.3.4 Wire Bonding

Wire bonding is the process of providing electrical connection between the silicon

chip terminals and the external leads of lead frames using very fine bonding wires.

Gold is the most common material that used in wire binding.

Figure 2.19: Schematic diagram of wire bonding process.

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During wire bonding, a gold ball is formed by the melting the end of wire by a

bonding tool known as a capillary. The free-air ball is brought into contact with the

bond pad of the chip. An initial metallurgical weld is formed between the ball and the

bond pad. The application of pressure, heat, and ultrasonic forces in adequate

amounts for a specific period causes the ball bond itself deformed into the final

shape. The wire is then run to the corresponding finger of lead frame by forming a

gradual arc between the bond pad and leadfinger. Similar step is done on the wire to

form the fishtail bond (second bond) with the leadfinger. The wire bonding machine

breaks the wire by clamping the wire and raising the capillary in preparation for the

next wire bonding cycle. [17]

(a) (b) (c) (d)

Figure 2.20: (a) Needle lowered. (b)Welding the ball to bond pad. (c) Welding the wire to leadfinger. (d) Cutting the wire.

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2.3.5 Encapsulation

Encapsulation is the process of moulding the die and the cavity of the lead frame

together with moulding resin for protection. Transfer moulding is one of the most

widely used moulding process in semiconductor industry due to its capability to

mould small parts with complex features.

In this process, the moulding compound is preheated before loading it into the

moulding chamber. After preheating, the hydraulic plunger is rotated to force the

moulding compound moving into the pot. The moulding compound becomes fluid

gradually as it reaching the melting temperature. The fluid (molten resin) is forced

into the runners of mould chase by the continuously rotation of plunger. The runners

serve as canals where the molten resin travels until it the cavities, which contain lead

frames for encapsulation. Once the encapsulation is done, the excess flashes from the

package of the newly moulded parts are trimmed. The tie bars that connecting the

individual units to the lead frame are cut so that each unit is separated into individual

packages. The leads protruding from the package are formed into the correct shape

and position. [18]

Figure 2.21: The tie bars are cut to separate the each unit into individual packages.

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2.3.6 Marking and Lead Finish

Marking is the process of putting identification, traceability and distinguishing mark

on the package of semiconductor device. Information such as device name, company

logo, date code and lot id are usually marked on the package. The marking process

could be done by either ink marking or laser marking method. [3]

Lead finish is the process of applying a coat of metal over the leads of

semiconductor device. The coating layer is used to protect the leads from corrosion

and abrasion. At the same time, it also improves the solderability and the appearances

of the leads. The coating is applied on the device through plating or coating

techniques. [3]

Figure 2.22: Information such as device name, company logo, date code, and lot id is marked on the surface of package.

2.3.7 Final Inspection and Packing

Final inspection is done on the completed semiconductor devices in the way of

sampling before shipping to customer. Visual inspection is carried out to check for

scratches and stains, dimensions and shapes of leads and prints. Inspection on the

electrical characteristic of the devices is also done to ensure the devices fulfil the

quality requirement and safety to consumer. [3]

The semiconductor devices that passed the quality and reliability checks are

stored in trays and magazines. All the devices are packed by placing the cushioning

materials between external packages to prevent degradation of quality from impacts

while in transport. The outer boxes are labelled with the company’s name and

quantity of the product, and then shipped. [3]

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3.0 Reliability of Semiconductor Devices [19]

Reliability is defined as the ability of a semiconductor device to conform its electrical

and visual/mechanical specifications over a specified period of time under specified

conditions at a specified confidence level. Reliability tests are used as tool to achieve

continuous improvement of reliability throughout the entire semiconductor device life

cycle, which includes from design, to manufacturing, to usage and until after its

failure. Reliability is vital for semiconductor devices as any faulty in the device could

endangers the life of consumer. This is true especially the life of mankind is greatly

relates to semiconductor devices nowadays. Reliability tests could be divided into two

major levels, which are wafer level and packaging level.

Wafer level reliability testing is carried after the complete fabrication of dies

on wafer. Semiconductor industries today are more focused on carried out testing

within this level since any faulty on the chip could manifest at the end of package

level. It is good to identify and correct all the reliability issues of chips in earlier

stages if possible at all. In wafer level, the reliability tests are mainly aimed to

separate out all the bad dies from the manufactured wafer. This could ensure that the

further package assembly process afterward is done only on known good die (KGD).

This will minimize the waste of manufacturing cost on the faulty chips during

package assembly.

Package level reliability testing refers to the assessment of the overall

reliability of the device in packaged form. In this level, the package samples are tested

in different stress conditions to determine their maximum capability limits to

withstand the stress without fails. Since package level tests are destructive in nature,

only a sample population is used for the assessment of reliability. The reliability for

the rest of population is just control by the mean of statistical control.

Semiconductor devices are produced in mass volume in order to gain the

advantages from beneficial economic scale. But this could results in a large amounts

of reliability tests and time consuming in nature if it is done ones by ones. Hence, the

reliability tests are carried out with the aid of automated test equipment (ATE). ATE

is an apparatus that performs test (electrical characteristic test) on a device, known as

Device Under Test (DUT) by using automation to quickly perform measurement and

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evaluate the test results. Different devices require different levels of sophistication in

ATE equipment.

ATE assist the testing based on written software called test program. The test

program consists of a series of subroutines known as test blocks. Each test block

represents a corresponding device parameter to test under specific conditions. The

device under test (DUT) is subjected to specific excitation and the resulting response

of the device is measured. The measurement is used to compare with the pass/fail

limits that set in the test program. Once the device tested, the handler of ATE will

classify the device either as a reject or as a good unit.

3.1 Reliability Testing

Reliability testing could be categorized as two major types which are environmental

type and endurance type.

For environmental types, the purpose of testing is to check the reliability of the

semiconductor device with respect to different service environment. In real field

operation, semiconductor devices may expose to extreme environmental changes or

sudden impact. Hence, stimulation on devices is done by modification of

environmental factors such as temperature, humidity, contamination level, etc. The

main purpose of this type of testing is to ensure that the semiconductor devices are

capable to perform and safe to be used in the intended environmental conditions. The

examples of this type of testing are Thermal Shock Test, Thermal Cycling Test,

Mechanical Shock Test and Vibration Test.

For endurance types, the purpose of testing is to find out to what extend a

device would fails when it is over serviced. Sometimes, semiconductor devices might

operate at a condition which is exceeded their stated limits due to improper usage by

consumer. Besides that, there is also the possibility where deterioration of device

occurs after services over a period of time in some extreme environment. This causes

the original endurance limit of device is decreases due to the deterioration. Hence, it

is important to know the maximum operating limits of the devices. This is done by

accelerating the device to reach its failure. The examples of this type of testing are

Burn-in Test, THB test, HAST and High Temperature Storage.

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3.1.1 Temperature Cycling Test (TCT) and Thermal Shock Test (TST) [20] [21]

Semiconductor devices are very prone to fail when subject to sudden temperature

changes during their real-life application. Hence, it is important to ensure their

reliability in such environment. There are two testing method that being employed in

semiconductor industry for this purpose, which are Temperature Cycling Test (TCT)

and Thermal Shock Test (TST).

TCT is performed to determine the ability of devices to resist extremely low

and extremely high temperatures, as well as their ability to withstand cyclical

exposures to these temperature extremes. It is a testing that accelerates fatigue failure.

During TCT, the sample is firstly exposes under specified low (or high) temperature;

follow by subjects the same unit to the specified high (or low) temperature for a

specified number of cycles using Temperature Cycle Chamber.

TST is a test that closely resembles TCT for some aspects but it is more on

determines the resistance of the devices to sudden temperature changes in a much

shorter period of time. In this test, the sample undergoes a specified number of cycles

that starts at ambient temperature. The sample is then exposed to an extremely low (or

high) temperature and, within a short period of time, exposed to an extremely high (or

low) temperature, before going back to ambient temperature.

After final cycle, external visual examination is carried out in TCT and TST.

The inspection on the case, leads and seals should be performed at a magnification of

10 X to 20 X. The marking should also be inspected at a magnification not greater

than 3 X. If there is any illegal mark and/or any evidence of damage to the case, lead,

or seals after stress test, the sample is considered as failure. For both of the test,

electrical testing is done on the sample via ATE in order to detect electrical failures

accelerated by temperature cycle. Generally, failure mechanisms accelerated by both

tests include die cracking, package cracking, neck/heel/wire breaks, and bond lifting.

Failure acceleration due to Thermal Shock and Temp Cycling depends on the

following factors:

difference between the high and low temperatures used;

transfer time between the two temperatures;

dwell times at the extreme temperatures.

http://www.siliconfareast.com/TCT.htm

27


For reliability testing or qualification of new devices, 1000 temp cycles are

usually performed, with intermediate visual inspection and electrical testing read

points at 200X and 500X.

(a) (b)

Figure 3.0: (a) Temperature Cycle Machine. (b)Thermal Shock Chamber.

28


The example of Temperature Cycle Test specification that used in semiconductor

industry:

M il-Std-883, Method 1010 Specs : Temperature Cycle Test

Total Transfer Time <= 1 minute

Total Dwell Time >= 10 minutes

Specified Temp reached in <= 15 minutes

Must be conducted for a minimum of 10 cycles

Condition Low Temp (°C) High Temp (°C)

A -55 (+0/-10) 85 (+10,-0)

B -55 (+0/-10) 125 (+15,-0)

C -65 (+0/-10) 150 (+15,-0)

D -65 (+0/-10) 200 (+15,-0)

E -65 (+0/-10) 300 (+15,-0)

F -65 (+0/-10) 175 (+15,-0)

Table 3.1: Mil-Std-883 Method 1010 Temp Cycle Test Conditions

JEDEC JESD22-A104 Specs : Temperature Cycle Test

Total Transfer Time <= 1 minute

Total Dwell Time >= 10 minutes

Specified Temp reached in <= 15 minutes

Recommended for lot acceptance screen : 10 cycles

Recommended for qualification : 1000 cycles


A -55 (+0/-10) 85 (+10,-0)

B -55 (+0/-10) 125 (+10,-0)

C -65 (+0/-10) 150 (+10,-0)

D -65 (+0/-10) 200 (+10,-0)

F -65 (+0/-10) 175 (+10,-0)

G -40 (+0/-10) 125 (+10,-0)

H -55 (+0/-10) 150 (+10,-0)

Table 3.2: JEDEC JESD22-A104 Specs Temp Cycle Test Conditions

29


The example of Temperature Shock Test specification that used in semiconductor

industry:

M il-Std-883, Method 1011 Specs: Thermal Shock Test

Total Transfer Time < 10 seconds

Total Dwell Time > 2 minutes

Specified Temp reached in < 5 minutes



A -0 (+2/-10) 100 (+10,-2)

B -55 (+0/-10) 125 (+10,-0)

C -65 (+0/-10) 150 (+10,-0)

Table 3.3: Mil-Std-883 Method 1011 Thermal Shock Test Conditions

JEDEC JESD22-A106 Specs: Thermal Shock Test

Total Transfer Time < 10 seconds

Total Dwell Time > 2 minutes

Specified Temp reached in < 5 minutes



A -40 (+0/-30) 85 (+10/-0)

B -0 (+2/-10) 100 (+10,-2)

C -55 (+0,-10) 125 (+10,-0)

D -65 (+0,-10) 150 (+10,-0)

Table 3.4: Mil-Std-883 Method 1011 Thermal Shock Test Conditions

3.1.2 Mechanical Shock Test [22]

30


Mechanical Shock Test is a test performed to determine the ability of semiconductor

devices to withstand moderately severe shocks. The sources of shock may come from

suddenly applied forces or abrupt changes in motion encountered during mishandling,

improper transportation, or field operation. The devices might degrade in performance

or even get damage permanently as the result of the shocks. If the shock pulses are

repetitive in nature, it can also cause the damage on device that is similar to those

caused by extreme vibration.

In this test, the mechanical shock testing machine must be mounted on a

sturdy and leveled surface. The sample must be rigidly mounted or restrained by its

case or body, with ample protection for the leads. The machine is able to provide

shock pulses of 500 to 30,000 g (peak), with the pulse duration ranging from 0.1 to 1

millisecond, to the body of the device package. The acceleration pulse applied

normally is a half sine wave with a distortion not exceeding +/-20% of the specified

peak acceleration. The measurement is taken by a transducer and optional electronic

filter whose cut-off frequency is at least 5 times the fundamental frequency of the

shock pulse. The pulse width is measured between the 10% point of the peak

acceleration during rise time and the 10% point during decay time. The pulse widths

have a tolerance of whichever is greater between +/-0.1 milliseconds or +/-30% of the

specified width.

After the mechanical shock test has been completed, external visual inspection

of the case, leads, and seals is performed at a magnification of 10 X to 20 X. The

marking is also inspected with or without magnification, but with the magnification

not greater than 3 X. If any illegible mark and/or any evidence of damage to the case,

leads, or seals after the stress test are identified, the device is considered a failure.

31


The example of Mechanic Shock testing specification that used in semiconductor

industry:

Mil-Std-883 Method 2002: Mechanic Shock Test

Test Condition g Level (peak) Pulse Duration (ms)

A 500 1

B 1,500 0.5

C 3,000 0.3

D 5,000 0.3

E 10,000 0.2

F 20,000 0.2

G 30,000 0.12

Table 3.5: Mil-Std-883 Method 2002 Mechanical Shock Testing Test Conditions

32


3.1.3 Vibration Tests [23]

Vibration test are tests performed to determine the effects of mechanical vibration

within a specified frequency range on semiconductor devices. Basically, there are

two different types of vibration tests, which are vibration fatigue test and variable

frequency vibration test. Both of them are similar in many aspects, but each of them

is intended to reveal different types of vibration-related failures.

For vibration fatigue test, the sample is subjected to sustained vibration within

specified levels. There is optical and electrical equipment that used to perform post-

test measurements. During the test, the sample is fixed on the vibration platform with

its lead adequately secured. The sample is then subjected to a simple harmonic

vibration that a constant amplitude having a peak acceleration corresponding to the

specified test condition. The vibration is performed for minimum of 32+/- 8 hours in

each of X-, Y- and Z- orientations, for a total of 96 hours minimum.

For variable frequency variation test, the sample is subjected to variable

frequency vibration at specified levels. It is same as vibration fatigue test in which

there is also optical and electrical equipment to perform the post-test measurements.

During the test, the sample is firmly fastened on the vibration platform with its leads

adequately secured. The sample is then subjected to a simple harmonic vibration that

has either peak-to-peak amplitude of 0.06 inch +/- 10% or a peak acceleration of the

specified test condition. The vibration frequency is varied approximately

logarithmically between 20 and 2,000 Hz. The entire frequency range of 20-2000 Hz

and the return to 20 Hz must be traversed in not less than 4 minutes. This cycle is

performed 4 times in each of the orientations X, Y, and Z, for a total of 12 times.

Once the vibration test has been completed, external visual inspection of the

case, leads, and seals is performed at the magnification of 10 X to 20 X. The marking

is also inspected with or without magnification, but with the magnification not

greater than 3 X. If there is any illegible mark and/or any evidence of damage to the

case, leads, or seals after the stress test, the device is considered as a failure.

33


The example of Vibration testing specification that used in semiconductor

industry:

Mil-Std-883 Method 2005: Vibration Fatigue Test

Test Condition Stress Level (g)

A 20

B 50

C 70

Table 3.6: Mil-Std-883 Method 2005 Vibration Fatigue Testing Test Conditions

Mil-Std-883 Method 2007 : Variable Frequency Vibration Test

Test Condition Stress Level

(g)

A 20

B 50

C 70

Table 3.7: Mil-Std-883 Method 2007 Variable Frequency Vibration Testing Test

Conditions

34


3.1.4 Burn-in Test [24]

Burn-in test is an electrical test that accelerates the electrical failure of a device

through the application of voltage and temperature under over range condition. The

electrical excitation applied during burn-in may mirror the worst case bias that the

device will be subjected to in the course of its usable life. Thus, burn-in essentially

stimulates the operating life of the device. Depending on the burn-in duration used,

the reliability information obtained may pertain to the device’s early life or its wear-

out.

Burn-in is usually carried out by applying the electrical excitation to the

sample at temperature about 125°C. During the testing, the samples are loaded into

the burn-in boards. These burn-in boards are then inserted into the burn-in oven in

which the samples are supplied with necessary voltages while maintaining the

temperature at 125°C. The electrical bias applied may either be static or dynamic,

depending on the failure mechanism being accelerated.

(a) (b)

Figure 3.1: (a) Burn-in boards. (b)Burn-in ovens.

The operating life cycle distribution of devices may be modeled as a bathtub

curve. The bath tub curve shows that the highest failure rates experienced by a

population of devices occur during the early life and during the wear-out period of the

life cycle. In the region between the early life and wear-out stages, the device seldom

fails and could performed well over a long period. Thus, burn-in test is useful tool to

identify the operating behaviour of device over a period.

35


Figure 3.2: Reliability bathtub curve of a device.

Early Life Failure (ELF) is a type of burn-in test that perform to screen out

potential early life failures. Inversely, High Temperature Operating Life (HTOL) and

Low Temperature Operating Life (LTOL) is burn-in test that identify the reliability of

the samples in their wear-out phase.

3.1.4.1 Early Life Failure (ELF) [24]

Early Life Failure is a burn-in test which accelerates possible early life failure of

devices during production level. It is conducted for duration of 168 hours or less, and

normally for only 48 hours. If the sample shows early life failures during the test, this

means that these units of product will fail prematurely when they were used in their

normal operation.

36


3.1.4.2 High Temperature/ Low Temperature Operating Life [25] [26]

High Temperature/Low Temperature Operating Life is performed to determine the

reliability of devices when subjecting to a specified bias (electrical stressing) for

specified amount of time and at a specified temperature. If it is refer to HTOL, the test

will conducted in a high temperature conditions whereas LTOL is done at low

temperature conditions but not exceeding the maximum limits of -10°C unless

otherwise specified. Actually, HTOL and LTOL are just essentially a long term burn-

in of sample that is carried in a burn-in oven capable of operating continuously over

long durations. Both of them are usually conducted for duration of 1000 hours, with

intermediate reading of testing is taken at 168 hour and 500 hour.

There are several requirements need to take care when biasing the sample

during the testing. The sample cannot be electrically overstressed and exceed the

datasheet limits of manufacturer. The bias must also be continuous, and should only

be interrupted when taking the reading of testing.

This test is more concerned with acceleration of wear-out failures in the

samples. This is the reason where the test is required long durations of testing in order

to assure that results are not due to early life failures.

Sometimes, the test duration may be decreased by increasing the ambient

temperature for HTOL and decreasing the temperature for LTOL. Unless otherwise

specified, all intermediate and end-point electrical tests must be performed on the

parts within 96 hours (24 hours for Ta>=175 ° C) after removal of sample from the

specified burn-in conditions. If not specified, an intermediate electrical testing shall

be performed after 168 (+72,-0) hours and after 504 (+168,-0) hours.

37


The example of Burn-in test specification that used in semiconductor industry:

Mil Std 883 , Method 1005 Specs: HTOL generally 1000 hours min. at 125 °C max. rated Tc or Ta < 200 ° C (Class B) max. rated Tc or Ta < 175 °C (Class S) Condition A : steady-state, reverse bias Condition B : steady-state, forward bias Condition C : steady-state, power/reverse bias Condition D : steady-state, parallel excitation Condition E : steady-state, ring oscillator Condition F : steady-state, temp.-accelerated

http://www.siliconfareast.com/milmethods.htm

38


3.1.5 Temperature, Humidity, Bias (THB) Test [27]

Temperature, Humidity, Bias (THB) testing is a reliability test designed to accelerate

metal corrosion, especially the metallization that done on the die surface of the

device.

When there is the present of contaminants within the device, temperature and

humidity of surrounding environment could easily promote the deterioration of metal

layer of the die. Besides that, bias that is applied to the device also could provide the

potential difference needed to trigger the corrosion process. The potential difference

supplies the energy required to drive mobile contaminants to area of concentration in

the die.

THB testing is conducted with electrical bias at 85°C with room humidity

(RH) of 85% for duration of 1000 hour. The bias applied is actually designed to

stimulate the bias conditions of the device in its real-life application. This is to

maximize the variations in the potential levels of the different metallization areas on

the die as much as possible. The intermediate readpoints at 48H, 96H, 168H and

500H are often used in this test.

Figure 3.3: Temperature/Humidity Chambers

Normally, preconditioning is needed to be done before THB test, especially

for surface mounted devices. Surface mounted device is a semiconductor device in

which the electronic circuits are constructed by mounting the units directly onto the

surface of printed circuit boards (PCB). The purpose of preconditioning is just to

stimulate the board mounting/soldering process that a unit undergoes before they used

in the field.

39


During preconditioning, the unit is exposed to thermally stressful conditions

that similar to the mounting/soldering process of unit on PCB. If the sample is

subjected to the THB test without preconditioning, it just likes testing the sample that

has not been mounted on the board. Thus, preconditioning is important to reflect the

actual use condition of the unit.

Preconditioning generally consists of three distinct steps. The sample is firstly

baked to drive away all the internal moisture within the samples. After that, the

sample is subjected to temperature or humidity soak to introduce controlled amounts

of moisture into the package. Lastly, the sample is undergoes some form of thermal

shock that stimulates the board mounting/soldering process itself.

The main disadvantage of THB is its long duration, necessitating weeks before

useable data area obtained. Hence, an alternative test called Highly Accelerated Stress

Test (HAST) has gained increasing popularity to replace THB test in semiconductor

industry.

40


3.1.6 Highly Accelerated Stress Test (HAST) [28]

Highly Accelerated test is a shorter alternative to THB testing. It employed more

severe stress condition in which able to complete within 96-100 hours instead of 1000

hours in THB test. This enables the testing results could be obtained is a much faster

period. HAST is also a testing that accelerates corrosion like THB test, particularly

that of the die metal lines and thin film resistors. The testing procedures of HAST is

actually almost similar to THB testing where it required preconditioning before the

testing. The only difference is that it is conducted with electrical bias at 130°C with

room humidity (RH) of 85% for duration of 96-100 hours.

Electrical bias during HAST stressing must be defined based on the following

guidelines:

Power dissipation must be minimized to ensure that moisture is always present at

the die surface;

Alternate pins must be subjected to opposite bias (low voltage versus high

voltage) as much as possible;

Potential differences between the various metallization areas on the die must be

maximized;

The operating voltage range for the device must also be maximized, as long as the

power dissipation is kept under control.

The sample of HAST stressing are loaded into HAST boards before loading

into the HAST chamber. HAST boards are relatively expensive equipment that are

able to withstand the severe test conditions of HAST. The HAST boards are then

inserted into board racks inside the chamber of the HAST system.

(a) (b)

http://www.universalfareast.com/hast_sys.htm

http://www.universalfareast.com/hast_sys.htm

41


Figure 3.4: (a) HAST system: the Trio Tech 6000X (b) the chamber of the Trio Tech 6000X

3.1.7 High Temperature Storage (HTS) [29]

High Temperature Storage test is performed to determine the effect of long-term

storage at elevated temperature without any electrical stresses applied. HTS is not

substitute for burn-in because it does not subject the sample to electrical stresses

(bias). This test is effective for testing the sample in terms of mechanism accelerated

by temperature only such as oxidation, bond and lead finish intermetallic growth, etc.

Any oven or chamber capable for providing controlled elevated temperature

can be used for HTS. It is similar to stabilization bake, except that HTS is done over a

much longer period of time at specific temperature. For example, HTS is conducted at

150°C for duration 1000 hours instead of 24 hours for stabilization bake. The purpose

of HTS is to assess the long-term reliability of devices under high temperature

conditions while that of stabilization bake is merely to serve as a preconditioning

treatment prior to conduct other tests.

The example of High Temperature Storage (HTS) test specification that used in semiconductor industry:

Mil Std 883, Method 1008, Stabilization Bake Specs: HTS

storage at a high temperature for a specified duration Test Condition A : 75 °C / 24 hours minimum Test Condition B : 125 °C / 24 hours minimum Test Condition C : 150 °C / 24 hours minimum Test Condition D : 200 °C / 24 hours minimum Test Condition E : 250 °C / 24 hours minimum Test Condition F : 300 °C / 24 hours minimum Test Condition G : 350 °C / 24 hours minimum Test Condition H : 400 °C / 24 hours minimum

42


4.0 Conclusions

Semiconductor devices had change the human world tremendously in this past few

year decades. They are the fundamental of electronic equipment for many applications

such as mobile phones, automobiles and computers. Its related technology is growing

in a rapid and unbelievable rate. The current semiconductor device is undergoes the

trend of miniaturization in size and complexity of device functions. Hence, this result

in more difficulties arises during the manufacturing of devices. The manufacturers

have the responsibility to ensure the quality for each batch of product is within the

safety limits. Otherwise, this would incur a huge lost if the device fail to perform as

intended.

As a result, reliability issue of the devices become the primary concern in all

the semiconductor industries. Reliability testing indirectly becomes the efficient tools

to assess and evaluate the performance of the manufactured devices. In addition,

semiconductor devices are manufactured in mass volume to gain economic scale of

benefits. The manufacturing of the device is high in complexity and involve multi-

step process. Any mishandling either by worker or the machine during the

manufacturing process could the whole batch of the devices to be failed. Thus,

reliability testing is important because these tests function as a mean to control and

monitor the whole process. The successful for the flow of manufacturing process is

depends greatly on the use of reliability testing.

43


5.0 References

1. Siliconfareast, 2006, What is semiconductor?, viewed 17 July 2010,

<http://www.siliconfareast.com/whatissemicon.htm>

2. STMicroelectronics, n.d, Introduction to Semiconductor Technology,

viewed 17 July 2010, <http://www.st.com/stonline/books/pdf/docs/5038.pdf>

3. Renesas, 2010, Logic Circuit Design/ Layout Design , viewed 17 July 2010,

<http://www2.renesas.com/fab/en/line/line1.html>

4. Dr. Seth P. Bates, 2000, Silicon Wafer Processing, viewed 17 July 2010,

<http://www.me.gatech.edu/jonathan.colton/me4210/waferproc.pdf>

5. Siliconfareast, 2006, Incoming Wafers, viewed 19 July 2010,

<http://www.siliconfareast.com/in_wafers.htm>

6. Siliconfareast, 2006, Single Crystal Growing for Wafer Production,

viewed 19 July 2010, <http://www.siliconfareast.com/crystal2.htm>

7. Michael Quirk & Julian Serda, Instructor’s Manual, viewed 19 July 2010,

<http://www.google.com.my/search?um=1&hl=en&q=Michael%20Quirk

%20%26%20Julian%20Serda%2C%20Instructor%E2%80%99s

%20Manua&ie=UTF-8&sa=N&tab=iw>

8. Siliconfareast, 2006, Chemical Vapor Deposition (CVD),

viewed 19 July 2010, < http://www.siliconfareast.com/cvd.htm>

9. Siliconfareast, 2006, Physical Vapor Deposition (PVD) by Sputtering,

viewed 19 July 2010,< http://www.siliconfareast.com/sputtering.htm>

10. Siliconfareast, 2006, Lithography/Etch, viewed 20 July 2010,

< http://www.siliconfareast.com/lith_etch.htm>

11. Siliconfareast, 2006, Diffusion, viewed 20 July 2010,

<http://www.siliconfareast.com/diffusion.htm>

12. Siliconfareast, 2006, Ion Implantation, viewed 20 July 2010,

<http://www.siliconfareast.com/implant.htm>

13. Siliconfareast, 2006, Glassivation, viewed 20 July 2010,

<http://www.siliconfareast.com/glassivation.htm>

14. Siliconfareast, 2006, WaferBackgrind, viewed 20 July 2010,

<http://www.siliconfareast.com/backgrind.htm>

15. Siliconfareast, 2006, Die Preparation, viewed 22 July 2010,

<http://www.siliconfareast.com/dieprep.htm>

http://www.siliconfareast.com/dieprep.htm

http://www.siliconfareast.com/implant.htm

http://www.siliconfareast.com/diffusion.htm

http://www.siliconfareast.com/lith_etch.htm

http://www.siliconfareast.com/sputtering.htm

http://www.google.com.my/search?um=1&hl=en&q=Michael%20Quirk%20%26%20Julian%20Serda%2C%20Instructor%E2%80%99s%20Manua&ie=UTF-8&sa=N&tab=iw



http://www.siliconfareast.com/in_wafers.htm

http://www2.renesas.com/fab/en/line/line1.html

http://www.siliconfareast.com/whatissemicon.htm

44


16. Siliconfareast, 2006, Die Attach Process, viewed 22 July 2010,

<http://www.siliconfareast.com/dieattach.htm>

17. Siliconfareast, 2006, Wire Bonding Process, viewed 22 July 2010,

<http://www.siliconfareast.com/wirebond.htm>

18. Siliconfareast, 2006, Molding/Plastic, viewed 23 July 2010,

<http://www.siliconfareast.com/molding.htm>

19. Siliconfareast, 2006, Semiconductor Reliability Engineering, viewed 23 July

2010, <http://www.siliconfareast.com/rel.html>

20. Siliconfareast, 2006, Temperature Cycle Test (TCT), viewed 23 July 2010,

<http://www.siliconfareast.com/TCT.htm>

21. Siliconfareast, 2006, Thermal Shock Test (TST),

viewed 23 July 2010, <http://www.siliconfareast.com/TST.htm>

22. Siliconfareast, 2006, Mechanical Shock Test - Mil-Std-883 Method 2002,

viewed 23 July 2010, <http://www.siliconfareast.com/mech-shock.htm>

23. Siliconfareast, 2006, Vibration Tests - Mil-Std-883 Methods 2005 and 2007,

viewed 23 July 2010, <http://www.siliconfareast.com/vibration-tests.htm>

24. Siliconfareast, 2006, Burn-in, viewed 23 July 2010

<http://www.siliconfareast.com/burnin.htm>

25. Siliconfareast, 2006, High Temperature Operating Life (HTOL) Test,

viewed 23 July 2010 <http://www.siliconfareast.com/HTOL.htm>

26. Siliconfareast, 2006, Low Temperature Operating Life (LTOL) Test,

viewed 23 July 2010, <http://www.siliconfareast.com/LTOL.htm>

27. Siliconfareast, 2006, Temperature, Humidity, Bias (THB) Test,

viewed 23 July 2010, <http://www.siliconfareast.com/THB.htm>

28. Siliconfareast, 2006, Highly Accelerated Stress Test (HAST), viewed 23 July

2010, <http://www.siliconfareast.com/HAST.htm>

29. Siliconfareast, 2006, High Temperature Storage (HTS) , viewed 23 July 2010

<http://www.siliconfareast.com/HTS.htm>

http://www.siliconfareast.com/HAST.htm

http://www.siliconfareast.com/THB.htm

http://www.siliconfareast.com/HTOL.htm

http://www.siliconfareast.com/vibration-tests.htm

http://www.siliconfareast.com/TST.htm

http://www.siliconfareast.com/TCT.htm

http://www.siliconfareast.com/rel.html

http://www.siliconfareast.com/wirebond.htm

http://www.siliconfareast.com/dieattach.htm

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