instruction set design by kip r. irvine (c) kip irvine, 2002-2003. all rights reserved. you may...

Instruction Set DesignInstruction Set Design

by Kip R. Irvine

(c) Kip Irvine, 2002-2003. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.

Revision date: 3/26/2003

Copyright 2002-2003, Irvine, Kip R. All rights reserved. 2

Instruction Set Design Factors *Instruction Set Design Factors *

• Operation types: how many operations to provide, and how complex should they be

• Data types: what data types will be supported?• Instruction format: length, number of operands,

fields sizes, etc.• Registers: number and type• Addressing modes: used when accessing memory

* Source: Stallings, William. Computer Organization and Architecture, 2002


Important ConsiderationsImportant Considerations

• Expansion – ability to add opcodes later• Technology changes

• speed of memory access versus register access

• changes in machine word size

• changes in common applications such as multimedia that have high bandwidth

• superscalar architecture

• cache memory


Intel ProcessorsIntel Processors

• Started with simple 8-bit processor (8086)• CPU was almost as slow as memory, so there were

few registers and frequent memory access

• no ability to overlap instructions

• 16-bit address fields

• Upgraded to 16-bit and 32-bit processors• CPU much faster than memory

• overlapped instruction execution

• 32-bit address fields

• had to remain backward-compatible with 8086


UltraSPARC II Instruction Set UltraSPARC II Instruction Set **

• All instructions are 32 bits• Each instruction is simple (single action)• Three-operand instructions:

• Example: Add R3,R1,R2 ; R3 = R1 + R2

• Load/Store: two registers, or register + constant• Example: Load R1,(R2+R3)

• Example: Stor (R2+200),R1

* Source: Tanenbaum, Andrew. Structured Computer Organization, 4th ed.


Machine InstructionMachine Instruction

• A machine instruction is represented by a sequence of bits

• Divided into fields:• opcode

• selector bits (operand size, type...)

• between 0 and 3 operands

opcode operand1 operand2


Types of InstructionsTypes of Instructions

• arithmetic• logical

• boolean, shift, test• data transfer• input-output• system control• transfer of control

• unconditional branch• conditional branch• subroutine call


Number of OperandsNumber of Operands

• Important factor in Processor Design• zero operands

• operands kept on stack

• one operand• accumulator is implied operand

• two operands• destination, source

• three operands• destination, source1, source2


Expression Example Expression Example (1 of 3)(1 of 3)

Translate the following expression into a sequence of three-operand instructions:

R1 = (R2 + R3) (R4 – R5)

add R1,R2,R3 ; R1 = R2 + R3

sub R6,R4,R5 ; R6 = R4 – R5

mul R1,R1,R6 ; R1 = R1 * R6

(R6 is used as a temporary operand)



Translate the following expression into a sequence of two-operand instructions:

R1 = (R2 + R3) (R4 – R5)

mov R1,R2 ; R1 = R2

add R1,R3 ; R1 = R2 + R3

mov R6,R4 ; R6 = R4

sub R6,R5 ; R6 = R4 – R5

mul R1,R6 ; R1 = R1 * R6

(R6 is used as a temporary operand)



Translate the following expression into a sequence of one-operand instructions: R1 = (R2 + R3) (R4 – R5)

load R4 ; acc = R4

sub R5 ; acc = acc – R5

store R6 ; R6 = acc

load R2 ; acc = R2

add R3 ; acc = acc + R3

mult R6 ; acc = acc * R6

store R1 ; R1 = acc

(accumulator is the implied first operand)


Operand TypesOperand Types

• register• immediate value• memory

• direct

• indirect

• indexed (offset + register)

• base-register (register + offset)

• relative (loop, conditional jump)

• logical data (bit mapped)


Direct AddressingDirect Addressing

• operand is an offset (displacement)

• offset is automatically dereferenced

• Example:• mov ax,(0A00)

• mov ax,(myWord)


Indirect AddressingIndirect Addressing

• operand is a register• register contains an offset• offset is automatically

dereferenced• Example:

• mov R1,(R2)


Indexed AddressingIndexed Addressing

• operands are offset + register• effective address (EA) calculated• EA dereferenced• Example:

• mov R1,(Array + R2)

(Array begins at 0200h)


Base-Register AddressingBase-Register Addressing

• operands are register + offset• register contains the base address

(of an array, for example)• offset is usually small• Example:

• mov R1,(R2+18)

Applications: stack parameters and structure fields


Conditional Jump ExampleConditional Jump Example

jne target

Encoding:

opcode: 110001

condition code: 00010

offset: 0020h

opcode cc offset

110001 00010 000000000000000100000


Designing the Instruction FormatDesigning the Instruction Format


Things to Think AboutThings to Think About

• Number of instructions• Instruction length

• fixed-length or variable length?• multiple of bus width desirable• benefit diminishes as length increases

• Number of operands• Size of addresses

• affects memory addressing ranges• address granularity (byte, word, doubleword)

• Addressing modes• greater number adds flexibility, increases complexity


Choosing an Address SizeChoosing an Address Size

• Address range affected by number of bits and granularity

• 16-bit address• byte addressable up to 64KB

• word addressable up to 128KB

• doubleword addressable up to 256KB

• 20-bit address• byte=1MB, word=2MB, dword=4MB

• 32-bit address• byte=4GB, word=8GB, dword=16GB


Machine Instruction FieldsMachine Instruction Fields

• Opcode field• n-bit opcode can represent 2n instructions• can vary in size

• Register operand• few bits needed (5 bits = 32 registers)

• Direct Operand• restricts addressable memory range

• Indirect Operand• same number of bits as register operand• wide range of addresses

• Immediate Operand• convenient use of constant values• usually less than instruction length


SIS DesignSIS Design

• SIS – Simple Instruction Set• All instructions are the same length• Opcodes vary in length (2 – 20 bits)• Registers are 5 bits (numbered 0-31)• Instructions have 0 – 3 operands• Only the load, store, conditional branch, and call

instructions contain memory offsets• Immediate operand only permitted in MOV instruction• Loosely patterned after MIPS *

* Patterson & Hennessey, Computer Organization and Design.


SIS FormatsSIS Formats (1 of 8) (1 of 8)

• Format 1: Zero operands• stc ; set Carry flag

• clc ; clear Carry flag

• ret ; return from procedure

20 12

opcode - -



• Format 2: Single register operand• push R2 ; push R2 onto top of stack

• pop R1 ; pop top of stack into R1

• inc (R1) ; increment indirect memory

• dec R5 ; decrement R5

20 5 7opcode reg - -



• Format 3: Three register operands• add R1,R2,R3 ; R1 = R2 + R3

• mul R2,R0,R4 ; R2 = R0 * R4

• shr R3,R4,R5 ; R3 = R4 >> R5

12 5 5 5 5opcode reg regreg - -



• Format 4: Load and Store• STW (myVal),R2 ; store word from R2

• LDW R4,(array) ; load word into R4

6 5 21

opcode reg offset



• Format 5: Register and immediate operands• mvi R1,0FFFFFh ; move immediate into R1

• adi R2,3742 ; add immediate to R2

• mvi R3,array ; move address into R3

• cmpi R6,5 ; compare R6 to immediate

opcode reg immediate

6 5 21



• Format 6: Conditional jump• jnz target

• ja loopTop

6 5 21opcode cond offset


Conditional Jump CodesConditional Jump Codes

Condition Codesequal 00001not equal: 00010above 00011below 00100above/equal 00101etc.

Important flags: C, S, Z, O, P



oc offset

• Format 7: Subroutine call

• call mySub

2 30



• Format 8: Two registers and displacement

• ldw R1,(R2+4) ; load R1 from offset R2+4

• stw (R2+8),R1 ; store R1 at offset R2+8

• ldb R1,(R2+4) ; load byte from memory

• stb (R2+8),R1 ; store byte to memory

6 5 5 16

opcode reg dispreg


Expanding OpcodesExpanding Opcodes


Example: Sum an ArrayExample: Sum an Array (1 of 2) (1 of 2)

.dataarray DWORD 5 DUP(?)sum DWORD ?

sum = 0;for( int i = 0; i < 5; i++ )

sum = sum + array[i];

Data:

C++/Java code:


Example: Sum an ArrayExample: Sum an Array (2 of 2) (2 of 2)

mvi R6,0 ; loop countermvi R1,0 ; accumulatormvi R2,array ; R2 points to the array

top:ldw R3,(R2) ; load word from memoryadd R1,R1,R3 ; R1 = R1 + R3adi R2,4 ; point to next integeradi R6,1 ; increment loop countercmp R6,5 ; check for end of loopjb top ; continue loop

stw (sum),R1 ; store sum in memory

Implementation:


The EndThe End

instruction set design by kip r. irvine (c) kip irvine, 2002-2003. all rights reserved. you may...

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