institut für angewandte mikroelektronik und datentechnik results of phase 4: layout for st65...

Institut fürAngewandte

Mikroelektronikund Datentechnik

Results of Phase 4:Layout for ST65 technology

byChristoph Niemann

11.12.2013

Selected Topics in VLSI Design

26.04.23 © 2013 UNIVERSITÄT ROSTOCK | Fakultät für Informatik und Elektrotechnik 1

Institute MD, University of Rostock





Content• Observations• Changes in Filterdesign • Frequency Response• Changes in Implementation• Synthesis and Layout• Picture of Chip Layout• Metric

26.04.23 2© 2013 UNIVERSITÄT ROSTOCK | Fakultät für Informatik und Elektrotechnik





Observations• Filter-design is not optimal (slew rate can be achieved with less

then 14 coefficients• Further optimisations in VHDL-Code are possible• Those vhdl optimisations might have an higher impact on the

results then advanced Layout-Options• Use different CPA to save Registers• Correction of the mean of truncation-error and addition of the lsb-

ones of the sign change in two’s complement is possible with a single correction vector






Changes in Filterdesign

•Creating a standart bandpass design with fdatool•Costumize with pole/zero editor•Check the design in MATLAB within a replicated test bench

•Order 10 fir filter•Reduces number of partial products from 26 to 13•Maximum 2 partial products per coefficient






Frequency Response






Changes in Implementation

•Correction of truncation error•Makes the use of 8 bit adders ans 7 bit registers posible•Saves 33% of the full-adders and 42% of the registers

altogether reducing of hardware by 60%






Synthesis and LayoutSythesis•Higher frequency due to changed design

Layout•Quadratic core•core to I/O pin spacing of 10µm•No further layout improvements






Picture of Chip Layout






Metric


Phase 3 Phase 4

Timing 0.9 ns 0.86 ns

Frequency 1111 MHz 1163 MHz

Dynamic Power 9.97 mW 3.0905 mW

Leakage Power 66.8 nW 21.4150 nW

Metric 2.06*1018 MHz3/W² 2.377*1019 MHz3/W²

Pipeline Stages 4 1

Core Size -- 4689.4

Core Utilization -- 90.0 %





Thank you for your attention!


institut für angewandte mikroelektronik und datentechnik results of phase 4: layout for st65...

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