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CS61C L18 Combinational Logic Blocks, Latches (1) Chae, Summer 2008 © UCB

Albert Chae, Instructor

inst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures

Lecture #18 – Combinational Logic Blocks,Latches

2008-7-22


Review

•Use this table and techniques welearned to transform from 1 to another


Today

•Common Combinational Logic Blocks

•Data Multiplexors•Arithmetic and Logic Unit•Adder/Subtractor


Data Multiplexor (here 2-to-1, n-bit-wide)

“mux”


N instances of 1-bit-wide muxHow many rows in TT?


How do we build a 1-bit-wide mux?


4-to-1 Multiplexor?How many rows in TT?


Is there any other way to do it?

Hint: March Madness

Ans: Hierarchically!


CP

Q

0

1

D

D C0 P1 Q

Do you really understand NORs?• If one input is 1, what is a NOR?• If one input is 0, what is a NOR?A B NOR0 0 10 1 01 0 01 1 0

A

BNOR

A NOR0 B’1 0A

_B

0NOR


CP

Q

0

1

D

D C0 P1 Q

Do you really understand NANDs?• If one input is 1, what is a NAND?• If one input is 0, what is a NAND?A B NAND0 0 10 1 11 0 11 1 0 A NAND

0 11 B’A

1_B

NAND

A

BNAND


Arithmetic and Logic Unit

•Most processors contain a speciallogic block called “Arithmetic andLogic Unit” (ALU)•We’ll show you an easy one that doesADD, SUB, bitwise AND, bitwise OR


Our simple ALU


Adder/Subtracter Design -- how?

• Truth-table, thendeterminecanonical form,then minimize andimplement as we’veseen before

• Look at breakingthe problem downinto smaller piecesthat we cancascade orhierarchically layer


Adder/Subtracter – One-bit adder LSB…


Adder/Subtracter – One-bit adder (1/2)…


Adder/Subtracter – One-bit adder (2/2)…


Administrivia

•HW4 Due Friday 7/25•Learn Logisim in the next few labs•Proj3 poll?•Complaints about HW1 and 2•Submit by Friday or we won’t look at it


N 1-bit adders ⇒ 1 N-bit adder

What about overflow?Overflow = cn?

+ + +b0


What about overflow?•Consider a 2-bit signed # & overflow:•10 = -2 + -2 or -1•11 = -1 + -2 only•00 = 0 NOTHING!•01 = 1 + 1 only

•Highest adder•C1 = Carry-in = Cin, C2 = Carry-out = Cout•No Cout or Cin ⇒ NO overflow!•Cin, and Cout ⇒ NO overflow!•Cin, but no Cout ⇒ A,B both > 0, overflow!•Cout, but no Cin ⇒ A,B both < 0, overflow!

± #

Whatop?


What about overflow?

•Consider a 2-bit signed # & overflow:10 = -2 + -2 or -111 = -1 + -2 only00 = 0 NOTHING!01 = 1 + 1 only

•Overflows when…•Cin, but no Cout ⇒ A,B both > 0, overflow!•Cout, but no Cin ⇒ A,B both < 0, overflow!

± #


Extremely Clever Subtractor


Taking advantage of sum-of-products

•Since sum-of-products is aconvenient notation and way to thinkabout design, offer hardware buildingblocks that match that notation•One example isProgrammable Logic Arrays (PLAs)•Designed so that can select (program)ands, ors, complements after you getthe chip• Late in design process, fix errors, figureout what to do later, …


• • •

inputs

ANDarray

• • •

outputs

ORarrayproduct

terms

Programmable Logic Arrays• Pre-fabricated building block of many

AND/OR gates• “Programmed” or “Personalized" by making or

breaking connections among gates• Programmable array block diagram for sum of

products form

And Programming:• How many inputs?• How to combine inputs?• How many product terms?

Or Programming:• How to combine product terms?• How many outputs?


example:

F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

personality matrix1 = uncomplemented in term0 = complemented in term– = does not participate

1 = term connected to output0 = no connection to output

input side: 3 inputs

output side: 4 outputsProduct inputs outputsterm A B C F0 F1 F2 F3

AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1 reuse of terms;

5 product terms

Enabling Concept

•Shared product terms among outputs


Before Programming

•All possible connections available before“programming”


A B C

F1 F2 F3F0

AB

B'C

AC'

B'C'

A

After Programming• Unwanted connections are "blown"

• Fuse (normally connected, break unwantedones)• Anti-fuse (normally disconnected, make wanted

connections)


notation for implementingF0 = A B + A' B'F1 = C D' + C' D

AB+A'B'CD'+C'D

AB

A'B'

CD'

C'D

A B C D

Alternate Representation

• Short-hand notation--don't have to draw allthe wires• X Signifies a connection is present and

perpendicular signal is an input to gate


Peer Instruction

A. Truth table for mux with 4-bits ofselect signal has 24 rows

B. We could cascade N 1-bit shiftersto make 1 N-bit shifter for sll, srl

C. If 1-bit adder delay is T, the N-bitadder delay would also be T

ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT


Peer Instruction Answer

A. Truth table for mux with 4-bits ofsignals is 24 rows long

B. We could cascade N 1-bit shiftersto make 1 N-bit shifter for sll, srl

C. If 1-bit adder delay is T, the N-bitadder delay would also be T

ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT

A. Truth table for mux with 4-bits of signalscontrols 16 inputs, for a total of 20inputs, so truth table is 220 rows…FALSE

B. We could cascade N 1-bit shifters tomake 1 N-bit shifter for sll, srl … TRUE

C. What about the cascading carry? FALSE


Combinational Logic from 10 miles up

•CL circuits simply compute a binaryfunction (e.g., from truthtable)•Once the inputs go away, the outputsgo away, nothing is saved, no STATE•Similar to a function in Scheme with noset! or define to save anything

•How does the computer rememberdata? [e.g., for registers]

XY

XY

Z(define (xor x y) (or (and (not x) y) (and x (not y))))


State Circuits Overview

• State circuits have feedback, e.g.

•Output is function ofinputs + fed-back signals.• Feedback signals are the circuit's state.•What aspects of this circuit might cause

complications?

lab 12

counter

in0

in1

out0

out1

Combi-national

Logic


A simpler state circuit: two inverters

•When started up, it's internally stable.•Provide an or gate for coordination:

•What's the result?

0 1 0

0 1 0

0

0

0

1!

1

1 01 1

How do we set to 0?


0

Hold!

An R-S latch (cross-coupled NOR gates)•S means “set” (to 1),R means “reset” (to 0).

•Adding Q’ gives standard RS-latch:Truth tableS R Q0 0 hold (keep value)0 1 01 0 11 1 unstable

A B NOR0 0 10 1 01 0 01 1 0_

Q0 1 0

0

0

1

1 01 110

0

0 10 01

0 1Hold!

0


An R-S latch (in detail)

Truth table _S R Q Q Q(t+Δt)0 0 0 1 0 hold0 0 1 0 1 hold0 1 0 1 0reset0 1 1 0 0reset1 0 0 1 1 set1 0 1 0 1 set1 1 0 x xunstable1 1 1 x xunstable

A B NOR0 0 10 1 01 0 01 1 0


Controlling R-S latch with a clock

•Can't change R and S while clock isactive.

•Clocked latches are called flip-flops.

clock'

S'Q'

QR' R

S

A B NOR0 0 10 1 01 0 01 1 0


D flip-flop are what we really use• Inputs C (clock) and D.•When C is 1, latch open, output = D(even if it changes, “transparent latch”)•When C is 0, latch closed,output = stored value.

C D AND0 0 00 1 01 0 01 1 1


D flip-flop details•We don’t like transparent latches•We can build them so that the latch isonly open for an instant, on the risingedge of a clock (as it goes from 0⇒1)

DCQTiming Diagram


“And In conclusion…”

•Use muxes to select among input•S input bits selects 2S inputs•Each input can be n-bits wide, indep of S

•Can implement muxes hierarchically•ALU can be implemented using a mux•Coupled with basic block elements

•N-bit adder-subtractor done using N 1-bit adders with XOR gates on input•XOR serves as conditional inverter

•Latches are used to implement flip-flops

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